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Renaming all BSP specific startXXX directories to use the same name (start).

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This commit is contained in:
Joel Sherrill
1999-11-19 16:22:09 +00:00
parent 149f3f9642
commit 9c0385aaa9
17 changed files with 0 additions and 4067 deletions
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60
c/src/lib/libbsp/m68k/efi332/start332/Makefile.in
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@@ -1,60 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/efi332/start332
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGM = ${ARCH}/start332.o
# C source names, if any, go here -- minus the .c
C_PIECES = start332
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
SRCS = $(C_FILES) $(H_FILES)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGM} $(PROJECT_RELEASE)/lib
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

227
c/src/lib/libbsp/m68k/efi332/start332/start332.c
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@@ -1,227 +0,0 @@
/*
* $Id
*/
#include <efi332.h>
#include <sim.h>
#define __START_C__
#include "bsp.h"
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
void boot_card(int argc, char * const argv[]);
/*
* This prototype really should have the noreturn attribute but
* that causes a warning. Not sure how to fix that.
*/
/* void dumby_start () __attribute__ ((noreturn)); */
void dumby_start ();
void dumby_start() {
/* We need to by-pass the link instruction since the RAM chip-
select pins are not yet configured. */
asm volatile ( ".global start ;
start:");
/* disable interrupts, load stack pointer */
asm volatile ( "oriw #0x0700, %sr;
moveal #M68Kvec, %a0;
movec %a0, %vbr;
movel #_end, %d0;
addl " STACK_SIZE ",%d0;
movel %d0,%sp;
movel %d0,%a6"
);
/* include in ram_init.S */
/*
* Initalize the SIM module.
* The stack pointer is not usable until the RAM chip select lines
* are configured. The following code must remain inline.
*/
/* Module Configuration Register */
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
*SIMCR = (unsigned short int)
(FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
/* Synthesizer Control Register */
/* see section(s) 4.8 */
/* end include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
/* include in ram_init.S */
*SYNCR = (unsigned short int)
( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
/* System Protection Control Register */
/* !!! can only write to once after reset !!! */
/* see section 3.8.4 of the SIM Reference Manual */
*SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
/* Periodic Interrupr Control Register */
/* see section 3.8.2 of the SIM Reference Manual */
*PICR = (unsigned short int)
( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
/* ^^^ zero disables interrupt, don't enable here or ram_init will
be wrong. It's enabled below. */
/* Periodic Interrupt Timer Register */
/* see section 3.8.3 of the SIM Reference Manual */
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
/* 1.098mS interrupt */
/* Port C Data */
/* load values before enabled */
*PORTC = (unsigned char) 0x0;
/* Chip-Select Base Address Register */
/* see section 7 of the SIM Reference Manual */
*CSBARBT = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR0 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */
*CSBAR1 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR2 = (unsigned short int)
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
*CSBAR3 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
*CSBAR4 = (unsigned short int)
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */
*CSBAR5 = (unsigned short int)
(0xfff8 | BS_64K); /* AVEC interrupts */
#ifdef EFI332_v040b
*CSBAR6 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
*CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
(((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
*CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
(((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
#else /* EFI332_v040b */
*CSBAR10 = (unsigned short int)
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
#endif /* EFI332_v040b */
/* Chip-Select Options Registers */
/* see section 7 of the SIM Reference Manual */
#ifdef FLASHWRITE
*CSORBT = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace );
#else /* FLASHWRITE */
*CSORBT = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace );
#endif /* FLASHWRITE */
*CSOR0 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR1 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR2 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR3 = (unsigned short int)
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR4 = (unsigned short int)
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
*CSOR5 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
#ifdef EFI332_v040b
*CSOR6 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
*CSOR8 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
*CSOR9 = (unsigned short int)
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
#else /* EFI332_v040b */
*CSOR10 = (unsigned short int)
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
#endif /* EFI332_v040b */
/* Chip Select Pin Assignment Register 0 */
/* see section 7 of the SIM Reference Manual */
*CSPAR0 = (unsigned short int)(
SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */
SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */
SAM(CS16bit,CS_0,0x000c)| /* W/!R */
SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
);
/* Chip Select Pin Assignment Register 1 */
/* see section 7 of the SIM Reference Manual */
#ifdef EFI332_v040b
*CSPAR1 = (unsigned short int)(
SAM(DisOut,CS_10,0x300)| /* ECLK */
SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */
SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(CS16bit,CS_6,0x003) /* ROM !OE */
);
#else /* EFI332_v040b */
*CSPAR1 = (unsigned short int)(
SAM(CS16bit,CS_10,0x300)| /* ROM !OE */
SAM(DisOut,CS_9,0x0c0) | /* PC6 */
SAM(DisOut,CS_8,0x030) | /* PC5 */
SAM(DisOut,CS_7,0x00c) | /* PC4 */
SAM(DisOut,CS_6,0x003) /* PC3 */
);
#endif /* EFI332_v040b */
/* Port E and F Data Register */
/* see section 9 of the SIM Reference Manual */
*PORTE0 = (unsigned char) 0;
*PORTF0 = (unsigned char) 0;
/* Port E and F Data Direction Register */
/* see section 9 of the SIM Reference Manual */
*DDRE = (unsigned char) 0xff;
*DDRF = (unsigned char) 0xfd;
/* Port E and F Pin Assignment Register */
/* see section 9 of the SIM Reference Manual */
*PEPAR = (unsigned char) 0;
*PFPAR = (unsigned char) 0;
/* end of SIM initalization code */
/* end include in ram_init.S */
/*
* Initialize RAM by copying the .data section out of ROM (if
* needed) and "zero-ing" the .bss section.
*/
{
register char *src = _endtext;
register char *dst = _sdata;
if (_copy_data_from_rom)
/* ROM has data at end of text; copy it. */
while (dst < _edata)
*dst++ = *src++;
/* Zero bss */
for (dst = __bss_start; dst< _end; dst++)
*dst = 0;
}
/*
* Initalize the board.
*/
Spurious_Initialize();
console_init();
/*
* Execute main with arguments argc and agrv.
*/
boot_card(1,__argv);
reboot();
}

60
c/src/lib/libbsp/m68k/efi68k/start68k/Makefile.in
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@@ -1,60 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/efi68k/start68k
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGM = ${ARCH}/start68k.o
# C source names, if any, go here -- minus the .c
C_PIECES = start68k
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
SRCS = $(C_FILES) $(H_FILES)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGM} $(PROJECT_RELEASE)/lib
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

71
c/src/lib/libbsp/m68k/efi68k/start68k/start68k.c
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@@ -1,71 +0,0 @@
/*
* $Id$
*/
#include <efi68k.h>
#define __START_C__
#include "bsp.h"
m68k_isr_entry M68Kvec[256];
m68k_isr_entry vectors[256];
char * const __argv[]= {"main", ""};
char * const __env[]= {""};
/*
* This prototype really should have the noreturn attribute but
* that causes a warning since it appears that the routine does
* return.
*
* void dumby_start () __attribute__ ((noreturn));
*/
void dumby_start ();
void dumby_start() {
void boot_card();
/* We need to by-pass the link instruction since the RAM chip-
select pins are not yet configured. */
asm volatile ( ".global start ;
start:");
/* disable interrupts, load stack pointer */
asm volatile ( "oriw #0x0700, %sr;
movel #_end, %d0;
addl " STACK_SIZE ",%d0;
movel %d0,%sp;
link %a6, #0"
);
/*
* Initialize RAM by copying the .data section out of ROM (if
* needed) and "zero-ing" the .bss section.
*/
{
register char *src = _endtext;
register char *dst = _sdata;
if (_copy_data_from_rom)
/* ROM has data at end of text; copy it. */
while (dst < _edata)
*dst++ = *src++;
/* Zero bss */
for (dst = __bss_start; dst< _end; dst++)
*dst = 0;
}
/*
* Initalize the board.
*/
Spurious_Initialize();
console_init();
watch_dog_init();
tcp_init();
/*
* Execute main with arguments argv and environment env
*/
/* main(1, __argv, __env); */
boot_card();
reboot();
}

68
c/src/lib/libbsp/m68k/gen68302/start302/Makefile.in
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@@ -1,68 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/gen68302/start302
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGMS = ${ARCH}/start302.o
# C source names, if any, go here -- minus the .c
C_PIECES =
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
# Assembly source names, if any, go here -- minus the .S
S_PIECES = start302
S_FILES = $(S_PIECES:%=%.S)
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
SRCS = $(C_FILES) $(H_FILES) $(S_FILES)
OBJS = $(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGMS} $(PROJECT_RELEASE)/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL_CHANGE)
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

266
c/src/lib/libbsp/m68k/gen68302/start302/start302.S
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@@ -1,266 +0,0 @@
/* entry.s
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include "asm.h"
.set BAR, 0xF2 | Base Address Register location
.set SCR, 0xF4 | System Control Register location
.set BAR_VAL, 0x0f7f | BAR value
.set SCR_VAL, 0x00080f00 | SCR value
.set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN).
.set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address
.set oSYSRAM, 0x000 | 576 bytes of internal system RAM
.set oGIMR, 0x812
.set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg
.set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg
.set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg
.set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg
.set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg
.set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg
.set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg
.set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg
.set tmpSRAM_BASE, 0x400000 | start of temporary SRAM
.set FLASH_BASE, 0xc00000 | start of FLASH''s normal location
BEGIN_CODE
PUBLIC (M68Kvec) | Vector Table
SYM (M68Kvec): | standard location for vectors
V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP
V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC
V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error
V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error
.space 240 | reserve space for reset of vectors
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
SYM (lowintstack):
.space 4092 | reserve for interrupt stack
SYM (hiintstack):
.space 4 | end of interrupt stack
#endif
PUBLIC (start) | Default entry point for GNU
SYM (start):
move.w #0x2700,sr | Disable all interrupts
move.w #BAR_VAL,BAR | Set Base Address Register
move.l #SCR_VAL,SCR | Set System Control Register
lea BaseAddr,a5
move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register
|
| Set up chip select registers for the remapping process.
|
|
| 0 X x x x x
| 0 000 0 0-- - --- ---- ---- ----
| x xxx x xxx x xx
|
move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH)
move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS
|
| X x x x x x
| 0 100 0 0-- - --- ---- ---- ----
| x xxx x xxx x xx
|
move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM)
move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS
|
| Copy the initial boot FLASH area to the temporary SRAM location.
|
moveq #0,d0
movea.l d0,a0 | a0 -> start of FLASH
lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM
| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy
moveq #127,d0
cpy_flash: move.l (a0)+,(a1)+ | copy
subq.l #1,d0
bne cpy_flash
|
| Copy remap code to 68302''s internal system RAM.
|
movea.w #begRemap-V___ISSP,a0 | a0 -> remap code
lea a5@(oSYSRAM),a1 | a1 -> internal system RAM
| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy
moveq #11,d0
cpy_remap: move.w (a0)+,(a1)+ | copy
dbra d0,cpy_remap
|
| Jump to the remap code in the 68302''s internal system RAM.
|
jmp a5@(oSYSRAM) | (effectively a jmp begRemap)
|
| This remap code, when executed from the 68302''s internal system RAM
| will 1) remap CS1 so that SRAM is at 0
| 2) remap CS0 so that FLASH is at FLASH_BASE
| and 3) jump to executable code in the remapped FLASH.
|
begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM)
move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH)
lea FLASH_BASE,a0
jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH
endRemap:
|
| Now set up the remaining chip select registers.
|
|
| 4 0 x x x x
| 1 000 1 111 0 000 0--- ---- ----
| x xxx x xxx x xx
|
move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM)
move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS
|
| 8 X x x x x
| 1 000 0 0-- - --- ---- ---- ----
| x xxx x xxx x xx
|
move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO)
move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS
endPreBoot:
move.b #0x30,0x800001 | set status LED amber
.set oPIOB_Ctrl, 0x824
.set oPIOB_DDR, 0x826
.set oPIOB_Data, 0x828
.set oPIOA_Ctrl, 0x81e
.set oPIOA_DDR, 0x820
.set oPIOA_Data, 0x822
move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors.
move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output.
move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated
| peripheral pins.
move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors.
move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output.
move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated
| peripheral pins.
|
| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4
| are not set because they are the 68302''s BAR and SCR.
|
movea.w #0x010,a0
moveq #(0x0f0-0x010)/4-1,d0
move.l #Bad,d1
cpy_Bad: move.l d1,(a0)+
dbra d0,cpy_Bad
.set vbase, 0x0200
lea vbase,a0
moveq #31,d0
cpy_Bad1: move.l d1,(a0)+
dbra d0,cpy_Bad1
|
| Fill in special locations to configure OS
|
move.l #Bad,0x008 | Bus Error
move.l #Bad,0x00c | Address Error
move.l #Bad,0x024 | Trace
| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call
| move.l #_cnsl_isr,vbase+0x028 | SCC2
move.l #timerisr,vbase+0x018 | Timer ISR
|
| zero out uninitialized data area
|
zerobss:
moveal # SYM (end),a0 | find end of .bss
moveal # SYM (bss_start),a1 | find beginning of .bss
moveq #0,d0
loop: movel d0,a1@+ | to zero out uninitialized
cmpal a0,a1
jlt loop | loop until _end reached
movel # SYM (end),d0 | d0 = end of bss/start of heap
addl # SYM (heap_size),d0 | d0 = end of heap
movel d0, SYM (stack_start) | Save for brk() routine
addl # SYM (stack_size),d0 | make room for stack
andl #0xffffffc0,d0 | align it on 16 byte boundary
movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!!
movel d0,a7 | set master stack pointer
movel d0,a6 | set base pointer
/*
* RTEMS should maintain a separate interrupt stack on CPUs
* without one in hardware. This is currently not supported
* on versions of the m68k without a HW intr stack.
*/
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
lea SYM (hiintstack),a0 | a0 = high end of intr stack
movec a0,isp | set interrupt stack
#endif
move.l #0,a7@- | environp
move.l #0,a7@- | argv
move.l #0,a7@- | argc
jsr SYM (boot_card)
nop
Bad: bra Bad
nop
END_CODE
BEGIN_DATA
PUBLIC (start_frame)
SYM (start_frame):
.space 4,0
PUBLIC (stack_start)
SYM (stack_start):
.space 4,0
END_DATA
BEGIN_BSS
PUBLIC (environ)
.align 2
SYM (environ):
.long 0
PUBLIC (heap_size)
.set SYM (heap_size),0x2000
PUBLIC (stack_size)
.set SYM (stack_size),0x1000
END_DATA
END

68
c/src/lib/libbsp/m68k/gen68340/start340/Makefile.in
View File

@@ -1,68 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/gen68340/start340
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGMS = ${ARCH}/start340.o
# C source names, if any, go here -- minus the .c
C_PIECES =
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
# Assembly source names, if any, go here -- minus the .S
S_PIECES = start340
S_FILES = $(S_PIECES:%=%.S)
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
SRCS = $(C_FILES) $(H_FILES) $(S_FILES)
OBJS = $(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGMS} $(PROJECT_RELEASE)/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL_CHANGE)
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

873
c/src/lib/libbsp/m68k/gen68340/start340/start340.S
View File

@@ -1,873 +0,0 @@
/*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
#include "asm.h"
#include <m68349.inc>
#define _OLD_ASTECC 1 /* old addresses for AST68340 only, undefine for AST68349 */
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m340)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
move.w (a7),_boot_panic_registers+4 | SR
move.l 2(a7),_boot_panic_registers | PC
move.w 6(a7),_boot_panic_registers+6 | format & vector
movem.l d0-d7/a0-a7, _boot_panic_registers+8
movec sfc, d0
movem.l d0, _boot_panic_registers+72
movec dfc, d0
movem.l d0, _boot_panic_registers+76
movec vbr, d0
movem.l d0, _boot_panic_registers+80
jmp SYM(_dbug_dumpanic)
bra.s _crt0_cold_start
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
BEGIN_DATA
/* equates */
.equ _CPU340, 0x0
.equ _CPU349, 0x31
#ifdef _OLD_ASTECC /* old addresses for AST68340 only */
.equ _EPLD_CS_BASE, 0x1
.equ _PROM_Start, 0x01000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x10000000 /* SRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#else /* new addresses for AST68349 and 68340 */
.equ _EPLD_CS_BASE, 0x5
.equ _PROM_Start, 0x50000000 /* CS0 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x0c000000 /* CS3 */
.equ _BCCram_Start, 0x00000000 /* CS1 64 Kbytes */
.equ _BCCram_Size, 0x00010000 /* CS1 64 Kbytes */
.equ _ExtRam_Start, 0x80000000 /* DRAM */
.equ _ExtRam_Size, 0x00400000 /* 4 Mbytes */
.equ _FastRam_Start, 0x00000000 /* overlap /CS1 for the first 4 Kbytes */
.equ _FastRam_Size, 0x00001000 /* 4 Kbytes */
#endif
.equ _SPEED349, 0xD680 /* 24 Mhz */
.equ _SPEED340, 0xD700 /* 25 Mhz */
/* .equ _SPEED340, 0xCE00 16 Mhz */
#define crt0_boot_type d0 /* cold/warm start (must be D0) */
#define crt0_temp d1
#define crt0_cpu_type d2
#define crt0_csswitch d3
#define crt0_buswidth d4
#define crt0_pdcs d5
#define crt0_spare6 d6
#define crt0_spare7 d7
#define crt0_sim_base a0
#define crt0_glue a1
#define crt0_dram a2
#define crt0_ptr3 a3
#define crt0_ptr4 a4
#define crt0_ptr5 a5
#define crt0_ptr6 a6
/* -- PDCS buffer equates -- */
.equ pdcs_mask, 0x1F /* DRAM configuration */
.equ pdcs_sw12, 7 /* switch 12 */
.equ pdcs_sw11, 6 /* switch 11 */
.equ pdcs_sw14, 5 /* switch 14 */
.equ bit_cache, pdcs_sw12 /* enable cache if on */
.equ bit_meminit, pdcs_sw11 /* init memory if on */
/* -- Initialization stack and vars -- */
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
_AsteccCpuName: ds.l 1
.align 4
_crt0_init_stack:
ds.l 500
_crt0_init_stktop:
/* -- Initialization code -- */
BEGIN_CODE
.align 4
dc.l _crt0_init_stktop /* reset SP */
dc.l _crt0_cold_start /* reset PC */
dc.l _crt0_warm_start
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards"
dc.w 0
.align 4
.globl start
start:
_crt0_cold_start:
moveq.l #0,crt0_boot_type | signal cold reset
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,crt0_boot_type | signal warm reset
_crt0_common_start:
move.w #0x2700,sr | disable interrupts and switch to interrupt mode
movea.l #_crt0_init_stktop,sp | set up initialization stack
move.l #Entry,crt0_temp | VBR initialization
movec.l crt0_temp,vbr |
moveq.l #0x07,crt0_temp
movec.l crt0_temp,dfc | prepare access in CPU space
move.l #(BASE_SIM+0x111),crt0_temp | mask CPU, RESERVED USER SPACES
moves.l crt0_temp,BASE_REG | base initialization (must be MOVES, PCC-130795)
movea.l #BASE_SIM,crt0_sim_base
/* -- disable Bus Monitor -- */
move.b #0,SIM_SYPCR(crt0_sim_base) | system protection control register
/* -- enable A31-A24 -- */
clr.b SIM_PPRA1(crt0_sim_base)
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
move.w #0x427F,SIM_MCR(crt0_sim_base)
/* -- enable /IRQ3, 5, 6, 7 -- */
move.b #0xE8,SIM_PPRB(crt0_sim_base)
/* -- enable autovector on /IRQ7 -- */
move.b #0x80,SIM_AVR(crt0_sim_base)
/* -- test CPU type -- */
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne cpu_is_68340
/*-------------------------------------------------------------------------------------------*/
cpu_is_68349:
/* -- set cpu clock -- */
move.w #_SPEED349,SIM_SYNCR(crt0_sim_base) | clock
sync_wait349:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait349
/* to allow access to the EPLD internal registers, it is necessary
to disable the global chip-select /CS0 (which decodes every external
cycles). To do that, we initialize the 68349 internal RAM,
copy a part of the initialization code in it, and jump there.
from that moment, /CS0 is not used, therefore it can be initialized
with its default value. Its width may be incorrect, but it will be
adjusted later. The goal is to avoid any conflict with
the accesses to the EPLD registers.
When this is done, we read the RESET parameters (boot prom width
and chip-select switch) and proceed with the initialization
when all is done, we jump back to the boot prom now
decoded with a properly configured /CS0 */
/*-------------------------------------*/
/* -- configure internal SRAM banks -- */
move.l #0x00000000,QDMM_MCR(crt0_sim_base)
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(crt0_sim_base)
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(crt0_sim_base)
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(crt0_sim_base)
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(crt0_sim_base)
/*--------------------------------------------------------*/
/* -- copy to address of the 68349 initialization code -- */
lea.l _copy_start(%pc),crt0_ptr3
lea.l _copy_end(%pc),crt0_ptr4
move.l crt0_ptr4,crt0_temp
sub.l crt0_ptr3,crt0_temp
add.l #3,crt0_temp | adjust to next long word
lsr.l #2,crt0_temp
move.l #_FastRam_Start,crt0_ptr4
_copy_loop:
move.l (crt0_ptr3)+,(crt0_ptr4)+
subq.l #1,crt0_temp
bne.s _copy_loop
bra.l _FastRam_Start | jump to code in internal RAM
/*------------------------------------*/
/* -- start of initialization code -- */
_copy_start:
bra.l _begin_68349_init
/*----------------------------------------------------------*/
/* Astecc 68349 board : chip-select initialization values */
_table_csepld:
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
dc.b 0x80 | 16 bits, 0 ws
dc.b 0x90 | 16 bits, ext /dsack
dc.b 0x90 | 16 bits, ext /dsack
_table_cs349:
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
/*-------------------------------------------------*/
_begin_68349_init:
/*-------------------------------------------------*/
/* 68349 chip select initialization
at this stage, the width of /CS0 may be incorrect
it will be corrected later
*/
_cs68349_init:
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_cs349_init2:
move.l (crt0_ptr3)+,(crt0_ptr4)+
dbra crt0_temp,_cs349_init2
/*-----------------------------------------------*/
/* -- prepare access to the internal registers --*/
moveq.l #EPLD_SPACE,crt0_temp
movec.l crt0_temp,dfc
movec.l crt0_temp,sfc
move.l #GLUE_EPLD,crt0_glue
move.l #DRAM_EPLD,crt0_dram
/*-------------------------------------------*/
/* EPLD generated /CS[3..0] must be disabled */
_csepld_clear:
move.l crt0_glue,crt0_ptr4
move.w #3,crt0_spare6
clr.b crt0_temp
_csepld_clear1:
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld_clear1
/*---------------------------------------------------------*/
/* -- get width of boot PROM, and active chip-select set --*/
moves.b REG_BUSWIDTH(crt0_dram),crt0_csswitch
move.b crt0_csswitch,crt0_buswidth
/* state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
: sel == 1 => EPLD chip_selects (/CS[3..0]) */
and.b #1,crt0_csswitch
/* bus width of /CS0 during reset bw[1..0] : 0 1 2 3
bus width : 32 16 8 ext./dsackx */
rol.b #2,crt0_buswidth
and.b #3,crt0_buswidth
/*----------------------------------------------------*/
/* -- configure chip select 0 with boot prom width -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
move.l (crt0_ptr3)+,crt0_temp
and.b #0xFC,crt0_temp | clear PS0 & PS1
or.b crt0_buswidth,crt0_temp | set boot PROM bus width
move.l crt0_temp,(crt0_ptr4)+
/*------------------------*/
/* -- read PDCS buffer -- */
moves.b REG_PDCS(crt0_glue),crt0_pdcs
/* move.b #0x3F,crt0_pdcs pour test */
/*---------------------------------------*/
/* -- EPLD chip-select initialization -- */
/*---------------------------------------*/
btst.b #0,crt0_csswitch
beq _cs_init_end
/*--------------------------------------------*/
/* 68349 generated /CS[3..0] must be disabled */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs349(%pc),crt0_ptr3
moveq.l #0x03,crt0_temp
_cs349_clear:
move.l (crt0_ptr3)+,(crt0_ptr4)+
move.l (crt0_ptr3)+,crt0_spare6
and.b #0xFE,crt0_spare6 | disable chip-select
move.l crt0_spare6,(crt0_ptr4)+
dbra crt0_temp,_cs349_clear
/*---------------------------------------------*/
/* EPLD generated /CS[3..0] must be configured */
_csepld_init:
move.l crt0_glue,crt0_ptr4
lea.l _table_csepld(%pc),crt0_ptr3
move.b (crt0_ptr3)+,crt0_temp
or.b #0x20,crt0_temp | default width is 32 bits
tst.b crt0_buswidth | is boot PROM bus width 32 bits ?
beq _csepld1 | if not
and.b #0xDF,crt0_temp | set width to 16 bits
_csepld1:
moves.b crt0_temp,(crt0_ptr4)+
moveq.l #0x02,crt0_spare6
_csepld2:
move.b (crt0_ptr3)+,crt0_temp
moves.b crt0_temp,(crt0_ptr4)+
dbra crt0_spare6,_csepld2
_cs_init_end:
/*--------------------------------------*/
/* -- DRAM controller initialization -- */
_dram_init:
move.w #15,crt0_temp
move.l #_ExtRam_Start,crt0_ptr3
_dram_init1:
clr.l (crt0_ptr3)+ | must access DRAM
dbra crt0_temp,_dram_init1 | prior to init refresh
_dram_init2:
move.b #3,crt0_temp
moves.b crt0_temp,REG_WS(crt0_dram) | set 3 wait-states
move.b #0x81,crt0_temp
moves.b crt0_temp,REG_REFRESH(crt0_dram) | refresh every 10<EFBFBD>s
move.b #0,crt0_temp
moves.b crt0_temp,REG_CONFIG(crt0_dram) | default size = 4Mbytes
/*-----------------------*/
/* -- configure cache -- */
_init_cache:
move.l #0x000001E0,CACHE_MCR(crt0_sim_base)
btst.b #bit_cache,crt0_pdcs
bne _init_cache_end
or.l #0x00000001,CACHE_MCR(crt0_sim_base)
_init_cache_end:
/*-----------------------------*/
/* -- timers initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_TIMER1(crt0_glue) | disable timer 1
moves.b crt0_temp,REG_TIMER2(crt0_glue) | disable timer 2
/*--------------------------*/
/* -- I2C initialization -- */
move.b #3,crt0_temp
moves.b crt0_temp,REG_I2C(crt0_glue) | tri-states I2C ports
/*-----------------------------------------*/
/* -- baudrate generator initialization -- */
move.b #2,crt0_temp
moves.b crt0_temp,REG_BAUDRATE(crt0_glue) | baudrate = 38400
/*-------------------------------*/
/* -- IO port initialization -- */
clr.b crt0_temp
moves.b crt0_temp,REG_IO(crt0_glue) | set port as input
/* -- */
move.l #68349,crt0_cpu_type
/* -- jump back to PROM -- */
jmp.l (_fill_test) | must be absolute long
_copy_end:
/*-------------------------------------------------
initialization code for the 68340 board
-------------------------------------------------*/
/* Astecc 68340 board : chip-select initialization values */
_table_cs340:
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
cpu_is_68340:
/* -- set cpu clock -- */
move.w #_SPEED340,SIM_SYNCR(crt0_sim_base) | clock
sync_wait340:
btst.b #3,(SIM_SYNCR+1)(crt0_sim_base)
beq sync_wait340
/* -- chip select initialization -- */
lea.l SIM_MASKH0(crt0_sim_base),crt0_ptr4
lea.l _table_cs340(%pc),crt0_ptr3
moveq.l #0x07,crt0_temp
_b_cs340:
move.l (crt0_ptr3)+,crt0_ptr5
move.l crt0_ptr5,(crt0_ptr4)+ | pour test
dbra crt0_temp,_b_cs340
move.l #68340,crt0_cpu_type
move.b #0,crt0_csswitch | CPU
move.b #1,crt0_buswidth | 16 bits
/*-------------------------------------------------
fill RAM if COLDSTART
-------------------------------------------------*/
_fill_test:
tst.l crt0_boot_type
bne _dont_fill
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill
btst.b #bit_meminit,crt0_pdcs
bne _dont_fill
/* fill main memory */
_fill:
move.l #_crt0_init_stack,crt0_ptr3 | skip Astecc vars
move.l #_ExtRam_Start,crt0_temp
sub.l #_crt0_init_stack,crt0_temp
add.l #_ExtRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_fill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _fill_loop
cmp.b #_CPU349,SIM_IDR(crt0_sim_base)
bne _fill_bccram
/* fill QDMM memory */
movea.l #_FastRam_Start,crt0_ptr3 | get start
move.l #_FastRam_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_QDMMfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _QDMMfill_loop
bra _dont_fill
/* fill BCC memory */
_fill_bccram:
movea.l #_BCCram_Start,crt0_ptr3 | get start
move.l #_BCCram_Size,crt0_temp | get size
lsr.l #2,crt0_temp | ajust for long word
_BCCfill_loop:
clr.l (crt0_ptr3)+
subq.l #1,crt0_temp
bne _BCCfill_loop
*-------------------------------------------------*/
_dont_fill:
move.b crt0_csswitch,_AsteccCsSwitch
move.b crt0_buswidth,_AsteccBusWidth
move.l crt0_cpu_type,_AsteccCpuName
jmp SYM(_Init68340) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #stack_init,a7 | set master stack pointer
movel d0,a7@- | environp
movel d0,a7@- | argv
movel d0,a7@- | argc
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
/* stop #0x2700 | Stop with interrupts disabled */
move.w #0x2700,sr
bra.l SYM(_mainDone) | Stuck forever
.align 2
PUBLIC (_HeapSize)
SYM (_HeapSize):
.long HeapSize
PUBLIC (_StackSize)
SYM (_StackSize):
.long StackSize
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

498
c/src/lib/libbsp/m68k/gen68340/start340/startfor340only.S
View File

@@ -1,498 +0,0 @@
/*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Based on the `gen68360' board support package, and covered by the
* original distribution terms.
*
* Geoffroy Montel
* France Telecom - CNET/DSM/TAM/CAT
* 4, rue du Clos Courtel
* 35512 CESSON-SEVIGNE
* FRANCE
*
* e-mail: g_montel@yahoo.com
*
* $Id$
*/
#include "asm.h"
#include <m68340.inc>
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m340)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.s SYM(_uhoh) | Stuck forever
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
/* -- equates -- */
.equ _PROM_Start, 0x01000000 /* CS0 */
.equ _BCCram_Start, 0x00000000 /* CS1 */
.equ _FLEX_Start, 0x08000000 /* CS2 */
.equ _I2C_Start, 0x02000000 /* CS3 */
.equ _EXTram_Start, 0x10000000 /* CS4 */
.equ _EXTram_Size, 0x000400000 /* 4 Mbytes */
.equ _SPEED, 0xD780 /* 25 Mhz CPU349 */
/* .equ _SPEED, 0xD700 25 Mhz */
/* .equ _SPEED, 0xCE00 16 Mhz */
BEGIN_DATA
_crt0_init_stack:
ds.l 0x1000
_crt0_init_stktop:
BEGIN_CODE
dc.l _crt0_init_stktop /* reset SP */
dc.l _crt0_cold_start /* reset PC */
dc.l _crt0_warm_start
.ascii "RTEMS"
dc.w 0
.align 2
_table_cs:
/* carte Astecc - 68340 */
dc.l 0x003FFFF0 /* Mask CS0 (4Mbytes PROM, 32bits, 0WS) */
/* dc.l 0x003FFFFD Mask CS0 (4Mbytes PROM, 16bits, 3WS) */
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003) /* Base CS0 */
/* dc.l 0x0000FFF1 MASK CS1 (RAMBCC340, 0WS, FTE) */
dc.l 0x0000FFFD /* MASK CS1 (RAMBCC340, 0WS, FTE) */
/* dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000007) Base CS1 */
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003) /* Base CS1 */
dc.l 0x000000FF /* MASK CS2 (FLEX, ext DTACK, 256 bytes) */
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003) /* Base CS2 */
dc.l 0x000000FF /* Mask CS3 (I2C, ext DTACK, 256 bytes) */
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003) /* Base CS3 */
/*
* Initial PC
*/
.globl start
start:
_crt0_cold_start:
moveq.l #0,d0 /* signal cold reset */
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,d0 /* signal warm reset */
_crt0_common_start:
move.w #0x2700,sr /* disable interrupts and switch to interrupt mode */
movea.l #_crt0_init_stktop,sp /* set up initialization stack */
lea Entry,a0 /* Get base of vector table */
movec a0,vbr /* Set up the VBR */
moveq.l #0x07,d1
movec.l d1,dfc /* prepare access in CPU space */
move.l #(BASE_SIM+1),d1
moves.l d1,BASE_REG /* base initialization (must be MOVES, PCC-130795) */
moveq.l #0x05,d1
movec.l d1,dfc
movea.l #BASE_SIM,a0
/* -- disable Bus Monitor -- */
move.b #0,SIM_SYPCR(a0) /* system protection control register */
/* -- set frequency to 25.16 Mhz -- */
move.w #_SPEED,SIM_SYNCR(a0) /* clock */
sync_wait:
btst.b #3,(SIM_SYNCR+1)(a0)
beq sync_wait
/* -- enable A31-A24 -- */
clr.b SIM_PPRA1(a0)
/* -- show cycles, user acces to SIM, 4 /CS & 4 /IT -- */
move.w #0x427F,SIM_MCR(a0)
/* -- chip select initialization -- */
lea.l SIM_MASKH0(a0),a2
lea.l _table_cs(%pc),a1
moveq.l #0x07,d1
_b_cs:
move.l (a1)+, (a2)+
dbra d1,_b_cs
/* fill RAM if COLDSTART */
tst.l d0
bne _dont_fill
movea.l #_EXTram_Start,a0 /* get start */
move.l #_EXTram_Size,d1 /* get size */
lsr.l #2,d1 /* ajust for long word */
_fill_loop:
clr.l (a0)+
subq.l #1,d1
bne _fill_loop
_dont_fill:
jmp SYM(_Init68340) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #stack_init,a7 | set master stack pointer
movel d0,a7@- | environp
movel d0,a7@- | argv
movel d0,a7@- | argc
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
stop #0x2700 | Stop with interrupts disabled
bra.s SYM(_mainDone) | Stuck forever
.align 2
PUBLIC (_HeapSize)
SYM (_HeapSize):
.long HeapSize
PUBLIC (_StackSize)
SYM (_StackSize):
.long StackSize
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long 0
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END

68
c/src/lib/libbsp/m68k/gen68360/start360/Makefile.in
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@@ -1,68 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/gen68360/start360
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGMS = ${ARCH}/start360.o
# C source names, if any, go here -- minus the .c
C_PIECES =
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
# Assembly source names, if any, go here -- minus the .S
S_PIECES = start360
S_FILES = $(S_PIECES:%=%.S)
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
SRCS = $(C_FILES) $(H_FILES) $(S_FILES)
OBJS = $(C_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGMS} $(PROJECT_RELEASE)/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL_CHANGE)
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

436
c/src/lib/libbsp/m68k/gen68360/start360/start360.S
View File

@@ -1,436 +0,0 @@
/*
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Based on the `gen68302' board support package, and covered by the
* original distribution terms.
*
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
* University of Saskatchewan
* Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca
*
* $Id$
*/
#include "asm.h"
BEGIN_CODE
/*
* Step 1: Decide on Reset Stack Pointer and Initial Program Counter
*/
Entry:
.long SYM(m360)+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_uhoh) | 64: User defined vectors (192)
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
.long SYM(_uhoh) | 74:
.long SYM(_uhoh) | 75:
.long SYM(_uhoh) | 76:
.long SYM(_uhoh) | 77:
.long SYM(_uhoh) | 78:
.long SYM(_uhoh) | 79:
.long SYM(_uhoh) | 80:
.long SYM(_uhoh) | 81:
.long SYM(_uhoh) | 82:
.long SYM(_uhoh) | 83:
.long SYM(_uhoh) | 84:
.long SYM(_uhoh) | 85:
.long SYM(_uhoh) | 86:
.long SYM(_uhoh) | 87:
.long SYM(_uhoh) | 88:
.long SYM(_uhoh) | 89:
.long SYM(_uhoh) | 90:
.long SYM(_uhoh) | 91:
.long SYM(_uhoh) | 92:
.long SYM(_uhoh) | 93:
.long SYM(_uhoh) | 94:
.long SYM(_uhoh) | 95:
.long SYM(_uhoh) | 96:
.long SYM(_uhoh) | 97:
.long SYM(_uhoh) | 98:
.long SYM(_uhoh) | 99:
.long SYM(_uhoh) | 100:
.long SYM(_uhoh) | 101:
.long SYM(_uhoh) | 102:
.long SYM(_uhoh) | 103:
.long SYM(_uhoh) | 104:
.long SYM(_uhoh) | 105:
.long SYM(_uhoh) | 106:
.long SYM(_uhoh) | 107:
.long SYM(_uhoh) | 108:
.long SYM(_uhoh) | 109:
.long SYM(_uhoh) | 110:
.long SYM(_uhoh) | 111:
.long SYM(_uhoh) | 112:
.long SYM(_uhoh) | 113:
.long SYM(_uhoh) | 114:
.long SYM(_uhoh) | 115:
.long SYM(_uhoh) | 116:
.long SYM(_uhoh) | 117:
.long SYM(_uhoh) | 118:
.long SYM(_uhoh) | 119:
.long SYM(_uhoh) | 120:
.long SYM(_uhoh) | 121:
.long SYM(_uhoh) | 122:
.long SYM(_uhoh) | 123:
.long SYM(_uhoh) | 124:
.long SYM(_uhoh) | 125:
.long SYM(_uhoh) | 126:
.long SYM(_uhoh) | 127:
.long SYM(_uhoh) | 128:
.long SYM(_uhoh) | 129:
.long SYM(_uhoh) | 130:
.long SYM(_uhoh) | 131:
.long SYM(_uhoh) | 132:
.long SYM(_uhoh) | 133:
.long SYM(_uhoh) | 134:
.long SYM(_uhoh) | 135:
.long SYM(_uhoh) | 136:
.long SYM(_uhoh) | 137:
.long SYM(_uhoh) | 138:
.long SYM(_uhoh) | 139:
.long SYM(_uhoh) | 140:
.long SYM(_uhoh) | 141:
.long SYM(_uhoh) | 142:
.long SYM(_uhoh) | 143:
.long SYM(_uhoh) | 144:
.long SYM(_uhoh) | 145:
.long SYM(_uhoh) | 146:
.long SYM(_uhoh) | 147:
.long SYM(_uhoh) | 148:
.long SYM(_uhoh) | 149:
.long SYM(_uhoh) | 150:
.long SYM(_uhoh) | 151:
.long SYM(_uhoh) | 152:
.long SYM(_uhoh) | 153:
.long SYM(_uhoh) | 154:
.long SYM(_uhoh) | 155:
.long SYM(_uhoh) | 156:
.long SYM(_uhoh) | 157:
.long SYM(_uhoh) | 158:
.long SYM(_uhoh) | 159:
.long SYM(_uhoh) | 160:
.long SYM(_uhoh) | 161:
.long SYM(_uhoh) | 162:
.long SYM(_uhoh) | 163:
.long SYM(_uhoh) | 164:
.long SYM(_uhoh) | 165:
.long SYM(_uhoh) | 166:
.long SYM(_uhoh) | 167:
.long SYM(_uhoh) | 168:
.long SYM(_uhoh) | 169:
.long SYM(_uhoh) | 170:
.long SYM(_uhoh) | 171:
.long SYM(_uhoh) | 172:
.long SYM(_uhoh) | 173:
.long SYM(_uhoh) | 174:
.long SYM(_uhoh) | 175:
.long SYM(_uhoh) | 176:
.long SYM(_uhoh) | 177:
.long SYM(_uhoh) | 178:
.long SYM(_uhoh) | 179:
.long SYM(_uhoh) | 180:
.long SYM(_uhoh) | 181:
.long SYM(_uhoh) | 182:
.long SYM(_uhoh) | 183:
.long SYM(_uhoh) | 184:
.long SYM(_uhoh) | 185:
.long SYM(_uhoh) | 186:
.long SYM(_uhoh) | 187:
.long SYM(_uhoh) | 188:
.long SYM(_uhoh) | 189:
.long SYM(_uhoh) | 190:
.long SYM(_uhoh) | 191:
.long SYM(_uhoh) | 192:
.long SYM(_uhoh) | 193:
.long SYM(_uhoh) | 194:
.long SYM(_uhoh) | 195:
.long SYM(_uhoh) | 196:
.long SYM(_uhoh) | 197:
.long SYM(_uhoh) | 198:
.long SYM(_uhoh) | 199:
.long SYM(_uhoh) | 200:
.long SYM(_uhoh) | 201:
.long SYM(_uhoh) | 202:
.long SYM(_uhoh) | 203:
.long SYM(_uhoh) | 204:
.long SYM(_uhoh) | 205:
.long SYM(_uhoh) | 206:
.long SYM(_uhoh) | 207:
.long SYM(_uhoh) | 208:
.long SYM(_uhoh) | 209:
.long SYM(_uhoh) | 210:
.long SYM(_uhoh) | 211:
.long SYM(_uhoh) | 212:
.long SYM(_uhoh) | 213:
.long SYM(_uhoh) | 214:
.long SYM(_uhoh) | 215:
.long SYM(_uhoh) | 216:
.long SYM(_uhoh) | 217:
.long SYM(_uhoh) | 218:
.long SYM(_uhoh) | 219:
.long SYM(_uhoh) | 220:
.long SYM(_uhoh) | 221:
.long SYM(_uhoh) | 222:
.long SYM(_uhoh) | 223:
.long SYM(_uhoh) | 224:
.long SYM(_uhoh) | 225:
.long SYM(_uhoh) | 226:
.long SYM(_uhoh) | 227:
.long SYM(_uhoh) | 228:
.long SYM(_uhoh) | 229:
.long SYM(_uhoh) | 230:
.long SYM(_uhoh) | 231:
.long SYM(_uhoh) | 232:
.long SYM(_uhoh) | 233:
.long SYM(_uhoh) | 234:
.long SYM(_uhoh) | 235:
.long SYM(_uhoh) | 236:
.long SYM(_uhoh) | 237:
.long SYM(_uhoh) | 238:
.long SYM(_uhoh) | 239:
.long SYM(_uhoh) | 240:
.long SYM(_uhoh) | 241:
.long SYM(_uhoh) | 242:
.long SYM(_uhoh) | 243:
.long SYM(_uhoh) | 244:
.long SYM(_uhoh) | 245:
.long SYM(_uhoh) | 246:
.long SYM(_uhoh) | 247:
.long SYM(_uhoh) | 248:
.long SYM(_uhoh) | 249:
.long SYM(_uhoh) | 250:
.long SYM(_uhoh) | 251:
.long SYM(_uhoh) | 252:
.long SYM(_uhoh) | 253:
.long SYM(_uhoh) | 254:
.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
PUBLIC (_uhoh)
SYM(_uhoh): nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.l SYM(_uhoh) | Stuck forever
/*
* Log, but otherwise ignore, spurious interrupts
*/
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/*
* Place the low-order 3 octets of the board's ethernet address at
* a `well-known' fixed location relative to the startup location.
*/
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
/*
* Initial PC
*/
.globl start
start:
/*
* Step 2: Stay in Supervisor Mode
*/
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
oriw #0x3000,sr | Switch to Master Stack Pointer
lea SYM(m360)+1024-64,a7 | Put stack in dual-port ram
| a little below the interrupt stack
#endif
/*
* Step 3: Write the VBR
*/
lea Entry,a0 | Get base of vector table
movec a0,vbr | Set up the VBR
/*
* Step 4: Write the MBAR
*/
movec dfc,d1 | Save destination register
moveq #7,d0 | CPU-space funcction code
movec d0,dfc | Set destination function code register
movel #SYM(m360)+0x101,d0 | MBAR value (mask CPU space accesses)
movesl d0,0x3FF00 | Set MBAR
movec d1,dfc | Restore destination register
/*
* Step 5: Verify a dual-port RAM location
*/
lea SYM(m360),a0 | Point a0 to first DPRAM location
moveb #0x33,d0 | Set the test value
moveb d0,a0@ | Set the memory location
cmpb a0@,d0 | Does it read back?
bne SYM(_uhoh) | If not, bad news!
notb d0 | Flip bits
moveb d0,a0@ | Set the memory location
cmpb a0@,d0 | Does it read back?
bne SYM(_uhoh) | If not, bad news!
/*
* Remaining steps are handled by C code
*/
jmp SYM(_Init68360) | Start C code (which never returns)
/*
* Copy DATA segment, clear BSS segment, set up real stack,
* initialize heap, start C program.
* Assume that DATA and BSS sizes are multiples of 4.
*/
PUBLIC (_CopyDataClearBSSAndStart)
SYM(_CopyDataClearBSSAndStart):
lea copy_start,a0 | Get start of DATA in RAM
lea SYM(etext),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea copy_end,a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea clear_start,a0 | Get start of BSS
lea clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #stack_init,a7 | set master stack pointer
pea env | envp
pea arg | argv
movel d0,a7@- | argc
jsr SYM(boot_card) | Call C main
PUBLIC (_mainDone)
SYM(_mainDone):
nop | Leave spot for breakpoint
movew #1,a7 | Force a double bus error
movel d0,a7@- | This should cause a RESET
stop #0x2700 | Stop with interrupts disabled
bra.l SYM(_mainDone) | Stuck forever
.align 2
PUBLIC (_HeapSize)
SYM (_HeapSize):
.long HeapSize
PUBLIC (_StackSize)
SYM (_StackSize):
.long StackSize
END_CODE
BEGIN_DATA_DCL
.align 2
PUBLIC (environ)
SYM (environ):
.long env
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
BEGIN_BSS
env: .long 0
arg: .long 0
END_BSS
END

80
c/src/lib/libbsp/m68k/ods68302/start302/Makefile.in
View File

@@ -1,80 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = m68k/ods68302/start302
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGM = ${ARCH}/start302.o
RESET_S_PIECES_yes_V = debugreset
RESET_S_PIECES_no_V = reset
RESET_S_PIECES__V = $(RESET_S_PIECES_no_V)
RESET_S_PIECES = $(RESET_S_PIECES_$(RTEMS_DEBUGGER)_V)
CFLAGS_no_V = -DGDB_MONITOR_ACTIVE
CFLAGS__V = $(CFLAGS_no_V)
CFLAGS_V = $(CFLAGS_$(RTEMS_DEBUGGER)_V)
# C source names, if any, go here -- minus the .c
C_PIECES = cpuboot
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
# Assembly source names, if any, go here -- minus the .S
S_PIECES = $(RESET_S_PIECES)
S_FILES = $(S_PIECES:%=%.S)
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
SRCS = $(C_FILES) $(H_FILES) $(S_FILES)
OBJS = $(S_O_FILES) $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS += $(CFLAGS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
${PGM}: ${OBJS}
$(make-rel)
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGM} $(PROJECT_RELEASE)/lib
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL_CHANGE)
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

133
c/src/lib/libbsp/m68k/ods68302/start302/cpuboot.c
View File

@@ -1,133 +0,0 @@
/*****************************************************************************/
/*
Boot the CPU.
Occurs in 3 phases for a 68302.
Phase 1.
Called as soon as able after reset. The BAR has been programed, and
a small stack exists in the DPRAM. All interrupts are masked, and
the processor is running in supervisor mode. No other hardware or
chip selects are active.
This phase programs the chip select registers, the parallel ports
are set into default configurations, and basic registers cleared or
reset. The leds are programmed to show the end of phase 1.
Phase 2.
This is a piece of code which is copied to DPRAM and executed. It
should not do any more thann is currently present. The return to ROM
is managed by modifing the return address. Again leds show the status.
Phase 3.
This code executes with a valid C environment. That is the data
section has been intialised and the bss section set to 0. This phase
performs any special card initialisation and then calls boot card.
$Id$
*/
/*****************************************************************************/
#include <bsp.h>
#include <m68302.h>
#include <debugport.h>
#include <crc.h>
/*
Open the address, reset all registers
*/
void boot_phase_1()
{
M302_SCR = SCR_DEFAULT;
WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(CSEL_1)
WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_1, CSEL_1_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#endif
#if defined(CSEL_2)
WRITE_OR(CSEL_2, CSEL_2_SIZE, CSEL_2_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
WRITE_BR(CSEL_2, CSEL_2_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#endif
m302.reg.gimr = m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0;
m302.reg.simode = 0;
m302.reg.pacnt = CARD_PA_CONFIGURATION;
m302.reg.paddr = CARD_PA_DEFAULT_DIRECTIONS;
m302.reg.padat = CARD_PA_DEFAULT_DATA;
m302.reg.pbcnt = CARD_PB_CONFIGURATION;
m302.reg.pbddr = CARD_PB_DEFAULT_DIRECTIONS;
m302.reg.pbdat = CARD_PB_DEFAULT_DATA;
m302.reg.wrr = WATCHDOG_TIMEOUT_PERIOD | WATCHDOG_ENABLE;
#if defined(LED_CONTROL)
LED_CONTROL(LED_1_RED, LED_2_OFF, LED_3_OFF, LED_4_OFF,
LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
#endif
}
/*
Swap the chip select mapping for ROM and RAM
*/
void boot_phase_2(void)
{
rtems_unsigned32 stack;
#if defined(LED_CONTROL)
LED_CONTROL(LED_1_RED, LED_2_RED, LED_3_OFF, LED_4_OFF,
LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
#endif
WRITE_BR(CSEL_ROM, ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
WRITE_BR(CSEL_RAM, RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
#if defined(LED_CONTROL)
LED_CONTROL(LED_1_GREEN, LED_2_RED, LED_3_OFF, LED_4_OFF,
LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
#endif
/* seems to want 2, looked at assember code output */
*(&stack + 2) |= ROM_BASE;
}
/*
Any pre-main initialisation, the C environment is setup, how-ever C++
static constructors have not been called, and RTEMS is not initialised.
*/
void boot_card();
void set_debug_traps();
void breakpoint();
void boot_phase_3(void)
{
if (GDB_RUN_MONITOR())
{
set_debug_traps();
breakpoint();
}
debug_port_banner();
/* FIXME : add RAM and ROM checks */
/* boot the bsp, what ever this means */
boot_card();
WATCHDOG_TRIGGER();
}

107
c/src/lib/libbsp/m68k/ods68302/start302/debugreset.S
View File

@@ -1,107 +0,0 @@
/*
* $Id$
*
* Re-written the gen68302 start-up code.
*
* Uses gas syntax only, removed the OAR asm.h.
*
* Supplies a complete vector table in ROM.
*
* Manages all vectors with seperate handlers to trap unhandled
* execptions.
*
* Uses the target specific header file to get the runtime
* configuration
*
* COPYRIGHT (c) 1996
* Objective Design Systems Pty Ltd (ODS)
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
*/
|
| Entry from debugger
|
.sect .text
|
| Start
|
| Entered from a hardware reset.
|
.global start | Default entry point for GNU
start:
move.w #0x2700,%sr | Disable all interrupts
|
| zero out uninitialized data area
|
zerobss:
moveal #end,%a0 | find end of .bss
moveal #bss_start,%a1 | find beginning of .bss
moveq #0,%d0
zerobss_loop:
movel %d0,%a1@+ | to zero out uninitialized
cmpal %a0,%a1
jlt zerobss_loop | loop until _end reached
movel #end,%d0 | d0 = end of bss/start of heap
addl #heap_size,%d0 | d0 = end of heap
movel %d0,stack_start | Save for brk() routine
addl #stack_size,%d0 | make room for stack
andl #0xffffffc0,%d0 | align it on 16 byte boundary
movw #0x3700,%sr | SUPV MODE,INTERRUPTS OFF!!!
movel %d0,%a7 | set master stack pointer
movel %d0,%a6 | set base pointer
jsr boot_phase_3
|
| Initialised data
|
.sect .data
.global start_frame
start_frame:
.space 4,0
.global stack_start
stack_start:
.space 4,0
|
| Uninitialised data
|
.sect .bss
.global environ
.align 2
environ:
.long 0
.global heap_size
.set heap_size,0x2000
.global stack_size
.set stack_size,0x1000

881
c/src/lib/libbsp/m68k/ods68302/start302/reset.S
View File

@@ -1,881 +0,0 @@
/*
* $Id$
*
* Re-written the gen68302 start-up code.
*
* Uses gas syntax only, removed the OAR asm.h.
*
* Supplies a complete vector table in ROM.
*
* Manages all vectors with seperate handlers to trap unhandled
* execptions.
*
* Uses the target specific header file to get the runtime
* configuration
*
* COPYRIGHT (c) 1996
* Objective Design Systems Pty Ltd (ODS)
*
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
* On-Line Applications Research Corporation (OAR).
* All rights assigned to U.S. Government, 1994.
*
* This material may be reproduced by or for the U.S. Government pursuant
* to the copyright license under the clause at DFARS 252.227-7013. This
* notice must appear in all copies of this file and its derivatives.
*
*/
|
| some basic defined, this is that is required
|
#define MC68302_BAR 0x000000F2
#define MC68302_BAR_FC_CFC 0x0000
#define MC68302_SYS_RAM_SIZE 0x240
|
| Boot boot code in a special section, ld postions
|
| Initial stack pointer is in the dual ported RAM
|
.sect .text
.global M68Kvec | Vector Table
M68Kvec: | standard location for vectors
|
| Make relative, can have the code positioned any where
|
V___ISSP: .long MC68302_BASE + MC68302_SYS_RAM_SIZE
V____IPC: .long start - V___ISSP
|
| Create the rest of the vector table to point to the unhandled expection
| handler
|
| Lots of macros, how-ever it creates a simple ROM vector table
|
exception_handler = unhandled_exception - V___ISSP
#define MAKE_EXCEPTION_VECTOR(n) V___##n: .long (exception_handler + (n * 8))
MAKE_EXCEPTION_VECTOR(2)
MAKE_EXCEPTION_VECTOR(3)
MAKE_EXCEPTION_VECTOR(4)
MAKE_EXCEPTION_VECTOR(5)
MAKE_EXCEPTION_VECTOR(6)
MAKE_EXCEPTION_VECTOR(7)
MAKE_EXCEPTION_VECTOR(8)
MAKE_EXCEPTION_VECTOR(9)
MAKE_EXCEPTION_VECTOR(10)
MAKE_EXCEPTION_VECTOR(11)
MAKE_EXCEPTION_VECTOR(12)
MAKE_EXCEPTION_VECTOR(13)
MAKE_EXCEPTION_VECTOR(14)
MAKE_EXCEPTION_VECTOR(15)
MAKE_EXCEPTION_VECTOR(16)
MAKE_EXCEPTION_VECTOR(17)
MAKE_EXCEPTION_VECTOR(18)
MAKE_EXCEPTION_VECTOR(19)
MAKE_EXCEPTION_VECTOR(20)
MAKE_EXCEPTION_VECTOR(21)
MAKE_EXCEPTION_VECTOR(22)
MAKE_EXCEPTION_VECTOR(23)
MAKE_EXCEPTION_VECTOR(24)
MAKE_EXCEPTION_VECTOR(25)
MAKE_EXCEPTION_VECTOR(26)
MAKE_EXCEPTION_VECTOR(27)
MAKE_EXCEPTION_VECTOR(28)
MAKE_EXCEPTION_VECTOR(29)
MAKE_EXCEPTION_VECTOR(30)
MAKE_EXCEPTION_VECTOR(31)
MAKE_EXCEPTION_VECTOR(32)
MAKE_EXCEPTION_VECTOR(33)
MAKE_EXCEPTION_VECTOR(34)
MAKE_EXCEPTION_VECTOR(35)
MAKE_EXCEPTION_VECTOR(36)
MAKE_EXCEPTION_VECTOR(37)
MAKE_EXCEPTION_VECTOR(38)
MAKE_EXCEPTION_VECTOR(39)
MAKE_EXCEPTION_VECTOR(40)
MAKE_EXCEPTION_VECTOR(41)
MAKE_EXCEPTION_VECTOR(42)
MAKE_EXCEPTION_VECTOR(43)
MAKE_EXCEPTION_VECTOR(44)
MAKE_EXCEPTION_VECTOR(45)
MAKE_EXCEPTION_VECTOR(46)
MAKE_EXCEPTION_VECTOR(47)
MAKE_EXCEPTION_VECTOR(48)
MAKE_EXCEPTION_VECTOR(49)
MAKE_EXCEPTION_VECTOR(50)
MAKE_EXCEPTION_VECTOR(51)
MAKE_EXCEPTION_VECTOR(52)
MAKE_EXCEPTION_VECTOR(53)
MAKE_EXCEPTION_VECTOR(54)
MAKE_EXCEPTION_VECTOR(55)
MAKE_EXCEPTION_VECTOR(56)
MAKE_EXCEPTION_VECTOR(57)
MAKE_EXCEPTION_VECTOR(58)
MAKE_EXCEPTION_VECTOR(59)
MAKE_EXCEPTION_VECTOR(60)
MAKE_EXCEPTION_VECTOR(61)
MAKE_EXCEPTION_VECTOR(62)
MAKE_EXCEPTION_VECTOR(63)
MAKE_EXCEPTION_VECTOR(64)
MAKE_EXCEPTION_VECTOR(65)
MAKE_EXCEPTION_VECTOR(66)
MAKE_EXCEPTION_VECTOR(67)
MAKE_EXCEPTION_VECTOR(68)
MAKE_EXCEPTION_VECTOR(69)
MAKE_EXCEPTION_VECTOR(70)
MAKE_EXCEPTION_VECTOR(71)
MAKE_EXCEPTION_VECTOR(72)
MAKE_EXCEPTION_VECTOR(73)
MAKE_EXCEPTION_VECTOR(74)
MAKE_EXCEPTION_VECTOR(75)
MAKE_EXCEPTION_VECTOR(76)
MAKE_EXCEPTION_VECTOR(77)
MAKE_EXCEPTION_VECTOR(78)
MAKE_EXCEPTION_VECTOR(79)
MAKE_EXCEPTION_VECTOR(80)
MAKE_EXCEPTION_VECTOR(81)
MAKE_EXCEPTION_VECTOR(82)
MAKE_EXCEPTION_VECTOR(83)
MAKE_EXCEPTION_VECTOR(84)
MAKE_EXCEPTION_VECTOR(85)
MAKE_EXCEPTION_VECTOR(86)
MAKE_EXCEPTION_VECTOR(87)
MAKE_EXCEPTION_VECTOR(88)
MAKE_EXCEPTION_VECTOR(89)
MAKE_EXCEPTION_VECTOR(90)
MAKE_EXCEPTION_VECTOR(91)
MAKE_EXCEPTION_VECTOR(92)
MAKE_EXCEPTION_VECTOR(93)
MAKE_EXCEPTION_VECTOR(94)
MAKE_EXCEPTION_VECTOR(95)
MAKE_EXCEPTION_VECTOR(96)
MAKE_EXCEPTION_VECTOR(97)
MAKE_EXCEPTION_VECTOR(98)
MAKE_EXCEPTION_VECTOR(99)
MAKE_EXCEPTION_VECTOR(100)
MAKE_EXCEPTION_VECTOR(101)
MAKE_EXCEPTION_VECTOR(102)
MAKE_EXCEPTION_VECTOR(103)
MAKE_EXCEPTION_VECTOR(104)
MAKE_EXCEPTION_VECTOR(105)
MAKE_EXCEPTION_VECTOR(106)
MAKE_EXCEPTION_VECTOR(107)
MAKE_EXCEPTION_VECTOR(108)
MAKE_EXCEPTION_VECTOR(109)
MAKE_EXCEPTION_VECTOR(110)
MAKE_EXCEPTION_VECTOR(111)
MAKE_EXCEPTION_VECTOR(112)
MAKE_EXCEPTION_VECTOR(113)
MAKE_EXCEPTION_VECTOR(114)
MAKE_EXCEPTION_VECTOR(115)
MAKE_EXCEPTION_VECTOR(116)
MAKE_EXCEPTION_VECTOR(117)
MAKE_EXCEPTION_VECTOR(118)
MAKE_EXCEPTION_VECTOR(119)
MAKE_EXCEPTION_VECTOR(120)
MAKE_EXCEPTION_VECTOR(121)
MAKE_EXCEPTION_VECTOR(122)
MAKE_EXCEPTION_VECTOR(123)
MAKE_EXCEPTION_VECTOR(124)
MAKE_EXCEPTION_VECTOR(125)
MAKE_EXCEPTION_VECTOR(126)
MAKE_EXCEPTION_VECTOR(127)
MAKE_EXCEPTION_VECTOR(128)
MAKE_EXCEPTION_VECTOR(129)
MAKE_EXCEPTION_VECTOR(130)
MAKE_EXCEPTION_VECTOR(131)
MAKE_EXCEPTION_VECTOR(132)
MAKE_EXCEPTION_VECTOR(133)
MAKE_EXCEPTION_VECTOR(134)
MAKE_EXCEPTION_VECTOR(135)
MAKE_EXCEPTION_VECTOR(136)
MAKE_EXCEPTION_VECTOR(137)
MAKE_EXCEPTION_VECTOR(138)
MAKE_EXCEPTION_VECTOR(139)
MAKE_EXCEPTION_VECTOR(140)
MAKE_EXCEPTION_VECTOR(141)
MAKE_EXCEPTION_VECTOR(142)
MAKE_EXCEPTION_VECTOR(143)
MAKE_EXCEPTION_VECTOR(144)
MAKE_EXCEPTION_VECTOR(145)
MAKE_EXCEPTION_VECTOR(146)
MAKE_EXCEPTION_VECTOR(147)
MAKE_EXCEPTION_VECTOR(148)
MAKE_EXCEPTION_VECTOR(149)
MAKE_EXCEPTION_VECTOR(150)
MAKE_EXCEPTION_VECTOR(151)
MAKE_EXCEPTION_VECTOR(152)
MAKE_EXCEPTION_VECTOR(153)
MAKE_EXCEPTION_VECTOR(154)
MAKE_EXCEPTION_VECTOR(155)
MAKE_EXCEPTION_VECTOR(156)
MAKE_EXCEPTION_VECTOR(157)
MAKE_EXCEPTION_VECTOR(158)
MAKE_EXCEPTION_VECTOR(159)
MAKE_EXCEPTION_VECTOR(160)
MAKE_EXCEPTION_VECTOR(161)
MAKE_EXCEPTION_VECTOR(162)
MAKE_EXCEPTION_VECTOR(163)
MAKE_EXCEPTION_VECTOR(164)
MAKE_EXCEPTION_VECTOR(165)
MAKE_EXCEPTION_VECTOR(166)
MAKE_EXCEPTION_VECTOR(167)
MAKE_EXCEPTION_VECTOR(168)
MAKE_EXCEPTION_VECTOR(169)
MAKE_EXCEPTION_VECTOR(170)
MAKE_EXCEPTION_VECTOR(171)
MAKE_EXCEPTION_VECTOR(172)
MAKE_EXCEPTION_VECTOR(173)
MAKE_EXCEPTION_VECTOR(174)
MAKE_EXCEPTION_VECTOR(175)
MAKE_EXCEPTION_VECTOR(176)
MAKE_EXCEPTION_VECTOR(177)
MAKE_EXCEPTION_VECTOR(178)
MAKE_EXCEPTION_VECTOR(179)
MAKE_EXCEPTION_VECTOR(180)
MAKE_EXCEPTION_VECTOR(181)
MAKE_EXCEPTION_VECTOR(182)
MAKE_EXCEPTION_VECTOR(183)
MAKE_EXCEPTION_VECTOR(184)
MAKE_EXCEPTION_VECTOR(185)
MAKE_EXCEPTION_VECTOR(186)
MAKE_EXCEPTION_VECTOR(187)
MAKE_EXCEPTION_VECTOR(188)
MAKE_EXCEPTION_VECTOR(189)
MAKE_EXCEPTION_VECTOR(190)
MAKE_EXCEPTION_VECTOR(191)
MAKE_EXCEPTION_VECTOR(192)
MAKE_EXCEPTION_VECTOR(193)
MAKE_EXCEPTION_VECTOR(194)
MAKE_EXCEPTION_VECTOR(195)
MAKE_EXCEPTION_VECTOR(196)
MAKE_EXCEPTION_VECTOR(197)
MAKE_EXCEPTION_VECTOR(198)
MAKE_EXCEPTION_VECTOR(199)
MAKE_EXCEPTION_VECTOR(200)
MAKE_EXCEPTION_VECTOR(201)
MAKE_EXCEPTION_VECTOR(202)
MAKE_EXCEPTION_VECTOR(203)
MAKE_EXCEPTION_VECTOR(204)
MAKE_EXCEPTION_VECTOR(205)
MAKE_EXCEPTION_VECTOR(206)
MAKE_EXCEPTION_VECTOR(207)
MAKE_EXCEPTION_VECTOR(208)
MAKE_EXCEPTION_VECTOR(209)
MAKE_EXCEPTION_VECTOR(210)
MAKE_EXCEPTION_VECTOR(211)
MAKE_EXCEPTION_VECTOR(212)
MAKE_EXCEPTION_VECTOR(213)
MAKE_EXCEPTION_VECTOR(214)
MAKE_EXCEPTION_VECTOR(215)
MAKE_EXCEPTION_VECTOR(216)
MAKE_EXCEPTION_VECTOR(217)
MAKE_EXCEPTION_VECTOR(218)
MAKE_EXCEPTION_VECTOR(219)
MAKE_EXCEPTION_VECTOR(220)
MAKE_EXCEPTION_VECTOR(221)
MAKE_EXCEPTION_VECTOR(222)
MAKE_EXCEPTION_VECTOR(223)
MAKE_EXCEPTION_VECTOR(224)
MAKE_EXCEPTION_VECTOR(225)
MAKE_EXCEPTION_VECTOR(226)
MAKE_EXCEPTION_VECTOR(227)
MAKE_EXCEPTION_VECTOR(228)
MAKE_EXCEPTION_VECTOR(229)
MAKE_EXCEPTION_VECTOR(230)
MAKE_EXCEPTION_VECTOR(231)
MAKE_EXCEPTION_VECTOR(232)
MAKE_EXCEPTION_VECTOR(233)
MAKE_EXCEPTION_VECTOR(234)
MAKE_EXCEPTION_VECTOR(235)
MAKE_EXCEPTION_VECTOR(236)
MAKE_EXCEPTION_VECTOR(237)
MAKE_EXCEPTION_VECTOR(238)
MAKE_EXCEPTION_VECTOR(239)
MAKE_EXCEPTION_VECTOR(240)
MAKE_EXCEPTION_VECTOR(241)
MAKE_EXCEPTION_VECTOR(242)
MAKE_EXCEPTION_VECTOR(243)
MAKE_EXCEPTION_VECTOR(244)
MAKE_EXCEPTION_VECTOR(245)
MAKE_EXCEPTION_VECTOR(246)
MAKE_EXCEPTION_VECTOR(247)
MAKE_EXCEPTION_VECTOR(248)
MAKE_EXCEPTION_VECTOR(249)
MAKE_EXCEPTION_VECTOR(250)
MAKE_EXCEPTION_VECTOR(251)
MAKE_EXCEPTION_VECTOR(252)
MAKE_EXCEPTION_VECTOR(253)
MAKE_EXCEPTION_VECTOR(254)
MAKE_EXCEPTION_VECTOR(255)
|
| Start
|
| Entered from a hardware reset.
|
.global start | Default entry point for GNU
start:
move.w #0x2700,%sr | Disable all interrupts
|
| Program the BAR, give us a stack !!
|
moveq #0,%d0
move.w #(MC68302_BASE >> 12),%d0
or.w #(MC68302_BAR_FC_CFC << 12),%d0
move.l #MC68302_BAR,%a0
move.w %d0,%a0@(0)
|
| watch for sign extended maths with the linker on (boot_phase_1-V___ISSP)
| manage the address with code, limited address of 2K at reset for CS0
|
move.l #boot_phase_1,%d0
and.l #0x1FFF,%d0
move.l %d0,%a0
jsr %a0@(0) | programs all basic 302 registers
|
| Map to the 68302 registers
|
move.l #MC68302_BASE,%a5
|
| Make a vector table in RAM
|
move.l #RAM_BASE,%a0 | a0 -> rom vector table
moveal #ROM_BASE,%a1 | d1 -> start of tmp SRAM
move.l #255,%d0
copy_vec_table:
move.l (%a0)+,%d1
or.l #ROM_BASE,%d1
move.l %d1,(%a1)+
subq.l #1,%d0
bne copy_vec_table
#if defined(SYSTEM_TABLE_ANCHOR_OFFSET)
|
| Clear the system table
|
move.l #SYSTEM_TABLE_ANCHOR_OFFSET,%a0
move.l #0,(%a0)
#endif
|
| Copy the chip select swap code to DPRAM and run it
|
move.l #boot_phase_2,%d0
and.l #(ROM_SIZE - 1),%d0
move.l %d0,%a0 | a0 -> remap code
lea %a5@(0),%a1 | a1 -> internal system RAM
move.l #boot_phase_3,%d0
and.l #(ROM_SIZE - 1),%d0
sub.l %a0,%d0
copy_remap:
move.b (%a0)+,(%a1)+ | copy
dbra %d0,copy_remap
|
| Jump to the remap code in the 68302''s internal system RAM.
|
jsr %a5@(0) | execute the swap code
|
| Map to the 68302 registers
|
move.l #MC68302_BASE,%a5
|
| Copy initialized data area from ROM to RAM
|
copy_data:
moveal #etext,%a0 | find the end of .text
moveal #data_start,%a1 | find the beginning of .data
moveal #edata,%a2 | find the end of .data
copy_data_loop:
movel %a0@+,%a1@+ | copy the data
cmpal %a2,%a1
jlt copy_data_loop | loop until edata reached
|
| zero out uninitialized data area
|
zerobss:
moveal #end,%a0 | find end of .bss
moveal #bss_start,%a1 | find beginning of .bss
moveq #0,%d0
zerobss_loop:
movel %d0,%a1@+ | to zero out uninitialized
cmpal %a0,%a1
jlt zerobss_loop | loop until _end reached
movel #end,%d0 | d0 = end of bss/start of heap
addl #heap_size,%d0 | d0 = end of heap
movel %d0,stack_start | Save for brk() routine
addl #stack_size,%d0 | make room for stack
andl #0xffffffc0,%d0 | align it on 16 byte boundary
movw #0x3700,%sr | SUPV MODE,INTERRUPTS OFF!!!
movel %d0,%a7 | set master stack pointer
movel %d0,%a6 | set base pointer
jsr boot_phase_3
|
| Create an unhandled exception jump table. The table has an entry for
| each vector in the vector table. The entry pushes the vector number onto
| the stack and then calls a common exception handler using PIC.
|
| The macros are to create the labels and format vectors.
|
#define cat(x, y) x ## y
#define FORMAT_ID(n) (n << 2)
#define EXCEPTION_HANDLER(h, n) EH__##n: move.w cat(h, FORMAT_ID(n)),-(%sp) ; \
bra common_exception_handler
unhandled_exception:
EXCEPTION_HANDLER(#, 0)
EXCEPTION_HANDLER(#, 1)
EXCEPTION_HANDLER(#, 2)
EXCEPTION_HANDLER(#, 3)
EXCEPTION_HANDLER(#, 4)
EXCEPTION_HANDLER(#, 5)
EXCEPTION_HANDLER(#, 6)
EXCEPTION_HANDLER(#, 7)
EXCEPTION_HANDLER(#, 8)
EXCEPTION_HANDLER(#, 9)
EXCEPTION_HANDLER(#, 10)
EXCEPTION_HANDLER(#, 11)
EXCEPTION_HANDLER(#, 12)
EXCEPTION_HANDLER(#, 13)
EXCEPTION_HANDLER(#, 14)
EXCEPTION_HANDLER(#, 15)
EXCEPTION_HANDLER(#, 16)
EXCEPTION_HANDLER(#, 17)
EXCEPTION_HANDLER(#, 18)
EXCEPTION_HANDLER(#, 19)
EXCEPTION_HANDLER(#, 20)
EXCEPTION_HANDLER(#, 21)
EXCEPTION_HANDLER(#, 22)
EXCEPTION_HANDLER(#, 23)
EXCEPTION_HANDLER(#, 24)
EXCEPTION_HANDLER(#, 25)
EXCEPTION_HANDLER(#, 26)
EXCEPTION_HANDLER(#, 27)
EXCEPTION_HANDLER(#, 28)
EXCEPTION_HANDLER(#, 29)
EXCEPTION_HANDLER(#, 30)
EXCEPTION_HANDLER(#, 31)
EXCEPTION_HANDLER(#, 32)
EXCEPTION_HANDLER(#, 33)
EXCEPTION_HANDLER(#, 34)
EXCEPTION_HANDLER(#, 35)
EXCEPTION_HANDLER(#, 36)
EXCEPTION_HANDLER(#, 37)
EXCEPTION_HANDLER(#, 38)
EXCEPTION_HANDLER(#, 39)
EXCEPTION_HANDLER(#, 40)
EXCEPTION_HANDLER(#, 41)
EXCEPTION_HANDLER(#, 42)
EXCEPTION_HANDLER(#, 43)
EXCEPTION_HANDLER(#, 44)
EXCEPTION_HANDLER(#, 45)
EXCEPTION_HANDLER(#, 46)
EXCEPTION_HANDLER(#, 47)
EXCEPTION_HANDLER(#, 48)
EXCEPTION_HANDLER(#, 49)
EXCEPTION_HANDLER(#, 50)
EXCEPTION_HANDLER(#, 51)
EXCEPTION_HANDLER(#, 52)
EXCEPTION_HANDLER(#, 53)
EXCEPTION_HANDLER(#, 54)
EXCEPTION_HANDLER(#, 55)
EXCEPTION_HANDLER(#, 56)
EXCEPTION_HANDLER(#, 57)
EXCEPTION_HANDLER(#, 58)
EXCEPTION_HANDLER(#, 59)
EXCEPTION_HANDLER(#, 60)
EXCEPTION_HANDLER(#, 61)
EXCEPTION_HANDLER(#, 62)
EXCEPTION_HANDLER(#, 63)
EXCEPTION_HANDLER(#, 64)
EXCEPTION_HANDLER(#, 65)
EXCEPTION_HANDLER(#, 66)
EXCEPTION_HANDLER(#, 67)
EXCEPTION_HANDLER(#, 68)
EXCEPTION_HANDLER(#, 69)
EXCEPTION_HANDLER(#, 70)
EXCEPTION_HANDLER(#, 71)
EXCEPTION_HANDLER(#, 72)
EXCEPTION_HANDLER(#, 73)
EXCEPTION_HANDLER(#, 74)
EXCEPTION_HANDLER(#, 75)
EXCEPTION_HANDLER(#, 76)
EXCEPTION_HANDLER(#, 77)
EXCEPTION_HANDLER(#, 78)
EXCEPTION_HANDLER(#, 79)
EXCEPTION_HANDLER(#, 80)
EXCEPTION_HANDLER(#, 81)
EXCEPTION_HANDLER(#, 82)
EXCEPTION_HANDLER(#, 83)
EXCEPTION_HANDLER(#, 84)
EXCEPTION_HANDLER(#, 85)
EXCEPTION_HANDLER(#, 86)
EXCEPTION_HANDLER(#, 87)
EXCEPTION_HANDLER(#, 88)
EXCEPTION_HANDLER(#, 89)
EXCEPTION_HANDLER(#, 90)
EXCEPTION_HANDLER(#, 91)
EXCEPTION_HANDLER(#, 92)
EXCEPTION_HANDLER(#, 93)
EXCEPTION_HANDLER(#, 94)
EXCEPTION_HANDLER(#, 95)
EXCEPTION_HANDLER(#, 96)
EXCEPTION_HANDLER(#, 97)
EXCEPTION_HANDLER(#, 98)
EXCEPTION_HANDLER(#, 99)
EXCEPTION_HANDLER(#, 100)
EXCEPTION_HANDLER(#, 101)
EXCEPTION_HANDLER(#, 102)
EXCEPTION_HANDLER(#, 103)
EXCEPTION_HANDLER(#, 104)
EXCEPTION_HANDLER(#, 105)
EXCEPTION_HANDLER(#, 106)
EXCEPTION_HANDLER(#, 107)
EXCEPTION_HANDLER(#, 108)
EXCEPTION_HANDLER(#, 109)
EXCEPTION_HANDLER(#, 110)
EXCEPTION_HANDLER(#, 111)
EXCEPTION_HANDLER(#, 112)
EXCEPTION_HANDLER(#, 113)
EXCEPTION_HANDLER(#, 114)
EXCEPTION_HANDLER(#, 115)
EXCEPTION_HANDLER(#, 116)
EXCEPTION_HANDLER(#, 117)
EXCEPTION_HANDLER(#, 118)
EXCEPTION_HANDLER(#, 119)
EXCEPTION_HANDLER(#, 120)
EXCEPTION_HANDLER(#, 121)
EXCEPTION_HANDLER(#, 122)
EXCEPTION_HANDLER(#, 123)
EXCEPTION_HANDLER(#, 124)
EXCEPTION_HANDLER(#, 125)
EXCEPTION_HANDLER(#, 126)
EXCEPTION_HANDLER(#, 127)
EXCEPTION_HANDLER(#, 128)
EXCEPTION_HANDLER(#, 129)
EXCEPTION_HANDLER(#, 130)
EXCEPTION_HANDLER(#, 131)
EXCEPTION_HANDLER(#, 132)
EXCEPTION_HANDLER(#, 133)
EXCEPTION_HANDLER(#, 134)
EXCEPTION_HANDLER(#, 135)
EXCEPTION_HANDLER(#, 136)
EXCEPTION_HANDLER(#, 137)
EXCEPTION_HANDLER(#, 138)
EXCEPTION_HANDLER(#, 139)
EXCEPTION_HANDLER(#, 140)
EXCEPTION_HANDLER(#, 141)
EXCEPTION_HANDLER(#, 142)
EXCEPTION_HANDLER(#, 143)
EXCEPTION_HANDLER(#, 144)
EXCEPTION_HANDLER(#, 145)
EXCEPTION_HANDLER(#, 146)
EXCEPTION_HANDLER(#, 147)
EXCEPTION_HANDLER(#, 148)
EXCEPTION_HANDLER(#, 149)
EXCEPTION_HANDLER(#, 150)
EXCEPTION_HANDLER(#, 151)
EXCEPTION_HANDLER(#, 152)
EXCEPTION_HANDLER(#, 153)
EXCEPTION_HANDLER(#, 154)
EXCEPTION_HANDLER(#, 155)
EXCEPTION_HANDLER(#, 156)
EXCEPTION_HANDLER(#, 157)
EXCEPTION_HANDLER(#, 158)
EXCEPTION_HANDLER(#, 159)
EXCEPTION_HANDLER(#, 160)
EXCEPTION_HANDLER(#, 161)
EXCEPTION_HANDLER(#, 162)
EXCEPTION_HANDLER(#, 163)
EXCEPTION_HANDLER(#, 164)
EXCEPTION_HANDLER(#, 165)
EXCEPTION_HANDLER(#, 166)
EXCEPTION_HANDLER(#, 167)
EXCEPTION_HANDLER(#, 168)
EXCEPTION_HANDLER(#, 169)
EXCEPTION_HANDLER(#, 170)
EXCEPTION_HANDLER(#, 171)
EXCEPTION_HANDLER(#, 172)
EXCEPTION_HANDLER(#, 173)
EXCEPTION_HANDLER(#, 174)
EXCEPTION_HANDLER(#, 175)
EXCEPTION_HANDLER(#, 176)
EXCEPTION_HANDLER(#, 177)
EXCEPTION_HANDLER(#, 178)
EXCEPTION_HANDLER(#, 179)
EXCEPTION_HANDLER(#, 180)
EXCEPTION_HANDLER(#, 181)
EXCEPTION_HANDLER(#, 182)
EXCEPTION_HANDLER(#, 183)
EXCEPTION_HANDLER(#, 184)
EXCEPTION_HANDLER(#, 185)
EXCEPTION_HANDLER(#, 186)
EXCEPTION_HANDLER(#, 187)
EXCEPTION_HANDLER(#, 188)
EXCEPTION_HANDLER(#, 189)
EXCEPTION_HANDLER(#, 190)
EXCEPTION_HANDLER(#, 191)
EXCEPTION_HANDLER(#, 192)
EXCEPTION_HANDLER(#, 193)
EXCEPTION_HANDLER(#, 194)
EXCEPTION_HANDLER(#, 195)
EXCEPTION_HANDLER(#, 196)
EXCEPTION_HANDLER(#, 197)
EXCEPTION_HANDLER(#, 198)
EXCEPTION_HANDLER(#, 199)
EXCEPTION_HANDLER(#, 200)
EXCEPTION_HANDLER(#, 201)
EXCEPTION_HANDLER(#, 202)
EXCEPTION_HANDLER(#, 203)
EXCEPTION_HANDLER(#, 204)
EXCEPTION_HANDLER(#, 205)
EXCEPTION_HANDLER(#, 206)
EXCEPTION_HANDLER(#, 207)
EXCEPTION_HANDLER(#, 208)
EXCEPTION_HANDLER(#, 209)
EXCEPTION_HANDLER(#, 210)
EXCEPTION_HANDLER(#, 211)
EXCEPTION_HANDLER(#, 212)
EXCEPTION_HANDLER(#, 213)
EXCEPTION_HANDLER(#, 214)
EXCEPTION_HANDLER(#, 215)
EXCEPTION_HANDLER(#, 216)
EXCEPTION_HANDLER(#, 217)
EXCEPTION_HANDLER(#, 218)
EXCEPTION_HANDLER(#, 219)
EXCEPTION_HANDLER(#, 220)
EXCEPTION_HANDLER(#, 221)
EXCEPTION_HANDLER(#, 222)
EXCEPTION_HANDLER(#, 223)
EXCEPTION_HANDLER(#, 224)
EXCEPTION_HANDLER(#, 225)
EXCEPTION_HANDLER(#, 226)
EXCEPTION_HANDLER(#, 227)
EXCEPTION_HANDLER(#, 228)
EXCEPTION_HANDLER(#, 229)
EXCEPTION_HANDLER(#, 230)
EXCEPTION_HANDLER(#, 231)
EXCEPTION_HANDLER(#, 232)
EXCEPTION_HANDLER(#, 233)
EXCEPTION_HANDLER(#, 234)
EXCEPTION_HANDLER(#, 235)
EXCEPTION_HANDLER(#, 236)
EXCEPTION_HANDLER(#, 237)
EXCEPTION_HANDLER(#, 238)
EXCEPTION_HANDLER(#, 239)
EXCEPTION_HANDLER(#, 240)
EXCEPTION_HANDLER(#, 241)
EXCEPTION_HANDLER(#, 242)
EXCEPTION_HANDLER(#, 243)
EXCEPTION_HANDLER(#, 244)
EXCEPTION_HANDLER(#, 245)
EXCEPTION_HANDLER(#, 246)
EXCEPTION_HANDLER(#, 247)
EXCEPTION_HANDLER(#, 248)
EXCEPTION_HANDLER(#, 249)
EXCEPTION_HANDLER(#, 250)
EXCEPTION_HANDLER(#, 251)
EXCEPTION_HANDLER(#, 252)
EXCEPTION_HANDLER(#, 253)
EXCEPTION_HANDLER(#, 254)
EXCEPTION_HANDLER(#, 255)
common_exception_handler:
|
| Need to put the format/vector above the PC and status register
|
move.l %d0,-(%sp) | free a register
move.w 4(%sp),%d0 | get the format/vector id
|
| If a bus error or address error then trash the extra
| data saved on the stack
|
cmp.w #0x0008,%d0
beq ceh_10
cmp.w #0x000C,%d0
beq ceh_10
bra ceh_20
ceh_10:
move.w %d0,12(%sp) | need to move the format/id
move.l (%sp)+,%d0 | recover d0
addq #8,%sp | trash the stack
move.l %d0,-(%sp) | free a register, again
move.w 4(%sp),%d0 | get the format/vector id
ceh_20:
move.w 6(%sp),4(%sp)
move.w 8(%sp),6(%sp)
move.w 10(%sp),8(%sp)
move.w %d0,10(%sp) | put the format/vector id
move.l (%sp)+,%d0
|
| Save all the registers, pass control to a dump trace routine
|
movem.l %d0-%d7/%a0-%a7,%sp@-
|
| check to see if ROM is mapped to zero
|
move.l #trace_exception,%d1 | get the linked address
and.l #(ROM_SIZE - 1),%d1 | obtain the offset into the ROM
lea.l %pc@(0),%a0 | were are we currently
move.l %a0,%d0 | need to use a data register
and.l #~(ROM_SIZE - 1),%d0 | keep the top part of the address
or.l %d1,%d0 | apply it to the trace exception offset
move.l %d0,%a0 | need an address register for jumping
jsr %a0@(0)
ceh_30:
jmp ceh_30
|
| The RAM based vector table
|
.sect .vtable
.global vector_table
vector_table:
.space (256 * 4),0
|
| Initialised data
|
.sect .data
.global start_frame
start_frame:
.space 4,0
.global stack_start
stack_start:
.space 4,0
|
| Uninitialised data
|
.sect .bss
.global environ
.align 2
environ:
.long 0
.global heap_size
.set heap_size,0x2000
.global stack_size
.set stack_size,0x1000

65
c/src/lib/libbsp/powerpc/psim/startsim/Makefile.in
View File

@@ -1,65 +0,0 @@
#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
top_srcdir = @top_srcdir@
top_builddir = ../../..
subdir = powerpc/psim/startsim
RTEMS_ROOT = @RTEMS_ROOT@
PROJECT_ROOT = @PROJECT_ROOT@
VPATH = @srcdir@
PGMS = ${ARCH}/startsim.o
# C source names, if any, go here -- minus the .c
C_PIECES =
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
H_FILES =
# Assembly source names, if any, go here -- minus the .S
S_PIECES = startsim
S_FILES = $(S_PIECES:%=%.S)
S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
SRCS = $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS = $(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(RTEMS_ROOT)/make/leaf.cfg
INSTALL_CHANGE = @INSTALL_CHANGE@
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS +=
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
$(INSTALL_VARIANT) -m 755 ${PGMS} $(PROJECT_RELEASE)/lib
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
cd $(top_builddir) \
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status

106
c/src/lib/libbsp/powerpc/psim/startsim/startsim.S
View File

@@ -1,106 +0,0 @@
/*
* This is based on the mvme-crt0.S file from libgloss/rs6000.
* crt0.S -- startup file for PowerPC systems.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*
* $Id$
*/
#include "ppc-asm.h"
.file "startsim.s"
.section ".got2","aw"
.align 2
.LCTOC1 = .+32768
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
.section ".got2","aw"
.Ltable = .-.LCTOC1
.long .LCTOC1 /* address we think .LCTOC1 is loaded at */
.Lbss_start = .-.LCTOC1
.long __bss_start
.Lend = .-.LCTOC1
.long _end
.Lstack = .-.LCTOC1 /* stack address if set by user */
.long __stack
.text
.Lptr:
.long .LCTOC1-.Laddr
.globl _start
.type _start,@function
_start:
bl .Laddr /* get current address */
.Laddr:
mflr r4 /* real address of .Laddr */
lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */
add r5,r5,r4 /* correct to real pointer */
lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */
subf r4,r4,r5 /* calculate difference between where linked and current */
/* clear bss */
lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */
lwz r7,.Lend(r5) /* calculate end of the BSS */
add r6,r6,r4 /* adjust pointers */
add r7,r7,r4
cmplw 1,r6,r7
bc 4,4,.Ldone
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lloop:
stwu r0,4(r6) /* zero bss */
bdnz .Lloop
.Ldone:
lwz r0,.Lstack(r5) /* stack address or 0 */
cmplwi 1,r0,0 /* equal to 0? */
bc 12,6,.Lnostack /* use default stack if == 0 */
mr sp,r0 /* use user defined stack */
.Lnostack:
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-56(sp) /* push another stack frame */
/* Let her rip */
bl FUNC_NAME(boot_card)
/* return value from boot_card is argument to exit */
bl FUNC_NAME(exit)
trap
.Lstart:
.size _start,.Lstart-_start