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score/aarch64: Fix interrupt level reads

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This commit is contained in:
Alex White
2021-01-11 10:23:16 -06:00
committed by Joel Sherrill
parent bbc9974a24
commit 9aff7e5685
2 changed files with 7 additions and 3 deletions
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2
cpukit/score/cpu/aarch64/cpu.c
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@@ -166,7 +166,7 @@ uint64_t _CPU_ISR_Get_level( void )
: [level] "=&r" (level) : [level] "=&r" (level)
); );
return level & AARCH64_PSTATE_I; return ( level & AARCH64_PSTATE_I ) != 0;
} }
void _CPU_ISR_install_vector( void _CPU_ISR_install_vector(

8
cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
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@@ -215,10 +215,14 @@ void AArch64_interrupt_flash( uint64_t level );
#else #else
static inline uint64_t AArch64_interrupt_disable( void ) static inline uint64_t AArch64_interrupt_disable( void )
{ {
uint64_t level = _CPU_ISR_Get_level(); uint64_t level;
__asm__ volatile ( __asm__ volatile (
"mrs %[level], DAIF\n"
"msr DAIFSet, #0x2\n" "msr DAIFSet, #0x2\n"
: [level] "=&r" (level)
); );
return level; return level;
} }
@@ -250,7 +254,7 @@ static inline void AArch64_interrupt_flash( uint64_t level )
RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t level ) RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint64_t level )
{ {
return ( level & AARCH64_PSTATE_I ) == 0; return level == 0;
} }
void _CPU_Context_Initialize( void _CPU_Context_Initialize(