forked from Imagelibrary/rtems
bsps/arm: Set vector base address if necessary
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@@ -100,6 +100,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
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BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
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{
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arm_a9mpcore_start_hook_1();
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bsp_start_copy_sections();
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setup_mmu_and_cache();
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bsp_start_clear_bss();
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@@ -27,12 +27,21 @@
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extern "C" {
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#endif /* __cplusplus */
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BSP_START_TEXT_SECTION static inline uint32_t
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arm_cp15_get_control(void);
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BSP_START_TEXT_SECTION static inline void
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arm_cp15_set_control(uint32_t val);
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BSP_START_TEXT_SECTION static inline uint32_t
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arm_cp15_get_auxiliary_control(void);
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BSP_START_TEXT_SECTION static inline void
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arm_cp15_set_auxiliary_control(uint32_t val);
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BSP_START_TEXT_SECTION static inline void
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arm_cp15_set_vector_base_address(void *base);
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BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
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{
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#ifdef RTEMS_SMP
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@@ -81,6 +90,26 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void)
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#endif
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}
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BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_1(void)
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{
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/*
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* Do not use bsp_vector_table_begin == 0, since this will get optimized away.
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*/
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if (bsp_vector_table_end != bsp_vector_table_size) {
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uint32_t ctrl;
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/*
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* For now we assume that every Cortex-A9 MPCore has the Security Extensions.
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* Later it might be necessary to evaluate the ID_PFR1 register.
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*/
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arm_cp15_set_vector_base_address(bsp_vector_table_begin);
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ctrl = arm_cp15_get_control();
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ctrl &= ~ARM_CP15_CTRL_V;
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arm_cp15_set_control(ctrl);
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}
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}
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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@@ -100,6 +100,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
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BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
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{
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arm_a9mpcore_start_hook_1();
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bsp_start_copy_sections();
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setup_mmu_and_cache();
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bsp_start_clear_bss();
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@@ -899,6 +899,53 @@ static inline void arm_cp15_set_auxiliary_control(uint32_t val)
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);
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}
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/* ID_PFR1, Processor Feature Register 1 */
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static inline uint32_t arm_cp15_get_processor_feature_1(void)
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{
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ARM_SWITCH_REGISTERS;
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uint32_t val;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrc p15, 0, %[val], c0, c1, 1\n"
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ARM_SWITCH_BACK
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: [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
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);
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return val;
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}
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/* VBAR, Vector Base Address Register, Security Extensions */
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static inline void *arm_cp15_get_vector_base_address(void)
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{
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ARM_SWITCH_REGISTERS;
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void *base;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrc p15, 0, %[base], c12, c0, 0\n"
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ARM_SWITCH_BACK
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: [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
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);
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return base;
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}
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static inline void arm_cp15_set_vector_base_address(void *base)
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{
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ARM_SWITCH_REGISTERS;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mcr p15, 0, %[base], c12, c0, 0\n"
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ARM_SWITCH_BACK
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: ARM_SWITCH_OUTPUT
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: [base] "r" (base)
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);
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}
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/**
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* @brief Sets the @a section_flags for the address range [@a begin, @a end).
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*
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