forked from Imagelibrary/rtems
bsps: Move startup files to bsps
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
This commit is contained in:
Sebastian Huber
92
bsps/sparc/erc32/start/boardinit.S
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92
bsps/sparc/erc32/start/boardinit.S
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@@ -0,0 +1,92 @@
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/**
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* @file
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*
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* @ingroup sparc_erc32
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*
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* @brief Initialise various ERC32 registers
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*/
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/*
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* COPYRIGHT (c) 2000.
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* European Space Agency.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <erc32.h>
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.global __bsp_board_init
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__bsp_board_init:
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/* Check if MEC is initialised. If not, this means that we are
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running on the simulator. Initiate some of the parameters
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that are done by the boot-prom otherwise.
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*/
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set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals
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ld [%g3], %g2
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set 0xfe080000, %g1
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andcc %g1, %g2, %g0
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bne 2f
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/* Stop the watchdog */
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st %g0, [%g3 + SYM(ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET)]
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/* Set zero waitstates */
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st %g0, [%g3 + SYM(ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET)]
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/* Set the correct memory size in MEC memory config register */
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set SYM(PROM_SIZE), %l0
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set 0, %l1
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srl %l0, 18, %l0
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1:
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tst %l0
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srl %l0, 1, %l0
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bne,a 1b
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inc %l1
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sll %l1, 8, %l1
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set SYM(RAM_SIZE), %l0
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srl %l0, 19, %l0
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1:
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tst %l0
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srl %l0, 1, %l0
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bne,a 1b
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inc %l1
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sll %l1, 10, %l1
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! set the Memory Configuration
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st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
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set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker
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set SYM(RAM_SIZE), %l2
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add %l1, %l2, %sp
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set SYM(CLOCK_SPEED), %g6 ! Use 14 MHz in simulator
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set 14, %g1
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st %g1, [%g6]
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2:
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/* Initialise timer */
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set SYM(_ERC32_MEC_Timer_Control_Mirror), %l2
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st %g0, [%l2]
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st %g0, [%g3 + SYM(ERC32_MEC_TIMER_CONTROL_OFFSET)]
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/* Enable power-down */
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ld [%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)], %l2
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or %l2, ERC32_CONFIGURATION_POWER_DOWN_ALLOWED, %l2
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st %l2, [%g3 + SYM(ERC32_MEC_CONTROL_OFFSET)]
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retl
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nop
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/* end of file */
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9
bsps/sparc/erc32/start/bsp_specs
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9
bsps/sparc/erc32/start/bsp_specs
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@@ -0,0 +1,9 @@
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%rename endfile old_endfile
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%rename startfile old_startfile
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*startfile:
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%{!qrtems: %(old_startfile)} \
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%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
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*endfile:
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%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
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25
bsps/sparc/erc32/start/bspdelay.c
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25
bsps/sparc/erc32/start/bspdelay.c
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/*
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* ERC32 BSP Delay Method
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*/
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/*
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* COPYRIGHT (c) 1989-2014.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp.h>
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void rtems_bsp_delay(int usecs)
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{
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uint32_t then;
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then = ERC32_MEC.Real_Time_Clock_Counter;
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then += usecs;
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while (ERC32_MEC.Real_Time_Clock_Counter >= then)
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;
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}
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27
bsps/sparc/erc32/start/bspidle.c
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27
bsps/sparc/erc32/start/bspidle.c
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@@ -0,0 +1,27 @@
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/*
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* ERC32 Idle Thread with power-down function
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*
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* COPYRIGHT (c) 1989-2009.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Ported to ERC32 implementation of the SPARC by On-Line Applications
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* Research Corporation (OAR) under contract to the European Space
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* Agency (ESA).
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*
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* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
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* European Space Agency.
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*/
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#include <bsp.h>
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void *bsp_idle_thread( uintptr_t ignored )
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{
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while (1) {
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ERC32_MEC.Power_Down = 0; /* value is irrelevant */
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}
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return NULL;
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}
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15
bsps/sparc/erc32/start/erc32mec.c
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15
bsps/sparc/erc32/start/erc32mec.c
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@@ -0,0 +1,15 @@
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/*
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* Put this variable in a separate file so it is only linked in when needed.
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*
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* COPYRIGHT (c) 1989-2002.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <bsp.h>
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ERC32_Register_Map ERC32_MEC;
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29
bsps/sparc/erc32/start/linkcmds
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29
bsps/sparc/erc32/start/linkcmds
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@@ -0,0 +1,29 @@
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/* linkcmds
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*/
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/* Default values, can be overridden */
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_PROM_SIZE = DEFINED (_PROM_SIZE) ? _PROM_SIZE : 2M;
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_PROM_START = DEFINED (_PROM_START) ? _PROM_START : 0x00000000;
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_RAM_SIZE = DEFINED (_RAM_SIZE) ? _RAM_SIZE : 4M;
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_RAM_START = DEFINED (_RAM_START) ? _RAM_START : 0x02000000;
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/*
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* Base address of the on-CPU peripherals
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*/
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_ERC32_MEC = 0x01f80000;
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ERC32_MEC = _ERC32_MEC;
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/* these are the maximum values */
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MEMORY
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{
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rom : ORIGIN = 0x00000000, LENGTH = 16
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ram : ORIGIN = 0x02000000, LENGTH = 32M
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}
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ENTRY(start)
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INCLUDE linkcmds.base
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59
bsps/sparc/erc32/start/setvec.c
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59
bsps/sparc/erc32/start/setvec.c
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@@ -0,0 +1,59 @@
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/* set_vector
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*
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* This routine installs an interrupt vector on the SPARC simulator.
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*
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* INPUT PARAMETERS:
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* handler - interrupt handler entry point
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* vector - vector number
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* type - 0 indicates raw hardware connect
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* 1 indicates RTEMS interrupt connect
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*
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* OUTPUT PARAMETERS: NONE
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*
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* RETURNS:
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* address of previous interrupt handler
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Ported to ERC32 implementation of the SPARC by On-Line Applications
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* Research Corporation (OAR) under contract to the European Space
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* Agency (ESA).
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*
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* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
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* European Space Agency.
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*/
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#include <bsp.h>
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rtems_isr_entry set_vector( /* returns old vector */
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rtems_isr_entry handler, /* isr routine */
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rtems_vector_number vector, /* vector number */
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int type /* RTEMS or RAW intr */
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)
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{
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rtems_isr_entry previous_isr;
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uint32_t real_trap;
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uint32_t source;
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if ( type )
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rtems_interrupt_catch( handler, vector, &previous_isr );
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else
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_CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
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real_trap = SPARC_REAL_TRAP_NUMBER( vector );
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if ( ERC32_Is_MEC_Trap( real_trap ) ) {
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source = ERC32_TRAP_SOURCE( real_trap );
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ERC32_Clear_interrupt( source );
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ERC32_Unmask_interrupt( source );
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}
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return previous_isr;
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}
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194
bsps/sparc/erc32/start/spurious.c
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194
bsps/sparc/erc32/start/spurious.c
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@@ -0,0 +1,194 @@
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/*
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* ERC32 Spurious Trap Handler
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*
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* This is just enough of a trap handler to let us know what
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* the likely source of the trap was.
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*
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* Developed as part of the port of RTEMS to the ERC32 implementation
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* of the SPARC by On-Line Applications Research Corporation (OAR)
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* under contract to the European Space Agency (ESA).
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*
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* COPYRIGHT (c) 1995. European Space Agency.
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*
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* This terms of the RTEMS license apply to this file.
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*/
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#include <bsp.h>
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#include <rtems/bspIo.h>
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#include <inttypes.h>
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void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
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{
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uint32_t trap;
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uint32_t real_trap;
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const CPU_Interrupt_frame *isf;
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trap = frame->trap;
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real_trap = SPARC_REAL_TRAP_NUMBER(trap);
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isf = frame->isf;
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printk(
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"Unexpected trap (%2" PRId32 ") at address 0x%08" PRIx32 "\n",
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real_trap,
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isf->tpc
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);
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switch (real_trap) {
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/*
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* First the ones defined by the basic architecture
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*/
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case 0x00:
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printk( "reset\n" );
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break;
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case 0x01:
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printk( "instruction access exception\n" );
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break;
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case 0x02:
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printk( "illegal instruction\n" );
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break;
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case 0x03:
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printk( "privileged instruction\n" );
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break;
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case 0x04:
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printk( "fp disabled\n" );
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break;
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case 0x07:
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printk( "memory address not aligned\n" );
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break;
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case 0x08:
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printk( "fp exception\n" );
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break;
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case 0x09:
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printk("data access exception at 0x%08" PRIx32 "\n",
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ERC32_MEC.First_Failing_Address );
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break;
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case 0x0A:
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printk( "tag overflow\n" );
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break;
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/*
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* Then the ones defined by the ERC32 in particular
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*/
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ):
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printk( "ERC32_INTERRUPT_MASKED_ERRORS\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_1 ):
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printk( "ERC32_INTERRUPT_EXTERNAL_1\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_2 ):
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printk( "ERC32_INTERRUPT_EXTERNAL_2\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_A_RX_TX ):
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printk( "ERC32_INTERRUPT_UART_A_RX_TX\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_B_RX_TX ):
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printk( "ERC32_INTERRUPT_UART_A_RX_TX\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR ):
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printk( "ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_ERROR ):
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printk( "ERC32_INTERRUPT_UART_ERROR\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_ACCESS_ERROR ):
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printk( "ERC32_INTERRUPT_DMA_ACCESS_ERROR\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_TIMEOUT ):
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printk( "ERC32_INTERRUPT_DMA_TIMEOUT\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_3 ):
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printk( "ERC32_INTERRUPT_EXTERNAL_3\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_4 ):
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printk( "ERC32_INTERRUPT_EXTERNAL_4\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER ):
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printk( "ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_REAL_TIME_CLOCK ):
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printk( "ERC32_INTERRUPT_REAL_TIME_CLOCK\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_5 ):
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printk( "ERC32_INTERRUPT_EXTERNAL_5\n" );
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break;
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case ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ):
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printk( "ERC32_INTERRUPT_WATCHDOG_TIMEOUT\n" );
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break;
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default:
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break;
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}
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}
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static rtems_isr bsp_spurious_handler(
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rtems_vector_number trap,
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CPU_Interrupt_frame *isf
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)
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{
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CPU_Exception_frame frame = {
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.trap = trap,
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.isf = isf
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};
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#if !defined(SPARC_USE_LAZY_FP_SWITCH)
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if ( SPARC_REAL_TRAP_NUMBER( trap ) == 4 ) {
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_Internal_error( INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT );
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}
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#endif
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rtems_fatal(
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RTEMS_FATAL_SOURCE_EXCEPTION,
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(rtems_fatal_code) &frame
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);
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}
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/*
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* bsp_spurious_initialize
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*
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* Install the spurious handler for most traps. Note that set_vector()
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* will unmask the corresponding asynchronous interrupt, so the initial
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* interrupt mask is restored after the handlers are installed.
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*/
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void bsp_spurious_initialize()
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{
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uint32_t trap;
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uint32_t level = 15;
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uint32_t mask;
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level = sparc_disable_interrupts();
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mask = ERC32_MEC.Interrupt_Mask;
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for ( trap=0 ; trap<256 ; trap++ ) {
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/*
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* Skip window overflow, underflow, and flush as well as software
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* trap 0,9,10 which we will use as a shutdown, IRQ disable, IRQ enable.
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* Also avoid trap 0x70 - 0x7f which cannot happen and where some of the
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* space is used to pass parameters to the program.
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*/
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if (( trap == 5 || trap == 6 ) ||
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#if defined(SPARC_USE_LAZY_FP_SWITCH)
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( trap == 4 ) ||
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#endif
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(( trap >= 0x11 ) && ( trap <= 0x1f )) ||
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(( trap >= 0x70 ) && ( trap <= 0x83 )) ||
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( trap == 0x80 + SPARC_SWTRAP_IRQDIS ) ||
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#if defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH)
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( trap == 0x80 + SPARC_SWTRAP_IRQDIS_FP ) ||
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#endif
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( trap == 0x80 + SPARC_SWTRAP_IRQEN ))
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continue;
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set_vector( (rtems_isr_entry) bsp_spurious_handler,
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SPARC_SYNCHRONOUS_TRAP( trap ), 1 );
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}
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ERC32_MEC.Interrupt_Mask = mask;
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sparc_enable_interrupts(level);
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}
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Reference in New Issue
Block a user