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bsps: Move startup files to bsps

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Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.
This commit is contained in:
Sebastian Huber
2018-04-20 10:35:35 +02:00
parent fbcd7c8fa6
commit 9964895866
653 changed files with 559 additions and 560 deletions
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9
bsps/mips/csb350/start/bsp_specs Normal file
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%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

24
bsps/mips/csb350/start/bspreset.c Normal file
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/*
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp/bootcard.h>
#include <libcpu/au1x00.h>
void bsp_reset(void)
{
void (*reset_func)(void);
reset_func = (void *)0xbfc00000;
mips_set_sr( 0x00200000 ); /* all interrupts off, boot exception vectors */
/* Try to restart bootloader */
reset_func();
}

44
bsps/mips/csb350/start/bspstart.c Normal file
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@@ -0,0 +1,44 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <string.h>
#include <bsp.h>
#include <libcpu/au1x00.h>
#include <libcpu/isr_entries.h>
#include <bsp/irq-generic.h>
void bsp_start( void );
au1x00_uart_t *uart0 = (au1x00_uart_t *)AU1X00_UART0_ADDR;
au1x00_uart_t *uart3 = (au1x00_uart_t *)AU1X00_UART3_ADDR;
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
unsigned int compare = 0;
mips_set_sr( 0x7f00 ); /* all interrupts unmasked but globally off */
/* depend on the IRC to take care of things */
__asm__ volatile ("mtc0 %0, $11\n" :: "r" (compare));
bsp_interrupt_initialize();
}

235
bsps/mips/csb350/start/linkcmds Normal file
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@@ -0,0 +1,235 @@
/*
* Linker script for CSB350 AU1100 based board
*/
/* . = 0x80020000; */
/*
* Declare some sizes.
*/
_sdram_base = DEFINED(_sdram_base) ? _sdram_base : 0x80400000;
_sdram_size = DEFINED(_sdram_size) ? _sdram_size : 12M;
/* standard items provided by RTEMS linkcmds files */
RamBase = _sdram_base;
RamSize = _sdram_size;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x4000;
ENTRY(_start)
STARTUP(start.o)
MEMORY
{
ram : ORIGIN = 0x80400000, LENGTH = 12M
}
SECTIONS
{
.text :
{
_ftext = . ;
*/start.o(.text)
*(.text*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
*(.reginfo*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
*(.rel.dyn)
PROVIDE (__runtime_reloc_stop = .);
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
} >ram
.init :
{
KEEP(*(.init))
} > ram
.fini :
{
KEEP(*(.fini))
} >ram
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
} >ram
.rdata :
{
*(.rdata)
*(.rodata)
*(.rodata.*)
KEEP (*(SORT(.rtemsroset.*)))
*(.gnu.linkonce.r*)
} >ram
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
} >ram
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
} >ram
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
.data :
{
_fdata = ALIGN(16);
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
} >ram
.jcr :
{
. = ALIGN(8);
KEEP (*(.jcr))
_gp = ALIGN(16) + 0x7440;
__global = _gp;
} >ram
.lit8 :
{
*(.lit8)
} >ram
.lit4 :
{
*(.lit4)
} >ram
.sdata :
{
*(.sdata*)
*(.gnu.linkonce.s*)
} >ram
.sbss :
{
edata = .;
_edata = .;
_fbss = .;
*(.sbss*)
*(.scommon)
} >ram
.bss :
{
_bss_start = . ;
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
_clear_end = .;
end = .;
_end = .;
. = ALIGN (1024);
WorkAreaBase = .;
} >ram
/*
** DWARF debug sections.
** Symbols in the DWARF debugging sections are relative to
** the beginning of the section so we begin them at 0.
*/
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame)}
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

9
bsps/mips/hurricane/start/bsp_specs Normal file
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@@ -0,0 +1,9 @@
%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

39
bsps/mips/hurricane/start/bspstart.c Normal file
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@@ -0,0 +1,39 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <string.h>
#include <bsp.h>
#include <libcpu/isr_entries.h>
#include <bsp/irq-generic.h>
void bsp_start( void );
uint32_t bsp_clicks_per_microsecond;
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
bsp_clicks_per_microsecond = CPU_CLOCK_RATE_MHZ;
bsp_interrupt_initialize();
}

19
bsps/mips/hurricane/start/ghlinkcmds Normal file
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@@ -0,0 +1,19 @@
#
# ghlinkcmds
#
-map
-sec
{
.text 0x80010000 :
.data align(16) :
.rodata :
.fini :
# .sdata :
.symtab :
.strtab :
.debug :
# .sbss :
.bss align(8) :
.init 0xbfc00000 :
}

10
bsps/mips/hurricane/start/inittlb.c Normal file
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@@ -0,0 +1,10 @@
#include <bsp.h>
#include <rtems/mips/idtcpu.h>
void init_tlb(void)
{
int i;
for (i = 0; i < N_TLB_ENTRIES; i++ )
resettlb(i);
}

188
bsps/mips/hurricane/start/linkcmds Normal file
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@@ -0,0 +1,188 @@
/*
* linkcmds
*/
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x80000000;
RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
ENTRY(start)
STARTUP(start.o)
SECTIONS
{
/* 0x80000000 - 0x8001FFFF used by PMON (with 0x80010000 - 0x8001FFFF as heap for symbol storage)
0x80020000 - 0x8002FFFF reserved for shared memory
0x80030000 beginning of text (code) section
*/
.text 0x80030000 :
{
_ftext = . ;
eprol = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
}
.init :
{
KEEP(*crti.o(.init))
KEEP(*(.init))
KEEP(*crtn.o(.init))
}
.fini :
{
KEEP(*crti.o(.fini))
KEEP(*(.fini))
KEEP(*crtn.o(.fini))
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
}
.rdata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
KEEP (*(SORT(.rtemsroset.*)))
*(.gnu.linkonce.r*)
}
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
}
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
}
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
_fdata = ALIGN(16);
.data : {
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
}
. = ALIGN(8);
.jcr : {
KEEP (*(.jcr))
}
_gp = ALIGN(16) + 0x8000;
__global = _gp;
.sdata : {
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s*)
}
.lit8 : {
*(.lit8)
}
.lit4 : {
*(.lit4)
}
edata = .;
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
end = .;
_end = .;
WorkAreaBase = .;
}
/* Debug sections. These should never be loadable, but they must have
zero addresses for the debuggers to work correctly. */
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

180
bsps/mips/hurricane/start/usc.S Normal file
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@@ -0,0 +1,180 @@
/* usc.S
*
* COPYRIGHT (c) 1989-2010.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bspopts.h>
#include <rtems/asm.h>
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#if BSP_HAS_USC320
#include <usc.h>
#endif
/***************************************************************************
**
** The following code was added to support boards using V3 USC320
** system controller chip.
**
****************************************************************************/
/*************************************************************
* init_hbt()
* Initialize the heartbeat timer
*/
FRAME(init_hbt,sp,0,ra)
.set noreorder
la t0,SYSTEM # Unlock USC registers
li t1,0xA5
sb t1,(t0)
la t0,WD_HBI # Initialize heatbeat and watchdog timers
# (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 4000 * 5 = 20000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
# (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 1000 * 20 = 20000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
# (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 10000 * 20 = 200000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14)
sw t1,(t0)
la t0,SYSTEM # Lock USC registers
li t1,0x60
sb t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(init_hbt)
/*************************************************************
* reset_wdt()
* Reset the watchdog timer
*/
FRAME(reset_wdt,sp,0,ra)
.set noreorder
la t0,WD_HBI+2 # Load address watchdog timer reset byte
li t1,WD_INIT
sb t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(reset_wdt)
/*************************************************************
* disable_wdt()
* Disable watchdog timer
*/
FRAME(disable_wdt,sp,0,ra)
.set noreorder
la t0,WD_HBI # Clear watchdog enable bit in control register
lw t1,(t0)
li t2,~WD_EN
and t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(disable_wdt)
/*************************************************************
* enable_hbi(ints)
* Enable the heartbeat interrupt
*/
FRAME(enable_hbi,sp,0,ra)
.set noreorder
la t0,INT_CFG3 # Enable heartbeat interrupt in USC320
lw t1,(t0)
li t2,(HBI_MASK | MODE_TOTEM_POLE)
or t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(enable_hbi)
/*************************************************************
* disable_hbi(ints)
* Disable the heartbeat interrupt
*/
FRAME(disable_hbi,sp,0,ra)
.set noreorder
la t0,INT_CFG3 # Disable heartbeat interrupt in USC320
lw t1,(t0)
li t2,~HBI_MASK
and t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(disable_hbi)
/*************************************************************
* enable_wdi()
* Enable the watchdog interrupt
*/
FRAME(enable_wdi,sp,0,ra)
.set noreorder
la t0,INT_CFG1 # Enable watchdog interrupt in USC320
lw t1,(t0)
li t2,(WDI_MASK | MODE_TOTEM_POLE)
or t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(enable_wdi)
/*************************************************************
* disable_wdi(ints)
* Disable the watchdog interrupt
*/
FRAME(disable_wdi,sp,0,ra)
.set noreorder
la t0,INT_CFG1 # Disable watchdog interrupt in USC320
lw t1,(t0)
li t2,~(WDI_MASK | MODE_TOTEM_POLE)
and t1,t1,t2
sw t1,(t0)
la t0,INT_STAT # Clear watchdog interrupt status bit
li t1,WDI_MASK
sw t1,(t0)
.set reorder
j ra
nop
.set reorder
ENDFRAME(disable_wdi)

9
bsps/mips/jmr3904/start/bsp_specs Normal file
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@@ -0,0 +1,9 @@
%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

65
bsps/mips/jmr3904/start/bspstart.c Normal file
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@@ -0,0 +1,65 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <libcpu/isr_entries.h>
#include <bsp/bootcard.h>
#include <bsp/irq-generic.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
/* Structure filled in by get_mem_info. Only the size field is
* actually used (to clear bss), so the others aren't even filled in.
*/
struct s_mem
{
unsigned int size;
unsigned int icsize;
unsigned int dcsize;
};
void bsp_start( void );
void clear_cache( void *address, size_t n );
void get_mem_info( struct s_mem *mem );
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
mips_set_sr( 0xff00 ); /* all interrupts unmasked but globally off */
/* depend on the IRC to take care of things */
bsp_interrupt_initialize();
}
/*
* Required routine by some gcc run-times.
*/
void clear_cache( void *address, size_t n )
{
}
void get_mem_info(
struct s_mem *mem
)
{
mem->size = 0x1000000; /* XXX figure out something here */
}

212
bsps/mips/jmr3904/start/linkcmds Normal file
View File

@@ -0,0 +1,212 @@
/*
* Based on jmr3904app-dram.ld from newlib 1.8.2
*/
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x88000000;
RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
ENTRY(_start)
STARTUP(start.o)
SECTIONS
{
. = 0x88000000;
.text :
{
_ftext = . ;
eprol = .;
*(.text*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
}
.rtemsroset : {
/* for pre rtems-libbsd FreeBSD code */
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = .;
*(set_domain_*);
*(set_pseudo_*);
KEEP (*(SORT(.rtemsroset.*)))
. = ALIGN (16);
_endtext = .;
}
.init :
{
KEEP(*(.init))
}
.fini :
{
KEEP(*(.fini))
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
}
.rdata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
}
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
}
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
}
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
_fdata = ALIGN(16);
.data : {
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
}
.rtemsrwset : {
KEEP (*(SORT(.rtemsrwset.*)))
}
. = ALIGN(8);
.jcr : {
KEEP (*(.jcr))
}
_gp = ALIGN(16) + 0x7440;
__global = _gp;
.sdata : {
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s*)
}
.lit8 : {
*(.lit8)
}
.lit4 : {
*(.lit4)
}
edata = .;
_edata = .;
_fbss = .;
.sbss : {
*(.sbss*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss*)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
WorkAreaBase = .;
_clear_end = .;
}
. = 0x88400000; /* reserve some memory for Work Area */
end = .;
_end = .;
/* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
the original script (when everything was in SRAM). */
/* __stack = 0x8000A000; */
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

9
bsps/mips/malta/start/bsp_specs Normal file
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%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

34
bsps/mips/malta/start/bspreset.c Normal file
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/**
* @file
*
* This file contains the code necessary to reset the Malta board.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp/bootcard.h>
void bsp_reset(void)
{
uint32_t *reset;
reset= (uint32_t *)0x9F000500;
/*
* Qemu understands 0x42 to reset simulated machine.
* We added code to recognize 0xFF to exit simulator.
*
* TBD: Qemu PC simulation has option to exit on reset.
* find processing of that command line option and
* use it to change behaviour of 0x42.
*/
// *reset = 0x42;
*reset = 0xFF;
}

113
bsps/mips/malta/start/bspstart.c Normal file
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/**
* @file
*
* This file contains the bsp_start() method and support.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <libcpu/isr_entries.h>
#include <bsp/bootcard.h>
#include <rtems/pci.h>
#include <bsp/irq-generic.h>
#include <bsp/i8259.h>
/*
* STRUCTURES
*/
/* Structure filled in by get_mem_info. Only the size field is
* actually used (to clear bss), so the others aren't even filled in.
*/
struct s_mem
{
unsigned int size;
unsigned int icsize;
unsigned int dcsize;
};
/*
* GLOBALS
*/
uint32_t bsp_clicks_per_microsecond;
/*
* PROTOTYPES
*/
void clear_cache( void *address, size_t n );
void get_mem_info( struct s_mem *mem );
/*
* EXTERNs
*/
extern int RamSize;
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
/* uint32_t board_ID = 0x420; */
static int j = 1;
int pci_init_retval;
/*
* Note: This is the value that works for qemu, and it was
* unable to be validated on the actual hardware.
*/
mips_set_sr( 0x04100000 );
bsp_interrupt_initialize();
/*
* XXX need to figure out a real value. :)
* This works for the qemu simulation, but timeing may
* be off for the actual hardware.
*/
bsp_clicks_per_microsecond = 100;
#if 1
while ( j != 1 ) {
int i;
printk (".");
for (i=0; i<1000; i++);
}
#endif
/*
* init PCI Bios interface...
*/
pci_init_retval = pci_initialize();
if (pci_init_retval != PCIB_ERR_SUCCESS) {
printk("PCI bus: could not initialize PCI BIOS interface\n");
}
BSP_i8259s_init();
}
/*
* Required routine by some gcc run-times.
*/
void clear_cache( void *address, size_t n )
{
}
void get_mem_info(
struct s_mem *mem
)
{
mem->size = (int) (&RamSize); /* Normally 128 or 256 MB */
}

27
bsps/mips/malta/start/inittlb.c Normal file
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/**
* @file
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/mips/idtcpu.h>
extern void resettlb( int i );
void init_tlb(void);
void init_tlb(void)
{
int i;
for (i = 0; i < N_TLB_ENTRIES; i++ )
resettlb(i);
}

213
bsps/mips/malta/start/linkcmds Normal file
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@@ -0,0 +1,213 @@
/*
* MIPS Malta Linker Script
*/
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x80000000;
RamSize = DEFINED(RamSize) ? RamSize : 128M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
ENTRY(_start)
STARTUP(start.o)
SECTIONS
{
. = 0x80010000;
.text :
{
_ftext = . ;
eprol = .;
*(.text*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
}
.init :
{
KEEP(*(.init))
}
.fini :
{
KEEP(*(.fini))
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
}
.rtemsroset : {
/* for pre rtems-libbsd FreeBSD code */
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = .;
*(set_domain_*);
*(set_pseudo_*);
KEEP (*(SORT(.rtemsroset.*)))
. = ALIGN (16);
_endtext = .;
}
.rdata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
}
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
}
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
}
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
_fdata = ALIGN(16);
.data : {
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
}
.rtemsrwset : {
KEEP (*(SORT(.rtemsrwset.*)))
}
. = ALIGN(8);
.jcr : {
KEEP (*(.jcr))
}
_gp = ALIGN(16) + 0x7440;
__global = _gp;
.sdata : {
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s*)
}
.lit8 : {
*(.lit8)
}
.lit4 : {
*(.lit4)
}
edata = .;
_edata = .;
_fbss = .;
.sbss : {
*(.sbss*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss*)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
WorkAreaBase = .;
_clear_end = .;
}
. = 0x88400000; /* reserve some memory for Work Area */
end = .;
_end = .;
/* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
the original script (when everything was in SRAM). */
/* __stack = 0x8000A000; */
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

133
bsps/mips/malta/start/simple_access.c Normal file
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/**
* @file
*
* This file contains the code to do simple memory and io accesses.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <bsp/pci.h>
#include <bsp/irq.h>
#include <rtems/bspIo.h>
#include <rtems/endian.h>
// #define DEBUG_ACCESSES 1
#ifdef DEBUG_ACCESSES
#define JPRINTK(fmt, ...) printk("%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
#define JPRINTK(fmt, ...)
#endif
/*
* * Simple accesses
* */
void simple_out_32(uint32_t base, uint32_t addr, uint32_t val)
{
volatile uint32_t *ptr;
ptr = (volatile uint32_t *) (base + addr);
*ptr = val;
JPRINTK( "%p data: 0x%x\n", ptr, val);
}
void simple_out_le32(uint32_t base, uint32_t addr, uint32_t val)
{
volatile uint32_t *ptr;
uint32_t data = 0;
ptr = (volatile uint32_t *) (base + addr);
rtems_uint32_to_little_endian( val, (uint8_t *) &data);
*ptr = data;
JPRINTK( "%p data: 0x%x\n", ptr, data);
}
uint8_t simple_in_8( uint32_t base, uint32_t addr ) {
volatile uint8_t *ptr;
uint8_t val;
ptr = (volatile uint8_t *) (base + addr);
val = *ptr;
JPRINTK( "0x%x data: 0x%x\n", ptr, val);
return val;
}
int16_t simple_in_le16( uint32_t base, uint32_t addr ) {
volatile uint16_t *ptr;
uint16_t val;
uint16_t rval;
ptr = (volatile uint16_t *) (base + addr);
val = *ptr;
rval = rtems_uint16_from_little_endian( (uint8_t *) &val);
JPRINTK( "0x%x data: 0x%x raw: 0x%x\n", ptr, rval, val);
return rval;
}
int16_t simple_in_16( uint32_t base, uint32_t addr ) {
volatile uint16_t *ptr;
uint16_t val;
ptr = (volatile uint16_t *) (base + addr);
val = *ptr;
JPRINTK( "0x%x data: 0x%x raw: 0x%x\n", ptr, val, val);
return val;
}
uint32_t simple_in_le32( uint32_t base, uint32_t addr ) {
volatile uint32_t *ptr;
uint32_t val;
uint32_t rval;
ptr = (volatile uint32_t *) (base + addr);
val = *ptr;
rval = rtems_uint32_from_little_endian( (uint8_t *) &val);
JPRINTK( "0x%x data: 0x%x raw: 0x%x\n", ptr, rval, val);
return rval;
}
uint32_t simple_in_32( uint32_t base, uint32_t addr ) {
volatile uint32_t *ptr;
uint32_t val;
ptr = (volatile uint32_t *) (base + addr);
val = *ptr;
JPRINTK( "0x%x data: 0x%x raw: 0x%x\n", ptr, val, val);
return val;
}
void simple_out_8( uint32_t base, uint32_t addr, uint8_t val ) {
volatile uint8_t *ptr;
ptr = (volatile uint8_t *) (base | addr);
JPRINTK( "0x%x data: 0x%x\n", ptr, val);
*ptr = val;
}
void simple_out_le16( uint32_t base, uint32_t addr, uint16_t val ) {
volatile uint16_t *ptr;
uint16_t data;
ptr = (volatile uint16_t *) (base + addr);
rtems_uint16_to_little_endian( val, (uint8_t *) &data);
*ptr = data;
JPRINTK( "0x%x data: 0x%x\n", ptr, data);
}
void simple_out_16( uint32_t base, uint32_t addr, uint16_t val ) {
volatile uint16_t *ptr;
ptr = (volatile uint16_t *) (base + addr);
*ptr = val;
JPRINTK( "0x%x data: 0x%x\n", ptr, val);
}

9
bsps/mips/rbtx4925/start/bsp_specs Normal file
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@@ -0,0 +1,9 @@
%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

34
bsps/mips/rbtx4925/start/bspstart.c Normal file
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@@ -0,0 +1,34 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <libcpu/isr_entries.h>
#include <bsp/irq-generic.h>
void bsp_start( void );
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
bsp_interrupt_initialize();
}

388
bsps/mips/rbtx4925/start/idttlb.S Normal file
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@@ -0,0 +1,388 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*/
/*
** idttlb.s - fetch the registers associated with and the contents
** of the tlb.
**
*/
/* 950308: Ketan patched a few tlb functions that would not have worked.*/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
.text
#if __mips == 1
/*
** ret_tlblo -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo,sp,0,ra)
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # write to index register
nop
tlbr # put tlb entry in entrylo and hi
nop
mfc0 v0,C0_TLBLO # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
nop
.set reorder
ENDFRAME(ret_tlblo)
#endif
#if __mips == 3
/*
** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo0,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO0 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo0)
FRAME(ret_tlblo1,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO1 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo1)
/*
** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
*/
FRAME(ret_pagemask,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_PAGEMASK # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
ENDFRAME(ret_pagemask)
/*
** ret_tlbwired(void) -- return wired register
*/
FRAME(ret_tlbwired,sp,0,ra)
mfc0 v0,C0_WIRED
j ra
ENDFRAME(ret_tlbwired)
#endif
/*
** ret_tlbhi -- return the tlb entry high content for tlb entry
** index
*/
FRAME(ret_tlbhi,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # drop it in C0 register
nop
tlbr # read entry to entry hi/lo
nop
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(ret_tlbhi)
/*
** ret_tlbpid() -- return tlb pid contained in the current entry hi
*/
FRAME(ret_tlbpid,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 v0,C0_TLBHI # to return value
nop
and v0,TLBHI_PIDMASK
j ra
#endif
ENDFRAME(ret_tlbpid)
/*
** tlbprobe(address, pid) -- probe the tlb to see if address is currently
** mapped
** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
** virtual page numbers for the r3000 are in
** entry hi bits 31-12
** a1 = pid - this is a process id ranging from 0 to 63
** this process id is shifted left 6 bits and or'ed into
** the entry hi register
** returns an index value (0-63) if successful -1 -f not
*/
FRAME(tlbprobe,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
mtc0 a0,C0_TLBHI
nop
tlbp /* do the probe */
nop
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
nop
sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */
1:
mtc0 t1,C0_TLBHI /* restore tlb hi */
mtc0 t0,C0_SR /* restore the status reg */
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
and a0,TLBHI_VPN2MASK # construct tlbhi for probe
and a1,TLBHI_PIDMASK
or a0,a1
mtc0 a0,C0_TLBHI
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbp # probe entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
move v0,v1
1: mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(tlbprobe)
/*
** resettlb(index) Invalidate the TLB entry specified by index
*/
FRAME(resettlb,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # set up tlbhi
mtc0 zero,C0_TLBLO
sll a0,TLBINX_INXSHIFT
mtc0 a0,C0_INX
nop
tlbwi # do actual invalidate
nop
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
nop
.set reorder
#endif
#if __mips == 3
li t2,K0BASE&TLBHI_VPN2MASK
mfc0 t0,C0_TLBHI # save current TLBHI
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # invalidate entry
mtc0 zero,C0_TLBLO0
mtc0 zero,C0_TLBLO1
mtc0 a0,C0_INX
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
#endif
ENDFRAME(resettlb)
#if __mips == 1
/*
** Setup TLB entry
**
** map_tlb(index, tlbhi, phypage)
** a0 = TLB entry index
** a1 = virtual page number and PID
** a2 = physical page
*/
FRAME(map_tlb,sp,0,ra)
.set noreorder
sll a0,TLBINX_INXSHIFT
mfc0 v0,C0_SR # fetch the current status
mfc0 a3,C0_TLBHI # save the current hi
and v0,~SR_PE # dont inadvertantly clear parity
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
ENDFRAME(map_tlb)
#endif
#if __mips == 3
/*
** Setup R4000 TLB entry
**
** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
** a0 = TLB entry index and page mask
** a1 = virtual page number and PID
** a2 = pte -- contents of even pte
** a3 = pte -- contents of odd pte
*/
FRAME(map_tlb4000,sp,0,ra)
and t2,a0,TLBPGMASK_MASK
and a0,TLBINX_INXMASK
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits
mtc0 a0,C0_INX # set INDEX to wired entry
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi # drop it in
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t1,C0_TLBHI # restore TLBPID
mtc0 v0,C0_SR # restore SR
j ra
ENDFRAME(map_tlb4000)
#endif
/*
** Set current TLBPID. This assumes PID is positioned correctly in reg.
** a0.
*/
FRAME(set_tlbpid,sp,0,ra)
.set noreorder
mtc0 a0,C0_TLBHI
j ra
nop
.set reorder
ENDFRAME(set_tlbpid)

17
bsps/mips/rbtx4925/start/inittlb.c Normal file
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/*
* inittlb.c
*/
#include <bsp.h>
#include <rtems/mips/idtcpu.h>
extern void resettlb( int i );
void init_tlb(void)
{
int i;
for (i = 0; i < N_TLB_ENTRIES; i++ )
resettlb(i);
}

188
bsps/mips/rbtx4925/start/linkcmds Normal file
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@@ -0,0 +1,188 @@
/*
* linkcmds
*/
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x80000000;
RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
ENTRY(start)
STARTUP(start.o)
SECTIONS
{
/* 0x80000000 - 0x8001FFFF used by PMON (with 0x80010000 - 0x8001FFFF as heap for symbol storage)
0x80020000 - 0x8002FFFF reserved for shared memory
0x80030000 beginning of text (code) section
*/
.text 0x80030000 :
{
_ftext = . ;
eprol = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
}
.init :
{
KEEP(*crti.o(.init))
KEEP(*(.init))
KEEP(*crtn.o(.init))
}
.fini :
{
KEEP(*crti.o(.fini))
KEEP(*(.fini))
KEEP(*crtn.o(.fini))
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
}
.rdata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
KEEP (*(SORT(.rtemsroset.*)))
*(.gnu.linkonce.r*)
}
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
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.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
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_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
_fdata = ALIGN(16);
.data : {
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
}
. = ALIGN(8);
.jcr : {
KEEP (*(.jcr))
}
_gp = ALIGN(16) + 0x8000;
__global = _gp;
.sdata : {
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s*)
}
.lit8 : {
*(.lit8)
}
.lit4 : {
*(.lit4)
}
edata = .;
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_fbss = .;
.sbss : {
*(.sbss)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
end = .;
_end = .;
WorkAreaBase = .;
}
/* Debug sections. These should never be loadable, but they must have
zero addresses for the debuggers to work correctly. */
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

9
bsps/mips/rbtx4938/start/bsp_specs Normal file
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@@ -0,0 +1,9 @@
%rename endfile old_endfile
%rename startfile old_startfile
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}

33
bsps/mips/rbtx4938/start/bspstart.c Normal file
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@@ -0,0 +1,33 @@
/**
* @file
*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*/
/*
* COPYRIGHT (c) 1989-2012.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <libcpu/isr_entries.h>
#include <bsp/irq-generic.h>
void bsp_start( void );
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
bsp_interrupt_initialize();
}

17
bsps/mips/rbtx4938/start/inittlb.c Normal file
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@@ -0,0 +1,17 @@
/*
* inittlb.c
*/
#include <bsp.h>
#include <rtems/mips/idtcpu.h>
extern void resettlb( int i );
void init_tlb(void)
{
int i;
for (i = 0; i < N_TLB_ENTRIES; i++ )
resettlb(i);
}

188
bsps/mips/rbtx4938/start/linkcmds Normal file
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@@ -0,0 +1,188 @@
/*
* linkcmds
*/
/*
* Declare some sizes.
*/
RamBase = DEFINED(RamBase) ? RamBase : 0x80000000;
RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
ENTRY(start)
STARTUP(start.o)
SECTIONS
{
/* 0x80000000 - 0x800FFFFF used by YAMON
0x80120000 - 0x8012FFFF reserved for shared memory
0x80130000 beginning of text (code) section
*/
.text 0x80130000 :
{
_ftext = . ;
eprol = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
*(.gcc_except_table*)
*(.eh_frame_hdr)
*(.eh_frame)
}
.init :
{
KEEP(*crti.o(.init))
KEEP(*(.init))
KEEP(*crtn.o(.init))
}
.fini :
{
KEEP(*crti.o(.fini))
KEEP(*(.fini))
KEEP(*crtn.o(.fini))
}
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
etext = .;
_etext = .;
}
.rdata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
KEEP (*(SORT(.rtemsroset.*)))
*(.gnu.linkonce.r*)
}
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
}
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
}
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
_fdata = ALIGN(16);
.data : {
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
}
. = ALIGN(8);
.jcr : {
KEEP (*(.jcr))
}
_gp = ALIGN(16) + 0x8000;
__global = _gp;
.sdata : {
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s*)
}
.lit8 : {
*(.lit8)
}
.lit4 : {
*(.lit4)
}
edata = .;
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(COMMON)
. = ALIGN (64);
_stack_limit = .;
. += _StackSize;
__stack = .;
_stack_init = .;
end = .;
_end = .;
WorkAreaBase = .;
}
/* Debug sections. These should never be loadable, but they must have
zero addresses for the debuggers to work correctly. */
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

920
bsps/mips/shared/start/idtmem.S Normal file
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@@ -0,0 +1,920 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*/
/************************************************************************
**
** idtmem.s - memory and cache functions
**
** Copyright 1991 Integrated Device Technology, Inc.
** All Rights Reserved
**
**************************************************************************/
/*
* 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
* to set mem_size.
*/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
.data
mem_size:
.word 0
dcache_size:
.word 0
icache_size:
#if __mips == 1
.word MINCACHE
#endif
#if __mips == 3
.word 0
#endif
#if __mips == 3
.data
scache_size:
.word 0
icache_linesize:
.word 0
dcache_linesize:
.word 0
scache_linesize:
.word 0
#endif
.text
#if __mips == 1
#define CONFIGFRM ((2*4)+4)
/*************************************************************************
**
** Config_Dcache() -- determine size of Data cache
**
**************************************************************************/
FRAME(config_Dcache,sp, CONFIGFRM, ra)
.set noreorder
subu sp,CONFIGFRM
sw ra,CONFIGFRM-4(sp) /* save return address */
sw s0,4*4(sp) /* save s0 in first regsave slot */
mfc0 s0,C0_SR /* save SR */
nop
mtc0 zero,C0_SR /* disable interrupts */
.set reorder
jal _size_cache /* returns Data cache size in v0 */
sw v0, dcache_size /* save it */
and s0, ~SR_PE /* do not clear PE */
.set noreorder
mtc0 s0,C0_SR /* restore SR */
nop
.set reorder
lw s0, 4*4(sp) /* restore s0 */
lw ra,CONFIGFRM-4(sp) /* restore ra */
addu sp,CONFIGFRM /* pop stack */
j ra
ENDFRAME(config_Dcache)
/*************************************************************************
**
** Config_Icache() -- determine size of Instruction cache
** MUST be run in uncached mode/handled in idt_csu.s
**
**************************************************************************/
FRAME(config_Icache,sp, CONFIGFRM, ra)
.set noreorder
subu sp,CONFIGFRM
sw ra,CONFIGFRM-4(sp) /* save return address */
sw s0,4*4(sp) /* save s0 in first regsave slot */
mfc0 s0,C0_SR /* save SR */
nop
mtc0 zero, C0_SR /* disable interrupts */
li v0,SR_SWC /* swap caches/disable ints */
mtc0 v0,C0_SR
nop
.set reorder
jal _size_cache /* returns instruction cache size */
.set noreorder
mtc0 zero,C0_SR /* swap back caches */
nop
and s0,~SR_PE /* do not inadvertantly clear PE */
mtc0 s0,C0_SR /* restore SR */
nop
.set reorder
sw v0, icache_size /* save it AFTER caches back */
lw s0,4*4(sp) /* restore s0 */
lw ra,CONFIGFRM-4(sp) /* restore ra */
addu sp,CONFIGFRM /* pop stack */
j ra
ENDFRAME(config_Icache)
/************************************************************************
**
** _size_cache()
** returns cache size in v0
**
************************************************************************/
FRAME(_size_cache,sp,0,ra)
.set noreorder
mfc0 t0,C0_SR /* save current sr */
nop
and t0,~SR_PE /* do not inadvertently clear PE */
or v0,t0,SR_ISC /* isolate cache */
mtc0 v0,C0_SR
/*
* First check if there is a cache there at all
*/
move v0,zero
li v1,0xa5a5a5a5 /* distinctive pattern */
sw v1,K0BASE /* try to write into cache */
lw t1,K0BASE /* try to read from cache */
nop
mfc0 t2,C0_SR
nop
.set reorder
and t2,SR_CM
bne t2,zero,3f /* cache miss, must be no cache */
bne v1,t1,3f /* data not equal -> no cache */
/*
* Clear cache size boundries to known state.
*/
li v0,MINCACHE
1:
sw zero,K0BASE(v0)
sll v0,1
ble v0,MAXCACHE,1b
li v0,-1
sw v0,K0BASE(zero) /* store marker in cache */
li v0,MINCACHE /* MIN cache size */
2: lw v1,K0BASE(v0) /* Look for marker */
bne v1,zero,3f /* found marker */
sll v0,1 /* cache size * 2 */
ble v0,MAXCACHE,2b /* keep looking */
move v0,zero /* must be no cache */
.set noreorder
3: mtc0 t0,C0_SR /* restore sr */
j ra
nop
ENDFRAME(_size_cache)
.set reorder
#define FLUSHFRM (2*4)
/***************************************************************************
**
** flush_Dcache() - flush entire Data cache
**
****************************************************************************/
FRAME(flush_Dcache,sp,FLUSHFRM,ra)
lw t2, dcache_size
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
and t3,~SR_PE /* dont inadvertently clear PE */
beq t2,zero,_Dflush_done /* no D cache, get out! */
nop
li v0, SR_ISC /* isolate cache */
mtc0 v0, C0_SR
nop
.set reorder
li t0,K0BASE /* set loop registers */
or t1,t0,t2
2: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bne t0,t1,2b
.set noreorder
_Dflush_done:
mtc0 t3,C0_SR /* restore Status Register */
.set reorder
j ra
ENDFRAME(flush_Dcache)
/***************************************************************************
**
** flush_Icache() - flush entire Instruction cache
**
** NOTE: Icache can only be flushed/cleared when uncached
** Code forces into uncached memory regardless of calling mode
**
****************************************************************************/
FRAME(flush_Icache,sp,FLUSHFRM,ra)
lw t1,icache_size
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
la v0,1f
li v1,K1BASE
or v0,v1
j v0 /* force into non-cached space */
nop
1:
and t3,~SR_PE /* dont inadvertently clear PE */
beq t1,zero,_Iflush_done /* no i-cache get out */
nop
li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
mtc0 v0,C0_SR
li t0,K0BASE
.set reorder
or t1,t0,t1
1: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bne t0,t1,1b
.set noreorder
_Iflush_done:
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
.set reorder
j ra
ENDFRAME(flush_Icache)
/**************************************************************************
**
** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
**
** a0 = base address of portion to be cleared
** a1 = byte count of length
**
***************************************************************************/
FRAME(clear_Dcache,sp,0,ra)
lw t2, dcache_size /* Data cache size */
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
and t3,~SR_PE /* dont inadvertently clear PE */
nop
nop
.set reorder
/*
* flush data cache
*/
.set noreorder
nop
li v0,SR_ISC /* isolate data cache */
mtc0 v0,C0_SR
.set reorder
bltu t2,a1,1f /* cache is smaller than region */
move t2,a1
1: addu t2,a0 /* ending address + 1 */
move t0,a0
1: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bltu t0,t2,1b
.set noreorder
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
nop
.set reorder
j ra
ENDFRAME(clear_Dcache)
/**************************************************************************
**
** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
**
** a0 = base address of portion to be cleared
** a1 = byte count of length
**
** NOTE: Icache can only be flushed/cleared when uncached
** Code forces into uncached memory regardless of calling mode
**
***************************************************************************/
FRAME(clear_Icache,sp,0,ra)
lw t1, icache_size /* Instruction cache size */
/*
* flush text cache
*/
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
la v0,1f
li v1,K1BASE
or v0,v1
j v0 /* force into non-cached space */
nop
1:
and t3,~SR_PE /* dont inadvertently clear PE */
nop
nop
li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
mtc0 v0,C0_SR
.set reorder
bltu t1,a1,1f /* cache is smaller than region */
move t1,a1
1: addu t1,a0 /* ending address + 1 */
move t0,a0
sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bltu t0,t1,1b
.set noreorder
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
nop
nop
nop /* allow time for caches to swap */
.set reorder
j ra
ENDFRAME(clear_Icache)
/**************************************************************************
**
** get_mem_conf - get memory configuration
**
***************************************************************************/
FRAME(get_mem_conf,sp,0,ra)
lw t6, mem_size
sw t6, 0(a0)
lw t7, icache_size
sw t7, 4(a0)
lw t8, dcache_size
sw t8, 8(a0)
j ra
ENDFRAME(get_mem_conf)
#endif /* __mips == 1 */
#if __mips == 3
#define LEAF(label) FRAME(label,sp,0,ra)
#define XLEAF(label) \
.globl label ; \
label:
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,8f ; \
move size,maxsize ; \
8:
#define _align(tmp, minaddr, maxaddr, linesize) \
subu tmp,linesize,1 ; \
not tmp ; \
and minaddr,tmp ; \
addu maxaddr,-1 ; \
and maxaddr,tmp
/* This is a bit of a hack really because it relies on minaddr=a0 */
#define _doop1(op1) \
cache op1,0(a0)
#define _doop2(op1, op2) \
cache op1,0(a0) ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define _doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define _doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
7: _doop##tag##ops ; \
bne minaddr,maxaddr,7b ; \
addu minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
_mincache(n, cache_size); \
blez n,9f ; \
addu n,kva ; \
_align(t1, kva, n, cache_linesize) ; \
_oploopn(kva, n, cache_linesize, tag, ops) ; \
9:
#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
blez n,9f ; \
addu n,kva ; \
_align(t1, kva, n, cache_linesize) ; \
_oploopn(kva, n, cache_linesize, tag, ops) ; \
9:
#define icacheop(kva, n, cache_size, cache_linesize, op) \
icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
#define vcacheop(kva, n, cache_size, cache_linesize, op) \
vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
.text
/*
* static void _size_cache() R4000
*
* Internal routine to determine cache sizes by looking at R4000 config
* register. Sizes are returned in registers, as follows:
* t2 icache size
* t3 dcache size
* t6 scache size
* t4 icache line size
* t5 dcache line size
* t7 scache line size
*/
LEAF(_size_cache)
mfc0 t0,C0_CONFIG
and t1,t0,CFG_ICMASK
srl t1,CFG_ICSHIFT
li t2,0x1000
sll t2,t1
and t1,t0,CFG_DCMASK
srl t1,CFG_DCSHIFT
li t3,0x1000
sll t3,t1
li t4,32
and t1,t0,CFG_IB
bnez t1,1f
li t4,16
1:
li t5,32
and t1,t0,CFG_DB
bnez t1,1f
li t5,16
1:
move t6,zero # default to no scache
move t7,zero #
and t1,t0,CFG_C_UNCACHED # test config register
bnez t1,1f # no scache if uncached/non-coherent
li t6,0x100000 # assume 1Mb scache <<-NOTE
and t1,t0,CFG_SBMASK
srl t1,CFG_SBSHIFT
li t7,16
sll t7,t1
1: j ra
ENDFRAME(_size_cache)
/*
* void config_cache() R4000
*
* Work out size of I, D & S caches, assuming they are already initialised.
*/
LEAF(config_cache)
lw t0,icache_size
bgtz t0,8f # already known?
move v0,ra
bal _size_cache
move ra,v0
sw t2,icache_size
sw t3,dcache_size
sw t6,scache_size
sw t4,icache_linesize
sw t5,dcache_linesize
sw t7,scache_linesize
8: j ra
ENDFRAME(config_cache)
/*
* void _init_cache() R4000
*/
LEAF(_init_cache)
/*
* First work out the sizes
*/
move v0,ra
bal _size_cache
move ra,v0
/*
* The caches may be in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
/* disable all i/u and cache exceptions */
mfc0 v0,C0_SR
and v1,v0,~SR_IE
or v1,SR_DE
mtc0 v1,C0_SR
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
/* assume bottom of RAM will generate good parity for the cache */
li a0,PHYS_TO_K0(0)
move a2,t2 # icache_size
move a3,t4 # icache_linesize
move a1,a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
li a0,PHYS_TO_K0(0)
move a2,t3 # dcache_size
move a3,t5 # dcache_linesize
move a1,a2
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
/* assume unified I & D in scache <<-NOTE */
blez t6,1f
li a0,PHYS_TO_K0(0)
move a2,t6
move a3,t7
move a1,a2
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
1: mtc0 v0,C0_SR
j ra
ENDFRAME(_init_cache)
/*
* void flush_cache (void) R4000
*
* Flush and invalidate all caches
*/
LEAF(flush_cache)
/* secondary cacheops do all the work if present */
lw a2,scache_size
blez a2,1f
lw a3,scache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
b 2f
1:
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
lw a2,dcache_size
lw a3,dcache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
2: j ra
ENDFRAME(flush_cache)
/*
* void flush_cache_nowrite (void) R4000
*
* Invalidate all caches
*/
LEAF(flush_cache_nowrite)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
lw a2,dcache_size
lw a3,dcache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
2: mtc0 v0,C0_SR
j ra
ENDFRAME(flush_cache_nowrite)
/*
* void clean_cache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in all caches
*/
LEAF(clean_cache)
XLEAF(clear_cache)
/* secondary cacheops do all the work (if fitted) */
lw a2,scache_size
blez a2,1f
lw a3,scache_linesize
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
b 2f
1: lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
/* save kva & n for subsequent loop */
move t8,a0
move t9,a1
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
lw a2,dcache_size
lw a3,dcache_linesize
/* restore kva & n */
move a0,t8
move a1,t9
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
2: j ra
ENDFRAME(clean_cache)
/*
* void clean_dcache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in primary data cache
*/
LEAF(clean_dcache)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
2: j ra
ENDFRAME(clean_dcache)
/*
* void clean_dcache_indexed (unsigned kva, size_t n) R4000
*
* Writeback and invalidate indexed range in primary data cache
*/
LEAF(clean_dcache_indexed)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
2: j ra
ENDFRAME(clean_dcache_indexed)
/*
* void clean_dcache_nowrite (unsigned kva, size_t n) R4000
*
* Invalidate an address range in primary data cache
*/
LEAF(clean_dcache_nowrite)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
2: j ra
ENDFRAME(clean_dcache_nowrite)
/*
* void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in primary data cache
*/
LEAF(clean_dcache_nowrite_indexed)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
2: mtc0 v0,C0_SR
j ra
ENDFRAME(clean_dcache_nowrite_indexed)
/*
* void clean_icache (unsigned kva, size_t n) R4000
*
* Invalidate address range in primary instruction cache
*/
LEAF(clean_icache)
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
2: j ra
ENDFRAME(clean_icache)
/*
* void clean_icache_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in primary instruction cache
*/
LEAF(clean_icache_indexed)
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
2: j ra
ENDFRAME(clean_icache_indexed)
/*
* void clean_scache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in secondary cache
*/
LEAF(clean_scache)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
2: j ra
ENDFRAME(clean_scache)
/*
* void clean_scache_indexed (unsigned kva, size_t n) R4000
*
* Writeback and invalidate indexed range in secondary cache
*/
LEAF(clean_scache_indexed)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
2: j ra
ENDFRAME(clean_scache_indexed)
/*
* void clean_scache_nowrite (unsigned kva, size_t n) R4000
*
* Invalidate an address range in secondary cache
*/
LEAF(clean_scache_nowrite)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
2: j ra
ENDFRAME(clean_scache_nowrite)
/*
* void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in secondary cache
*/
LEAF(clean_scache_nowrite_indexed)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
2: mtc0 v0,C0_SR
j ra
ENDFRAME(clean_scache_nowrite_indexed)
/**************************************************************************
**
** get_mem_conf - get memory configuration R4000
**
***************************************************************************/
FRAME(get_mem_conf,sp,0,ra)
lw t6, mem_size
sw t6, 0(a0)
lw t7, icache_size
sw t7, 4(a0)
lw t8, dcache_size
sw t8, 8(a0)
lw t7, scache_size
sw t7, 12(a0)
j ra
ENDFRAME(get_mem_conf)
#endif /* __mips == 3 */
/*
* void set_mem_size (mem_size)
*
* config_memory()'s memory size gets written into mem_size here.
* Now we don't need to call config_cache() with memory size - New to IDTC6.0
*/
FRAME(set_memory_size,sp,0,ra)
sw a0, mem_size
j ra
ENDFRAME(set_memory_size)

388
bsps/mips/shared/start/idttlb.S Normal file
View File

@@ -0,0 +1,388 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*/
/*
** idttlb.s - fetch the registers associated with and the contents
** of the tlb.
**
*/
/* 950308: Ketan patched a few tlb functions that would not have worked.*/
#include <rtems/mips/iregdef.h>
#include <rtems/mips/idtcpu.h>
#include <rtems/asm.h>
.text
#if __mips == 1
/*
** ret_tlblo -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo,sp,0,ra)
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # write to index register
nop
tlbr # put tlb entry in entrylo and hi
nop
mfc0 v0,C0_TLBLO # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
nop
.set reorder
ENDFRAME(ret_tlblo)
#endif
#if __mips == 3
/*
** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo0,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO0 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo0)
FRAME(ret_tlblo1,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO1 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo1)
/*
** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
*/
FRAME(ret_pagemask,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_PAGEMASK # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
ENDFRAME(ret_pagemask)
/*
** ret_tlbwired(void) -- return wired register
*/
FRAME(ret_tlbwired,sp,0,ra)
mfc0 v0,C0_WIRED
j ra
ENDFRAME(ret_tlbwired)
#endif
/*
** ret_tlbhi -- return the tlb entry high content for tlb entry
** index
*/
FRAME(ret_tlbhi,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # drop it in C0 register
nop
tlbr # read entry to entry hi/lo
nop
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(ret_tlbhi)
/*
** ret_tlbpid() -- return tlb pid contained in the current entry hi
*/
FRAME(ret_tlbpid,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 v0,C0_TLBHI # to return value
nop
and v0,TLBHI_PIDMASK
j ra
#endif
ENDFRAME(ret_tlbpid)
/*
** tlbprobe(address, pid) -- probe the tlb to see if address is currently
** mapped
** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
** virtual page numbers for the r3000 are in
** entry hi bits 31-12
** a1 = pid - this is a process id ranging from 0 to 63
** this process id is shifted left 6 bits and or'ed into
** the entry hi register
** returns an index value (0-63) if successful -1 -f not
*/
FRAME(tlbprobe,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
mtc0 a0,C0_TLBHI
nop
tlbp /* do the probe */
nop
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
nop
sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */
1:
mtc0 t1,C0_TLBHI /* restore tlb hi */
mtc0 t0,C0_SR /* restore the status reg */
j ra
nop
.set reorder
#endif
#if __mips == 3
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
and a0,TLBHI_VPN2MASK # construct tlbhi for probe
and a1,TLBHI_PIDMASK
or a0,a1
mtc0 a0,C0_TLBHI
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbp # probe entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
move v0,v1
1: mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(tlbprobe)
/*
** resettlb(index) Invalidate the TLB entry specified by index
*/
FRAME(resettlb,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # set up tlbhi
mtc0 zero,C0_TLBLO
sll a0,TLBINX_INXSHIFT
mtc0 a0,C0_INX
nop
tlbwi # do actual invalidate
nop
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
nop
.set reorder
#endif
#if __mips == 3
li t2,K0BASE&TLBHI_VPN2MASK
mfc0 t0,C0_TLBHI # save current TLBHI
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # invalidate entry
mtc0 zero,C0_TLBLO0
mtc0 zero,C0_TLBLO1
mtc0 a0,C0_INX
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
#endif
ENDFRAME(resettlb)
#if __mips == 1
/*
** Setup TLB entry
**
** map_tlb(index, tlbhi, phypage)
** a0 = TLB entry index
** a1 = virtual page number and PID
** a2 = physical page
*/
FRAME(map_tlb,sp,0,ra)
.set noreorder
sll a0,TLBINX_INXSHIFT
mfc0 v0,C0_SR # fetch the current status
mfc0 a3,C0_TLBHI # save the current hi
and v0,~SR_PE # dont inadvertantly clear parity
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
ENDFRAME(map_tlb)
#endif
#if __mips == 3
/*
** Setup R4000 TLB entry
**
** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
** a0 = TLB entry index and page mask
** a1 = virtual page number and PID
** a2 = pte -- contents of even pte
** a3 = pte -- contents of odd pte
*/
FRAME(map_tlb4000,sp,0,ra)
and t2,a0,TLBPGMASK_MASK
and a0,TLBINX_INXMASK
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits
mtc0 a0,C0_INX # set INDEX to wired entry
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi # drop it in
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t1,C0_TLBHI # restore TLBPID
mtc0 v0,C0_SR # restore SR
j ra
ENDFRAME(map_tlb4000)
#endif
/*
** Set current TLBPID. This assumes PID is positioned correctly in reg.
** a0.
*/
FRAME(set_tlbpid,sp,0,ra)
.set noreorder
mtc0 a0,C0_TLBHI
j ra
nop
.set reorder
ENDFRAME(set_tlbpid)