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arm: Select the TLB invalidate based on the core's Id variant.

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Closes #3760
This commit is contained in:
Chris Johns
2019-06-25 20:48:51 +10:00
parent 57e0173584
commit 98d6792376
1 changed files with 10 additions and 6 deletions
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16
bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
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@@ -65,12 +65,16 @@ static uint32_t set_translation_table_entries(
for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
#if defined(__ARM_ARCH_7A__)
arm_cp15_tlb_invalidate_entry_all_asids(mva);
#else
arm_cp15_tlb_instruction_invalidate_entry(mva);
arm_cp15_tlb_data_invalidate_entry(mva);
#endif
#if defined(__ARM_ARCH_7A__)
if ((arm_cp15_get_multiprocessor_affinity() & (1 << 30)) == 0) {
arm_cp15_tlb_invalidate_entry_all_asids(mva);
}
else
#endif
{
arm_cp15_tlb_instruction_invalidate_entry(mva);
arm_cp15_tlb_data_invalidate_entry(mva);
}
}
_ARM_Data_synchronization_barrier();