RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2011-08-31 Sebastian Huber <sebastian.huber@embedded-brains.de>

Browse Source 
* mpc55xx/include/fsl-mpc551x.h, mpc55xx/include/fsl-mpc555x.h,
	mpc55xx/include/fsl-mpc556x.h, mpc55xx/include/fsl-mpc567x.h,
	mpc55xx/include/regs-edma.h, mpc55xx/include/regs-mmu.h: New files.
	* Makefile.am, M preinstall.am: Reflect changes above.
	* mpc55xx/dspi/dspi.c: Update due to API changes.
	* mpc55xx/include/edma.h, mpc55xx/edma/edma.c: Rework to support
	multiple eDMA modules.  Removed complex error interrupt handling.
	* mpc55xx/include/esci.h, mpc55xx/esci/esci.c: Support interrupt mode
	and printk().  Use configure options.
	* mpc55xx/include/irq.h: More defines.  API changes.
	* mpc55xx/include/mpc55xx.h: API changes.
	* mpc55xx/include/reg-defs.h: Added register defines.
	* mpc55xx/include/regs.h: Use new register header files.
	* mpc55xx/include/siu.h: Fixed includes.
	* mpc55xx/misc/fmpll.S, mpc55xx/misc/copy.S, mpc55xx/misc/flash.S:
	Changed sections.  API changes. Support MPC5674F.
This commit is contained in:
Sebastian Huber
2011-08-31 15:50:30 +00:00
parent b2aa729698
commit 97fa2f1b1e
22 changed files with 20168 additions and 5042 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
c/src/lib/libcpu/powerpc/ChangeLog
View File

@@ -1,3 +1,22 @@
2011-08-31 Sebastian Huber <sebastian.huber@embedded-brains.de>
* mpc55xx/include/fsl-mpc551x.h, mpc55xx/include/fsl-mpc555x.h,
mpc55xx/include/fsl-mpc556x.h, mpc55xx/include/fsl-mpc567x.h,
mpc55xx/include/regs-edma.h, mpc55xx/include/regs-mmu.h: New files.
* Makefile.am, M preinstall.am: Reflect changes above.
* mpc55xx/dspi/dspi.c: Update due to API changes.
* mpc55xx/include/edma.h, mpc55xx/edma/edma.c: Rework to support
multiple eDMA modules. Removed complex error interrupt handling.
* mpc55xx/include/esci.h, mpc55xx/esci/esci.c: Support interrupt mode
and printk(). Use configure options.
* mpc55xx/include/irq.h: More defines. API changes.
* mpc55xx/include/mpc55xx.h: API changes.
* mpc55xx/include/reg-defs.h: Added register defines.
* mpc55xx/include/regs.h: Use new register header files.
* mpc55xx/include/siu.h: Fixed includes.
* mpc55xx/misc/fmpll.S, mpc55xx/misc/copy.S, mpc55xx/misc/flash.S:
Changed sections. API changes. Support MPC5674F.
2011-08-31 Sebastian Huber <sebastian.huber@embedded-brains.de>
* new-exceptions/bspsupport/ppc_exc_categories.c,

26
c/src/lib/libcpu/powerpc/Makefile.am
View File

@@ -411,15 +411,23 @@ if mpc55xx
# Includes
include_mpc55xxdir = $(includedir)/mpc55xx
include_mpc55xx_HEADERS = mpc55xx/include/regs.h \
mpc55xx/include/reg-defs.h \
mpc55xx/include/dspi.h \
mpc55xx/include/edma.h \
mpc55xx/include/emios.h \
mpc55xx/include/mpc55xx.h \
mpc55xx/include/esci.h \
mpc55xx/include/siu.h \
mpc55xx/include/watchdog.h
include_mpc55xx_HEADERS =
include_mpc55xx_HEADERS += mpc55xx/include/regs.h
include_mpc55xx_HEADERS += mpc55xx/include/reg-defs.h
include_mpc55xx_HEADERS += mpc55xx/include/dspi.h
include_mpc55xx_HEADERS += mpc55xx/include/edma.h
include_mpc55xx_HEADERS += mpc55xx/include/emios.h
include_mpc55xx_HEADERS += mpc55xx/include/mpc55xx.h
include_mpc55xx_HEADERS += mpc55xx/include/esci.h
include_mpc55xx_HEADERS += mpc55xx/include/siu.h
include_mpc55xx_HEADERS += mpc55xx/include/irq.h
include_mpc55xx_HEADERS += mpc55xx/include/watchdog.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc551x.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc555x.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc556x.h
include_mpc55xx_HEADERS += mpc55xx/include/fsl-mpc567x.h
include_mpc55xx_HEADERS += mpc55xx/include/regs-edma.h
include_mpc55xx_HEADERS += mpc55xx/include/regs-mmu.h
include_bsp_HEADERS += mpc55xx/include/irq.h

8
c/src/lib/libcpu/powerpc/mpc55xx/dspi/dspi.c
View File

@@ -22,6 +22,8 @@
#include <mpc55xx/dspi.h>
#include <mpc55xx/mpc55xx.h>
#include <bsp/irq.h>
#include <libcpu/powerpc-utility.h>
#define RTEMS_STATUS_CHECKS_USE_PRINTK
@@ -172,7 +174,7 @@ static rtems_status_code mpc55xx_dspi_init( rtems_libi2c_bus_t *bus)
);
RTEMS_CHECK_SC( sc, "create receive update semaphore");
sc = mpc55xx_edma_obtain_channel( &e->edma_receive);
sc = mpc55xx_edma_obtain_channel( &e->edma_receive, MPC55XX_INTC_DEFAULT_PRIORITY);
RTEMS_CHECK_SC( sc, "obtain receive eDMA channel");
/* eDMA transmit */
@@ -185,10 +187,10 @@ static rtems_status_code mpc55xx_dspi_init( rtems_libi2c_bus_t *bus)
);
RTEMS_CHECK_SC( sc, "create transmit update semaphore");
sc = mpc55xx_edma_obtain_channel( &e->edma_transmit);
sc = mpc55xx_edma_obtain_channel( &e->edma_transmit, MPC55XX_INTC_DEFAULT_PRIORITY);
RTEMS_CHECK_SC( sc, "obtain transmit eDMA channel");
sc = mpc55xx_edma_obtain_channel( &e->edma_push);
sc = mpc55xx_edma_obtain_channel( &e->edma_push, MPC55XX_INTC_DEFAULT_PRIORITY);
RTEMS_CHECK_SC( sc, "obtain push eDMA channel");
tcd_push.SADDR = mpc55xx_dspi_push_data_address( e);

454
c/src/lib/libcpu/powerpc/mpc55xx/edma/edma.c
View File

@@ -22,258 +22,288 @@
#include <mpc55xx/edma.h>
#include <mpc55xx/mpc55xx.h>
#include <assert.h>
#include <string.h>
#include <bsp/irq.h>
#define RTEMS_STATUS_CHECKS_USE_PRINTK
#if MPC55XX_CHIP_TYPE / 10 == 551
#define EDMA_CHANNEL_COUNT 16U
#elif MPC55XX_CHIP_TYPE / 10 == 567
#define EDMA_CHANNEL_COUNT 96U
#else
#define EDMA_CHANNEL_COUNT 64U
#endif
#include <rtems/status-checks.h>
#define EDMA_CHANNELS_PER_GROUP 32U
#if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
#define MPC55XX_EDMA_CHANNEL_COUNT 16U
#else /* ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517)) */
#define MPC55XX_EDMA_CHANNEL_COUNT 64U
#endif /* ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517)) */
#define EDMA_CHANNELS_PER_MODULE 64U
#define MPC55XX_EDMA_INVALID_CHANNEL MPC55XX_EDMA_CHANNEL_COUNT
#define EDMA_GROUP_COUNT ((EDMA_CHANNEL_COUNT + 31U) / 32U)
#define MPC55XX_EDMA_IS_CHANNEL_INVALID( i) ((unsigned) (i) >= MPC55XX_EDMA_CHANNEL_COUNT)
#define EDMA_MODULE_COUNT ((EDMA_CHANNEL_COUNT + 63U) / 64U)
#define MPC55XX_EDMA_IS_CHANNEL_VALID( i) ((unsigned) (i) < MPC55XX_EDMA_CHANNEL_COUNT)
#define EDMA_INVALID_CHANNEL EDMA_CHANNEL_COUNT
#define MPC55XX_EDMA_IRQ_PRIORITY MPC55XX_INTC_DEFAULT_PRIORITY
#define EDMA_IS_CHANNEL_INVALID(i) ((unsigned) (i) >= EDMA_CHANNEL_COUNT)
#define MPC55XX_EDMA_CHANNEL_FLAG( channel) ((uint64_t) 1 << (channel))
#define EDMA_IS_CHANNEL_VALID(i) ((unsigned) (i) < EDMA_CHANNEL_COUNT)
static uint64_t mpc55xx_edma_channel_occupation = 0;
#define EDMA_GROUP_INDEX(channel) ((channel) / EDMA_CHANNELS_PER_GROUP)
static rtems_chain_control mpc55xx_edma_channel_chain;
#define EDMA_GROUP_BIT(channel) (1U << ((channel) % EDMA_CHANNELS_PER_GROUP))
static void mpc55xx_edma_interrupt_handler( void *arg)
#define EDMA_MODULE_INDEX(channel) ((channel) / EDMA_CHANNELS_PER_MODULE)
#define EDMA_MODULE_BIT(channel) (1U << ((channel) % EDMA_CHANNELS_PER_MODULE))
static uint32_t edma_channel_occupation [EDMA_GROUP_COUNT];
static RTEMS_CHAIN_DEFINE_EMPTY(edma_channel_chain);
volatile struct EDMA_tag *edma_get_regs_by_channel(unsigned channel)
{
mpc55xx_edma_channel_entry *e = (mpc55xx_edma_channel_entry *) arg;
#ifdef DEBUG
uint32_t citer = EDMA.TCD [e->channel].CITERE_LINK ? EDMA.TCD [e->channel].CITER & EDMA_TCD_BITER_LINKED_MASK : EDMA.TCD [e->channel].CITER;
RTEMS_DEBUG_PRINT( "channel %i (CITER = %i)\n", e->channel, citer);
#endif /* DEBUG */
/* Clear interrupt */
EDMA.CIRQR.R = (uint8_t) e->channel;
/* Notify user */
e->done( e, 0);
#if EDMA_MODULE_COUNT == 1
return &EDMA;
#elif EDMA_MODULE_COUNT == 2
return channel < EDMA_CHANNELS_PER_MODULE ? &EDMA_A : &EDMA_B;
#else
#error "unsupported module count"
#endif
}
static void mpc55xx_edma_interrupt_error_handler( void *arg)
volatile struct EDMA_tag *edma_get_regs_by_module(unsigned module)
{
rtems_chain_control *chain = &mpc55xx_edma_channel_chain;
rtems_chain_node *node = rtems_chain_first( chain );
unsigned i = 0;
uint64_t error_status = EDMA.ESR.R;
uint64_t error_channels = ((uint64_t) EDMA.ERH.R << 32) | EDMA.ERL.R;
uint64_t error_channels_update = 0;
RTEMS_DEBUG_PRINT( "error channels: %08x %08x\n", (unsigned) (error_channels >> 32), (unsigned) error_channels);
/* Mark all channels that are linked to a channel with errors */
do {
error_channels_update = 0;
for (i = 0; i < MPC55XX_EDMA_CHANNEL_COUNT; ++i) {
uint64_t channel_flags = 0;
unsigned minor_link = i;
unsigned major_link = i;
/* Check if we have linked channels */
if (EDMA.TCD [i].BMF.B.BITERE_LINK) {
minor_link = EDMA_TCD_BITER_LINK( i);
}
if (EDMA.TCD [i].BMF.B.MAJORE_LINK) {
major_link = EDMA.TCD [i].BMF.B.MAJORLINKCH;
}
/* Set flags related to this channel */
channel_flags = MPC55XX_EDMA_CHANNEL_FLAG( i) | MPC55XX_EDMA_CHANNEL_FLAG( minor_link) | MPC55XX_EDMA_CHANNEL_FLAG( major_link);
/* Any errors in these channels? */
if ( error_channels & channel_flags ) {
/* Get new error channels */
uint64_t update = (error_channels & channel_flags) ^ channel_flags;
/* Update error channels */
error_channels |= channel_flags;
/* Contribute to the update of this round */
error_channels_update |= update;
}
}
} while (error_channels_update != 0);
RTEMS_DEBUG_PRINT( "error channels (all): %08x %08x\n", (unsigned) (error_channels >> 32), (unsigned) error_channels);
/* Process the channels related to errors */
while (!rtems_chain_is_tail( chain, node)) {
mpc55xx_edma_channel_entry *e = (mpc55xx_edma_channel_entry *) node;
if ( error_channels & MPC55XX_EDMA_CHANNEL_FLAG( e->channel)) {
mpc55xx_edma_enable_hardware_requests( e->channel, false);
/* Notify user */
e->done( e, error_status);
}
node = node->next;
}
/* Clear the error interrupt requests */
for (i = 0; i < MPC55XX_EDMA_CHANNEL_COUNT; ++i) {
if ( error_channels & MPC55XX_EDMA_CHANNEL_FLAG( i)) {
EDMA.CER.R = (uint8_t) i;
}
}
#if EDMA_MODULE_COUNT == 1
return &EDMA;
#elif EDMA_MODULE_COUNT == 2
return module == 0 ? &EDMA_A : &EDMA_B;
#else
#error "unsupported module count"
#endif
}
void mpc55xx_edma_enable_hardware_requests( unsigned channel, bool enable)
static uint32_t edma_bit_array_set(unsigned channel, uint32_t *bit_array)
{
if (MPC55XX_EDMA_IS_CHANNEL_VALID( channel)) {
if (enable) {
EDMA.SERQR.R = (uint8_t) channel;
} else {
EDMA.CERQR.R = (uint8_t) channel;
}
} else {
RTEMS_SYSLOG_ERROR( "invalid channel number\n");
}
unsigned array = channel / 32;
uint32_t bit = 1U << (channel % 32);
uint32_t previous = bit_array [array];
bit_array [array] = previous | bit;
return previous;
}
void mpc55xx_edma_enable_error_interrupts( unsigned channel, bool enable)
static uint32_t edma_bit_array_clear(unsigned channel, uint32_t *bit_array)
{
if (MPC55XX_EDMA_IS_CHANNEL_VALID( channel)) {
if (enable) {
EDMA.SEEIR.R = (uint8_t) channel;
} else {
EDMA.CEEIR.R = (uint8_t) channel;
}
} else {
RTEMS_SYSLOG_ERROR( "invalid channel number\n");
}
unsigned array = channel / 32;
uint32_t bit = 1U << (channel % 32);
uint32_t previous = bit_array [array];
bit_array [array] = previous & ~bit;
return previous;
}
rtems_status_code mpc55xx_edma_init(void)
static void edma_interrupt_handler(void *arg)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
mpc55xx_edma_channel_entry *e = arg;
unsigned channel = e->channel;
volatile struct EDMA_tag *edma = edma_get_regs_by_channel(channel);
/* Initialize channel chain */
rtems_chain_initialize_empty( &mpc55xx_edma_channel_chain);
edma->CIRQR.R = (uint8_t) channel;
/* Arbitration mode: round robin */
EDMA.CR.B.ERCA = 1;
EDMA.CR.B.ERGA = 1;
/* Clear TCDs */
memset( (void *)&EDMA.TCD [0], 0,
MPC55XX_EDMA_CHANNEL_COUNT * sizeof( EDMA.TCD[0]));
/* Error interrupt handlers */
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EDMA_ERROR_LOW,
"eDMA Error (Low)",
RTEMS_INTERRUPT_UNIQUE,
MPC55XX_EDMA_IRQ_PRIORITY,
mpc55xx_edma_interrupt_error_handler,
NULL
);
RTEMS_CHECK_SC( sc, "install low error interrupt handler");
#if defined(MPC55XX_IRQ_EDMA_ERROR_HIGH)
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EDMA_ERROR_HIGH,
"eDMA Error (High)",
RTEMS_INTERRUPT_UNIQUE,
MPC55XX_EDMA_IRQ_PRIORITY,
mpc55xx_edma_interrupt_error_handler,
NULL
);
RTEMS_CHECK_SC( sc, "install high error interrupt handler");
#endif /* defined(MPC55XX_IRQ_EDMA_ERROR_HIGH) */
return RTEMS_SUCCESSFUL;
e->done(e, 0);
}
rtems_status_code mpc55xx_edma_obtain_channel( mpc55xx_edma_channel_entry *e)
static void edma_interrupt_error_handler(void *arg)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_interrupt_level level;
uint64_t channel_occupation = 0;
rtems_chain_control *chain = &edma_channel_chain;
rtems_chain_node *node = rtems_chain_first(chain);
uint32_t error_channels [] = {
#if EDMA_GROUP_COUNT >= 1
EDMA.ERL.R
#endif
#if EDMA_GROUP_COUNT >= 2
, EDMA.ERH.R
#endif
#if EDMA_GROUP_COUNT >= 3
, EDMA_B.ERL.R
#endif
};
uint32_t error_status [] = {
#if EDMA_GROUP_COUNT >= 1
EDMA.ESR.R
#endif
#if EDMA_GROUP_COUNT >= 3
, EDMA_B.ESR.R
#endif
};
if (MPC55XX_EDMA_IS_CHANNEL_INVALID( e->channel)) {
return RTEMS_INVALID_NUMBER;
}
#if EDMA_GROUP_COUNT >= 1
EDMA.ERL.R = error_channels [0];
#endif
#if EDMA_GROUP_COUNT >= 2
EDMA.ERH.R = error_channels [1];
#endif
#if EDMA_GROUP_COUNT >= 3
EDMA_B.ERL.R = error_channels [2];
#endif
/* Test and set channel occupation flag */
rtems_interrupt_disable( level);
channel_occupation = mpc55xx_edma_channel_occupation;
if ( (channel_occupation & MPC55XX_EDMA_CHANNEL_FLAG( e->channel)) == 0 ) {
mpc55xx_edma_channel_occupation = channel_occupation | MPC55XX_EDMA_CHANNEL_FLAG( e->channel);
}
rtems_interrupt_enable( level);
while (!rtems_chain_is_tail(chain, node)) {
mpc55xx_edma_channel_entry *e = (mpc55xx_edma_channel_entry *) node;
unsigned channel = e->channel;
unsigned group_index = EDMA_GROUP_INDEX(channel);
unsigned group_bit = EDMA_GROUP_BIT(channel);
/* Check channel occupation flag */
if ( channel_occupation & MPC55XX_EDMA_CHANNEL_FLAG( e->channel)) {
return RTEMS_RESOURCE_IN_USE;
}
if ((error_channels [group_index] & group_bit) != 0) {
unsigned module_index = EDMA_MODULE_INDEX(channel);
/* Interrupt handler */
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EDMA_GET_REQUEST( e->channel),
"eDMA Channel",
RTEMS_INTERRUPT_SHARED,
MPC55XX_EDMA_IRQ_PRIORITY,
mpc55xx_edma_interrupt_handler,
e
);
RTEMS_CHECK_SC( sc, "install channel interrupt handler");
e->done(e, error_status [module_index]);
}
/* Enable error interrupts */
mpc55xx_edma_enable_error_interrupts( e->channel, true);
/* Prepend channel entry to channel list */
rtems_chain_prepend( &mpc55xx_edma_channel_chain, &e->node);
return RTEMS_SUCCESSFUL;
node = rtems_chain_next(node);
}
}
rtems_status_code mpc55xx_edma_release_channel( mpc55xx_edma_channel_entry *e)
void mpc55xx_edma_enable_hardware_requests(unsigned channel, bool enable)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_interrupt_level level;
volatile struct EDMA_tag *edma = edma_get_regs_by_channel(channel);
/* Clear channel occupation flag */
rtems_interrupt_disable( level);
mpc55xx_edma_channel_occupation &= ~MPC55XX_EDMA_CHANNEL_FLAG( e->channel);
rtems_interrupt_enable( level);
assert(EDMA_IS_CHANNEL_VALID(channel));
/* Disable hardware requests */
mpc55xx_edma_enable_hardware_requests( e->channel, false);
/* Disable error interrupts */
mpc55xx_edma_enable_error_interrupts( e->channel, false);
/* Extract channel entry from channel chain */
rtems_chain_extract( &e->node);
/* Remove interrupt handler */
sc = rtems_interrupt_handler_remove(
MPC55XX_IRQ_EDMA_GET_REQUEST( e->channel),
mpc55xx_edma_interrupt_handler,
e
);
RTEMS_CHECK_SC( sc, "remove channel interrupt handler");
/* Notify user */
e->done( e, 0);
return RTEMS_SUCCESSFUL;
if (enable) {
edma->SERQR.R = (uint8_t) channel;
} else {
edma->CERQR.R = (uint8_t) channel;
}
}
void mpc55xx_edma_enable_error_interrupts(unsigned channel, bool enable)
{
volatile struct EDMA_tag *edma = edma_get_regs_by_channel(channel);
assert(EDMA_IS_CHANNEL_VALID(channel));
if (enable) {
edma->SEEIR.R = (uint8_t) channel;
} else {
edma->CEEIR.R = (uint8_t) channel;
}
}
void mpc55xx_edma_init(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
unsigned channel_remaining = EDMA_CHANNEL_COUNT;
unsigned module = 0;
unsigned group = 0;
for (module = 0; module < EDMA_MODULE_COUNT; ++module) {
volatile struct EDMA_tag *edma = edma_get_regs_by_module(module);
unsigned channel_count = channel_remaining < EDMA_CHANNELS_PER_MODULE ?
channel_remaining : EDMA_CHANNELS_PER_MODULE;
unsigned channel = 0;
channel_remaining -= channel_count;
/* Arbitration mode: group round robin, channel fixed */
edma->CR.B.ERGA = 1;
edma->CR.B.ERCA = 0;
for (channel = 0; channel < channel_count; ++channel) {
edma->CPR [channel].R = 0x80U | (channel & 0xfU);
}
/* Clear TCDs */
memset((void *) &edma->TCD [0], 0, channel_count * sizeof(edma->TCD [0]));
}
for (group = 0; group < EDMA_GROUP_COUNT; ++group) {
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EDMA_ERROR(group),
"eDMA Error",
RTEMS_INTERRUPT_UNIQUE,
MPC55XX_INTC_DEFAULT_PRIORITY,
edma_interrupt_error_handler,
NULL
);
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
rtems_fatal_error_occurred(0xdeadbeef);
}
}
}
rtems_status_code mpc55xx_edma_obtain_channel(
mpc55xx_edma_channel_entry *e,
unsigned irq_priority
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_interrupt_level level;
unsigned channel = e->channel;
uint32_t channel_occupation = 0;
if (EDMA_IS_CHANNEL_INVALID(channel)) {
return RTEMS_INVALID_ID;
}
rtems_interrupt_disable(level);
channel_occupation = edma_bit_array_set(
channel,
&edma_channel_occupation [0]
);
rtems_interrupt_enable(level);
if ((channel_occupation & EDMA_GROUP_BIT(channel))) {
return RTEMS_RESOURCE_IN_USE;
}
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EDMA(channel),
"eDMA Channel",
RTEMS_INTERRUPT_SHARED,
irq_priority,
edma_interrupt_handler,
e
);
if (sc != RTEMS_SUCCESSFUL) {
rtems_interrupt_disable(level);
edma_bit_array_clear(channel, &edma_channel_occupation [0]);
rtems_interrupt_enable(level);
return RTEMS_IO_ERROR;
}
rtems_chain_prepend(&edma_channel_chain, &e->node);
mpc55xx_edma_enable_error_interrupts(channel, true);
return RTEMS_SUCCESSFUL;
}
void mpc55xx_edma_release_channel(mpc55xx_edma_channel_entry *e)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_interrupt_level level;
unsigned channel = e->channel;
rtems_interrupt_disable(level);
edma_bit_array_clear(channel, &edma_channel_occupation [0]);
rtems_interrupt_enable(level);
mpc55xx_edma_enable_hardware_requests(channel, false);
mpc55xx_edma_enable_error_interrupts(channel, false);
rtems_chain_extract(&e->node);
sc = rtems_interrupt_handler_remove(
MPC55XX_IRQ_EDMA(e->channel),
edma_interrupt_handler,
e
);
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
rtems_fatal_error_occurred(0xdeadbeef);
}
e->done(e, 0);
}

211
c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c
View File

@@ -7,15 +7,19 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
/* Include order is important */
@@ -23,6 +27,7 @@
#include <mpc55xx/esci.h>
#include <bsp/irq.h>
#include <assert.h>
#include <unistd.h>
#include <termios.h>
@@ -31,9 +36,7 @@
#include <rtems/console.h>
#include <rtems/bspIo.h>
#define RTEMS_STATUS_CHECKS_USE_PRINTK
#include <rtems/status-checks.h>
#include <bspopts.h>
/* Evil define conflicts */
#define TERMIOS_CR1 CR1
@@ -45,27 +48,23 @@
#define MPC55XX_ESCI_IS_MINOR_INVALD(minor) ((minor) < 0 || (minor) >= MPC55XX_ESCI_NUMBER)
#define MPC55XX_ESCI_USE_INTERRUPTS(e) (!(e)->console && (e)->use_interrupts)
/**
* @brief eSCI driver table.
*/
mpc55xx_esci_driver_entry mpc55xx_esci_driver_table [MPC55XX_ESCI_NUMBER] = { {
.regs = &ESCI_A,
.device_name = "/dev/tty1",
.device_name = "/dev/ttyS0",
.use_termios = 1,
.use_interrupts = 0,
.console = 1,
.use_interrupts = MPC55XX_ESCI_USE_INTERRUPTS,
.tty = NULL,
.irq_number = 146
.irq_number = MPC55XX_IRQ_ESCI(0)
}, {
.regs = &ESCI_B,
.device_name = "/dev/tty2",
.device_name = "/dev/ttyS1",
.use_termios = 1,
.use_interrupts = 0,
.console = 0,
.use_interrupts = MPC55XX_ESCI_USE_INTERRUPTS,
.tty = NULL,
.irq_number = 149
.irq_number = MPC55XX_IRQ_ESCI(1)
}
};
@@ -104,40 +103,51 @@ static inline uint8_t mpc55xx_esci_read_char( mpc55xx_esci_driver_entry *e)
return data->B.D;
}
/**
* @brief Writes the character @a c to the transmit register.
*
* @note Waits for the transmit data register empty flag.
*/
static inline void mpc55xx_esci_write_char( mpc55xx_esci_driver_entry *e, uint8_t c)
static inline void mpc55xx_esci_write_char(mpc55xx_esci_driver_entry *e, char c)
{
volatile union ESCI_SR_tag *status = &e->regs->SR;
volatile union ESCI_DR_tag *data = &e->regs->DR;
union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS;
static const union ESCI_SR_tag clear_tdre = { .B = { .TDRE = 1 } };
volatile struct ESCI_tag *esci = e->regs;
rtems_interrupt_level level;
bool done = false;
/* Set clear flag */
sr.B.TDRE = 1;
rtems_interrupt_disable(level);
if (e->transmit_nest_level == 0) {
union ESCI_CR1_tag cr1 = { .R = esci->CR1.R };
while (true) {
rtems_interrupt_disable( level);
if (status->B.TDRE != 0) {
/* Clear flag */
status->R = sr.R;
/* Write */
data->B.D = c;
/* Done */
rtems_interrupt_enable( level);
break;
if (cr1.B.TIE != 0) {
cr1.B.TIE = 0;
e->transmit_nest_level = 1;
esci->CR1.R = cr1.R;
}
rtems_interrupt_enable( level);
} else {
++e->transmit_nest_level;
}
rtems_interrupt_enable(level);
while (status->B.TDRE == 0) {
/* Wait */
while (!done) {
rtems_interrupt_disable(level);
bool tx = e->transmit_in_progress;
if (!tx || (tx && esci->SR.B.TDRE)) {
esci->SR.R = clear_tdre.R;
esci->DR.B.D = c;
e->transmit_in_progress = true;
done = true;
}
rtems_interrupt_enable(level);
}
rtems_interrupt_disable(level);
if (e->transmit_nest_level > 0) {
--e->transmit_nest_level;
if (e->transmit_nest_level == 0) {
union ESCI_CR1_tag cr1 = { .R = esci->CR1.R };
cr1.B.TIE = 1;
esci->CR1.R = cr1.R;
}
}
rtems_interrupt_enable(level);
}
static inline void mpc55xx_esci_interrupts_enable( mpc55xx_esci_driver_entry *e)
@@ -186,21 +196,21 @@ static int mpc55xx_esci_termios_first_open( int major, int minor, void *arg)
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
/* Connect TTY */
e->tty = tty;
/* Enable interrupts */
if (MPC55XX_ESCI_USE_INTERRUPTS( e)) {
if (e->use_interrupts) {
mpc55xx_esci_interrupts_enable( e);
}
rv = rtems_termios_set_initial_baud( e->tty, 115200);
RTEMS_CHECK_RV_SC( rv, "Set initial baud");
assert(rv == 0);
return RTEMS_SUCCESSFUL;
return 0;
}
/**
@@ -214,7 +224,7 @@ static int mpc55xx_esci_termios_last_close( int major, int minor, void* arg)
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
/* Disable interrupts */
@@ -255,7 +265,7 @@ static int mpc55xx_esci_termios_poll_read( int minor)
*
* @return Returns number of chars sent on success or -1 otherwise.
*/
static int mpc55xx_esci_termios_poll_write( int minor, const char *out,
static int mpc55xx_esci_termios_poll_write( int minor, const char *out,
size_t n)
{
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
@@ -285,9 +295,12 @@ static int mpc55xx_esci_termios_poll_write( int minor, const char *out,
static int mpc55xx_esci_termios_write( int minor, const char *out, size_t n)
{
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [minor];
rtems_interrupt_level level;
/* Write */
rtems_interrupt_disable(level);
e->regs->DR.B.D = out [0];
e->transmit_in_progress = true;
rtems_interrupt_enable(level);
return 0;
}
@@ -310,14 +323,14 @@ static int mpc55xx_esci_termios_set_attributes( int minor, const struct termios
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
/* Enable module */
cr2.B.MDIS = 0;
/* Interrupts */
if (MPC55XX_ESCI_USE_INTERRUPTS( e) && e->tty != NULL) {
if (e->use_interrupts && e->tty != NULL) {
cr1.B.RIE = 1;
cr1.B.TIE = 1;
} else {
@@ -418,6 +431,7 @@ static void mpc55xx_esci_termios_interrupt_handler( void *arg)
volatile union ESCI_DR_tag *data = &e->regs->DR;
union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS;
union ESCI_SR_tag active = MPC55XX_ZERO_FLAGS;
rtems_interrupt_level level;
/* Status */
sr.R = status->R;
@@ -433,7 +447,10 @@ static void mpc55xx_esci_termios_interrupt_handler( void *arg)
}
/* Clear flags */
rtems_interrupt_disable(level);
status->R = active.R;
e->transmit_in_progress = false;
rtems_interrupt_enable(level);
/* Enqueue */
if (active.B.RDRF != 0) {
@@ -485,7 +502,6 @@ static const rtems_termios_callbacks mpc55xx_esci_termios_callbacks_polled = {
rtems_device_driver console_initialize( rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
int console_done = 0;
int termios_do_init = 1;
rtems_device_minor_number i = 0;
mpc55xx_esci_driver_entry *e = NULL;
@@ -493,17 +509,15 @@ rtems_device_driver console_initialize( rtems_device_major_number major, rtems_d
for (i = 0; i < MPC55XX_ESCI_NUMBER; ++i) {
e = &mpc55xx_esci_driver_table [i];
sc = rtems_io_register_name ( e->device_name, major, i);
RTEMS_CHECK_SC( sc, "Register IO device");
if (e->console) {
if (console_done) {
RTEMS_SYSLOG_WARNING( "Multiple console ports defined\n");
} else {
console_done = 1;
if (e->use_interrupts) {
RTEMS_SYSLOG_WARNING( "Cannot use interrupts for console port\n");
}
sc = rtems_io_register_name( CONSOLE_DEVICE_NAME, major, i);
RTEMS_CHECK_SC( sc, "Register IO device");
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
rtems_fatal_error_occurred(0xdeadbeef);
}
if (i == MPC55XX_ESCI_CONSOLE_MINOR) {
sc = rtems_io_register_name( CONSOLE_DEVICE_NAME, major, i);
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
rtems_fatal_error_occurred(0xdeadbeef);
}
}
if (e->use_termios && termios_do_init) {
@@ -511,7 +525,7 @@ rtems_device_driver console_initialize( rtems_device_major_number major, rtems_d
termios_do_init = 0;
rtems_termios_initialize();
}
if (MPC55XX_ESCI_USE_INTERRUPTS( e)) {
if (e->use_interrupts) {
sc = mpc55xx_interrupt_handler_install(
e->irq_number,
"eSCI",
@@ -520,7 +534,10 @@ rtems_device_driver console_initialize( rtems_device_major_number major, rtems_d
mpc55xx_esci_termios_interrupt_handler,
e
);
RTEMS_CHECK_SC( sc, "Install IRQ handler");
if (sc != RTEMS_SUCCESSFUL) {
/* FIXME */
rtems_fatal_error_occurred(0xdeadbeef);
}
}
}
mpc55xx_esci_termios_set_attributes( (int) i, &mpc55xx_esci_termios_default);
@@ -536,19 +553,18 @@ rtems_device_driver console_open( rtems_device_major_number major, rtems_device_
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
if (e->use_termios) {
if (MPC55XX_ESCI_USE_INTERRUPTS( e)) {
if (e->use_interrupts) {
sc = rtems_termios_open( major, minor, arg, &mpc55xx_esci_termios_callbacks);
} else {
sc = rtems_termios_open( major, minor, arg, &mpc55xx_esci_termios_callbacks_polled);
}
RTEMS_CHECK_SC( sc, "Open");
}
return RTEMS_SUCCESSFUL;
return sc;
}
rtems_device_driver console_close( rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
@@ -557,7 +573,7 @@ rtems_device_driver console_close( rtems_device_major_number major, rtems_device
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
if (e->use_termios) {
@@ -573,7 +589,7 @@ rtems_device_driver console_read( rtems_device_major_number major, rtems_device_
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
if (e->use_termios) {
@@ -597,7 +613,7 @@ rtems_device_driver console_write( rtems_device_major_number major, rtems_device
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
if (e->use_termios) {
@@ -606,10 +622,10 @@ rtems_device_driver console_write( rtems_device_major_number major, rtems_device
rtems_libio_rw_args_t *rw = (rtems_libio_rw_args_t *) arg;
uint32_t i = 0;
while (i < rw->count) {
mpc55xx_esci_write_char( e, rw->buffer [i]);
if (rw->buffer [i] == '\n') {
mpc55xx_esci_write_char( e, '\r');
}
mpc55xx_esci_write_char( e, rw->buffer [i]);
++i;
}
rw->bytes_moved = i;
@@ -624,7 +640,7 @@ rtems_device_driver console_control( rtems_device_major_number major, rtems_devi
/* Check minor number */
if (MPC55XX_ESCI_IS_MINOR_INVALD( minor)) {
return RTEMS_INVALID_NUMBER;
return RTEMS_INVALID_ID;
}
if (e->use_termios) {
@@ -636,13 +652,6 @@ rtems_device_driver console_control( rtems_device_major_number major, rtems_devi
/** @} */
/**
* @brief Port number for the BSP character output function.
*
* The correct value will be set by mpc55xx_esci_output_char_init().
*/
static int mpc55xx_esci_output_char_minor = 0;
/**
* @name BSP Character Output
* @{
@@ -650,41 +659,21 @@ static int mpc55xx_esci_output_char_minor = 0;
static void mpc55xx_esci_output_char( char c)
{
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [mpc55xx_esci_output_char_minor];
mpc55xx_esci_driver_entry *e = &mpc55xx_esci_driver_table [MPC55XX_ESCI_CONSOLE_MINOR];
mpc55xx_esci_interrupts_disable( e);
mpc55xx_esci_write_char( e, c);
if (c == '\n') {
mpc55xx_esci_write_char( e, '\r');
}
mpc55xx_esci_write_char( e, c);
mpc55xx_esci_interrupts_enable( e);
}
static void mpc55xx_esci_output_char_nop( char c)
{
/* Do nothing */
}
static void mpc55xx_esci_output_char_init( char c)
{
bool console_found = false;
int i = 0;
for (i = 0; i < MPC55XX_ESCI_NUMBER; ++i) {
if (mpc55xx_esci_driver_table [i].console) {
console_found = true;
mpc55xx_esci_output_char_minor = i;
break;
}
}
if (console_found) {
BSP_output_char = mpc55xx_esci_output_char;
mpc55xx_esci_termios_set_attributes( mpc55xx_esci_output_char_minor, &mpc55xx_esci_termios_default);
mpc55xx_esci_output_char( c);
} else {
BSP_output_char = mpc55xx_esci_output_char_nop;
}
mpc55xx_esci_termios_set_attributes( MPC55XX_ESCI_CONSOLE_MINOR, &mpc55xx_esci_termios_default);
mpc55xx_esci_output_char( c);
BSP_output_char = mpc55xx_esci_output_char;
}
/** @} */

14
c/src/lib/libcpu/powerpc/mpc55xx/include/edma.h
View File

@@ -32,17 +32,17 @@ extern "C" {
#endif /* __cplusplus */
typedef struct mpc55xx_edma_channel_entry {
rtems_chain_node node;
unsigned channel;
void (*done)( struct mpc55xx_edma_channel_entry *, uint32_t);
rtems_id id;
rtems_chain_node node;
unsigned channel;
void (*done)( struct mpc55xx_edma_channel_entry *, uint32_t);
rtems_id id;
} mpc55xx_edma_channel_entry;
rtems_status_code mpc55xx_edma_init();
void mpc55xx_edma_init(void);
rtems_status_code mpc55xx_edma_obtain_channel( mpc55xx_edma_channel_entry *e);
rtems_status_code mpc55xx_edma_obtain_channel( mpc55xx_edma_channel_entry *e, unsigned irq_priority);
rtems_status_code mpc55xx_edma_release_channel( mpc55xx_edma_channel_entry *e);
void mpc55xx_edma_release_channel( mpc55xx_edma_channel_entry *e);
void mpc55xx_edma_enable_hardware_requests( unsigned channel, bool enable);

14
c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h
View File

@@ -27,6 +27,7 @@
#ifndef LIBCPU_POWERPC_MPC55XX_ESCI_H
#define LIBCPU_POWERPC_MPC55XX_ESCI_H
#include <rtems.h>
#include <rtems/termiostypes.h>
#ifdef __cplusplus
@@ -35,16 +36,15 @@ extern "C" {
#define MPC55XX_ESCI_NUMBER 2
struct ESCI_tag;
typedef struct {
volatile struct ESCI_tag *regs;
const char *device_name;
int use_termios;
int use_interrupts;
int console;
struct rtems_termios_tty *tty;
unsigned irq_number;
const char *device_name;
rtems_vector_number irq_number;
int transmit_nest_level;
bool transmit_in_progress;
bool use_termios;
bool use_interrupts;
} mpc55xx_esci_driver_entry;
extern mpc55xx_esci_driver_entry mpc55xx_esci_driver_table [ /* MPC55XX_ESCI_NUMBER */ ];

4002
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc551x.h Normal file
View File

File diff suppressed because it is too large Load Diff

3380
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc555x.h Normal file
View File

File diff suppressed because it is too large Load Diff

4560
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc556x.h Normal file
View File

File diff suppressed because it is too large Load Diff

6623
c/src/lib/libcpu/powerpc/mpc55xx/include/fsl-mpc567x.h Normal file
View File

File diff suppressed because it is too large Load Diff

246
c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h
View File

@@ -34,13 +34,8 @@ extern "C" {
* Interrupt numbers
*/
/* Basics */
#define MPC55XX_IRQ_INVALID 0x10000U
#define MPC55XX_IRQ_MIN 0U
#define MPC55XX_IRQ_MAX 328U
#define MPC55XX_IRQ_MIN 0U
#define MPC55XX_IRQ_MAX 328U
#define MPC55XX_IRQ_BASE MPC55XX_IRQ_MIN
#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
/* Software interrupts */
#define MPC55XX_IRQ_SOFTWARE_MIN 0U
@@ -49,19 +44,18 @@ extern "C" {
#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
#if MPC55XX_CHIP_TYPE >= 5510 && MPC55XX_CHIP_TYPE <= 5517
/* eDMA interrupts */
#define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 26U
#if MPC55XX_CHIP_TYPE / 10 == 551
#define MPC55XX_IRQ_MAX 293U
#define MPC55XX_IRQ_EDMA_GET_CHANNEL(v) \
((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
#define MPC55XX_IRQ_EDMA_GET_REQUEST(c) \
((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
/* eDMA */
#define MPC55XX_IRQ_EDMA_ERROR(group) \
((group) == 0 ? 10U : MPC55XX_IRQ_INVALID)
#define MPC55XX_IRQ_EDMA(ch) \
((unsigned) (ch) < 16U ? 11U + (ch) : MPC55XX_IRQ_INVALID)
/* I2C interrupt */
#define MPC55XX_IRQ_I2C 48U
/* I2C */
#define MPC55XX_IRQ_I2C(mod) \
((mod) == 0 ? 48U : MPC55XX_IRQ_INVALID)
/* SIU external interrupts */
#define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
@@ -70,31 +64,74 @@ extern "C" {
#define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
#define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
/* eMIOS interrupts */
#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 58U
#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 81U
#define MPC55XX_IRQ_EMIOS_GET_CHANNEL(v) \
((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
#define MPC55XX_IRQ_EMIOS_GET_REQUEST(c) \
((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
#elif MPC55XX_CHIP_TYPE >= 5554 && MPC55XX_CHIP_TYPE <= 5567
/* eDMA interrupts */
#define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
#define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 42U
/* PIT */
#define MPC55XX_IRQ_RTI 148U
#define MPC55XX_IRQ_PIT(timer) (148U + (timer))
#define MPC55XX_IRQ_EDMA_ERROR_HIGH 210U
#define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN 211U
#define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MAX 242U
/* eTPU */
#define MPC55XX_IRQ_ETPU_BASE(mod) MPC55XX_IRQ_INVALID
#define MPC55XX_IRQ_EDMA_GET_CHANNEL(v) \
(((v) > MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX) \
? ((v) + 32U - MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
: ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
#define MPC55XX_IRQ_EDMA_GET_REQUEST(c) \
(((c) >= 32U) \
? ((c) - 32U + MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
: ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
/* DSPI */
#define MPC55XX_IRQ_DSPI_BASE(mod) \
((mod) == 0 ? 117U : \
((mod) == 1 ? 122U : \
((mod) == 2 ? 274U : \
((mod) == 3 ? 279U : MPC55XX_IRQ_INVALID))))
/* eMIOS */
#define MPC55XX_IRQ_EMIOS(ch) \
((unsigned) (ch) < 24U ? 58U + (ch) : MPC55XX_IRQ_INVALID)
/* eQADC */
#define MPC55XX_IRQ_EQADC_BASE(mod) \
((mod) == 0 ? 82U : MPC55XX_IRQ_INVALID)
/* eSCI */
#define MPC55XX_IRQ_ESCI_BASE(mod) \
((mod) == 0 ? 113U : \
((mod) == 1 ? 114U : \
((mod) == 2 ? 115U : \
((mod) == 3 ? 116U : \
((mod) == 4 ? 270U : \
((mod) == 5 ? 271U : \
((mod) == 6 ? 272U : \
((mod) == 7 ? 273U : MPC55XX_IRQ_INVALID))))))))
/* FlexCAN */
#define MPC55XX_IRQ_CAN_BASE(mod) \
((mod) == 0 ? 127U : \
((mod) == 1 ? 157U : \
((mod) == 2 ? 178U : \
((mod) == 3 ? 199U : \
((mod) == 4 ? 220U : \
((mod) == 5 ? 241U : MPC55XX_IRQ_INVALID))))))
/* FlexRay */
#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
((mod) == 0 ? 284U : MPC55XX_IRQ_INVALID)
#else
#if MPC55XX_CHIP_TYPE / 10 == 555
#define MPC55XX_IRQ_MAX 307U
#elif MPC55XX_CHIP_TYPE / 10 == 556
#define MPC55XX_IRQ_MAX 360U
#elif MPC55XX_CHIP_TYPE / 10 == 567
#define MPC55XX_IRQ_MAX 479U
#else
#error "unsupported chip type"
#endif
/* eDMA */
#define MPC55XX_IRQ_EDMA_ERROR(group) \
((group) == 0 ? 10U : \
((group) == 1 ? 210U : \
((group) == 2 ? 425U : MPC55XX_IRQ_INVALID)))
#define MPC55XX_IRQ_EDMA(ch) \
((unsigned) (ch) < 32U ? 11U + (ch) : \
((unsigned) (ch) < 64U ? 179U + (ch) : \
((unsigned) (ch) < 96U ? 362U + (ch) : MPC55XX_IRQ_INVALID)))
/* I2C */
#define MPC55XX_IRQ_I2C(mod) MPC55XX_IRQ_INVALID
/* SIU external interrupts */
#define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
@@ -103,25 +140,116 @@ extern "C" {
#define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
#define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
/* eMIOS interrupts */
#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 51U
#define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 66U
#define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN 202U
#define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MAX 209U
/* PIT */
#define MPC55XX_IRQ_RTI 305U
#define MPC55XX_IRQ_PIT(ch) (301U + (ch))
#define MPC55XX_IRQ_EMIOS_GET_CHANNEL(v) \
(((v) > MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX) \
? ((v) + 16U - MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
: ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
/* eTPU */
#define MPC55XX_IRQ_ETPU_BASE(mod) \
((mod) == 0 ? 67U : \
((mod) == 1 ? 243U : MPC55XX_IRQ_INVALID))
#define MPC55XX_IRQ_EMIOS_GET_REQUEST(c) \
(((c) >= 16U) \
? ((c) - 16U + MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
: ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
#else
#error "unexpected chip type"
/* DSPI */
#define MPC55XX_IRQ_DSPI_BASE(mod) \
((mod) == 0 ? 275U : \
((mod) == 1 ? 131U : \
((mod) == 2 ? 136U : \
((mod) == 3 ? 141U : MPC55XX_IRQ_INVALID))))
/* eMIOS */
#define MPC55XX_IRQ_EMIOS(ch) \
((unsigned) (ch) < 16U ? 51U + (ch) : \
((unsigned) (ch) < 24U ? 186U + (ch) : \
((unsigned) (ch) < 32U ? 435U + (ch) : MPC55XX_IRQ_INVALID)))
/* eQADC */
#define MPC55XX_IRQ_EQADC_BASE(mod) \
((mod) == 0 ? 100U : \
((mod) == 1 ? 394U : MPC55XX_IRQ_INVALID))
/* eSCI */
#define MPC55XX_IRQ_ESCI_BASE(mod) \
((mod) == 0 ? 146U : \
((mod) == 1 ? 149U : \
((mod) == 2 ? 473U : MPC55XX_IRQ_INVALID)))
/* FlexCAN */
#define MPC55XX_IRQ_CAN_BASE(mod) \
((mod) == 0 ? 152U : \
((mod) == 1 ? 280U : \
((mod) == 2 ? 173U : \
((mod) == 3 ? 308U : \
((mod) == 4 ? 329U : MPC55XX_IRQ_INVALID)))))
/* FlexRay */
#define MPC55XX_IRQ_FLEXRAY_BASE(mod) \
((mod) == 0 ? 350U : MPC55XX_IRQ_INVALID)
#endif
#define MPC55XX_IRQ_NUMBER (MPC55XX_IRQ_MAX + 1U)
/* eTPU */
#define MPC55XX_IRQ_ETPU(mod) \
(MPC55XX_IRQ_ETPU_BASE(mod) + 0U)
#define MPC55XX_IRQ_ETPU_CHANNEL(mod, ch) \
(MPC55XX_IRQ_ETPU_BASE(mod) + 1U + (ch))
/* DSPI */
#define MPC55XX_IRQ_DSPI_TFUF_RFOF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 0U)
#define MPC55XX_IRQ_DSPI_EOQF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 1U)
#define MPC55XX_IRQ_DSPI_TFFF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 2U)
#define MPC55XX_IRQ_DSPI_TCF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 3U)
#define MPC55XX_IRQ_DSPI_RFDF(mod) (MPC55XX_IRQ_DSPI_BASE(mod) + 4U)
/* eQADC */
#define MPC55XX_IRQ_EQADC_TORF_RFOF_CFUF(mod) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 0U)
#define MPC55XX_IRQ_EQADC_NCF(mod, fifo) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 0U)
#define MPC55XX_IRQ_EQADC_PF(mod, fifo) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 1U)
#define MPC55XX_IRQ_EQADC_EOQF(mod, fifo) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 2U)
#define MPC55XX_IRQ_EQADC_CFFF(mod, fifo) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 3U)
#define MPC55XX_IRQ_EQADC_RFDF(mod, fifo) \
(MPC55XX_IRQ_EQADC_BASE(mod) + 1U + (fifo) * 5U + 4U)
/* eSCI */
#define MPC55XX_IRQ_ESCI(mod) (MPC55XX_IRQ_ESCI_BASE(mod) + 0U)
/* FlexCAN */
#define MPC55XX_IRQ_CAN_BOFF_TWRN_RWRN(mod) (MPC55XX_IRQ_CAN(mod) + 0U)
#define MPC55XX_IRQ_CAN_ERR(mod) (MPC55XX_IRQ_CAN(mod) + 1U)
#define MPC55XX_IRQ_CAN_BUF_0(mod) (MPC55XX_IRQ_CAN(mod) + 3U)
#define MPC55XX_IRQ_CAN_BUF_1(mod) (MPC55XX_IRQ_CAN(mod) + 4U)
#define MPC55XX_IRQ_CAN_BUF_2(mod) (MPC55XX_IRQ_CAN(mod) + 5U)
#define MPC55XX_IRQ_CAN_BUF_3(mod) (MPC55XX_IRQ_CAN(mod) + 6U)
#define MPC55XX_IRQ_CAN_BUF_4(mod) (MPC55XX_IRQ_CAN(mod) + 7U)
#define MPC55XX_IRQ_CAN_BUF_5(mod) (MPC55XX_IRQ_CAN(mod) + 8U)
#define MPC55XX_IRQ_CAN_BUF_6(mod) (MPC55XX_IRQ_CAN(mod) + 9U)
#define MPC55XX_IRQ_CAN_BUF_7(mod) (MPC55XX_IRQ_CAN(mod) + 10U)
#define MPC55XX_IRQ_CAN_BUF_8(mod) (MPC55XX_IRQ_CAN(mod) + 12U)
#define MPC55XX_IRQ_CAN_BUF_9(mod) (MPC55XX_IRQ_CAN(mod) + 12U)
#define MPC55XX_IRQ_CAN_BUF_10(mod) (MPC55XX_IRQ_CAN(mod) + 13U)
#define MPC55XX_IRQ_CAN_BUF_11(mod) (MPC55XX_IRQ_CAN(mod) + 14U)
#define MPC55XX_IRQ_CAN_BUF_12(mod) (MPC55XX_IRQ_CAN(mod) + 15U)
#define MPC55XX_IRQ_CAN_BUF_13(mod) (MPC55XX_IRQ_CAN(mod) + 16U)
#define MPC55XX_IRQ_CAN_BUF_14(mod) (MPC55XX_IRQ_CAN(mod) + 17U)
#define MPC55XX_IRQ_CAN_BUF_15(mod) (MPC55XX_IRQ_CAN(mod) + 18U)
#define MPC55XX_IRQ_CAN_BUF_16_31(mod) (MPC55XX_IRQ_CAN(mod) + 19U)
#define MPC55XX_IRQ_CAN_BUF_32_63(mod) (MPC55XX_IRQ_CAN(mod) + 20U)
/* FlexRay */
#define MPC55XX_IRQ_FLEXRAY_MIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 0U)
#define MPC55XX_IRQ_FLEXRAY_PRIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 1U)
#define MPC55XX_IRQ_FLEXRAY_CHIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 2U)
#define MPC55XX_IRQ_FLEXRAY_WUP_IF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 3U)
#define MPC55XX_IRQ_FLEXRAY_FBNE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 4U)
#define MPC55XX_IRQ_FLEXRAY_FANE_F(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 5U)
#define MPC55XX_IRQ_FLEXRAY_RBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 6U)
#define MPC55XX_IRQ_FLEXRAY_TBIF(mod) (MPC55XX_IRQ_FLEXRAY_BASE(mod) + 7U)
/* Checks */
#define MPC55XX_IRQ_IS_VALID(v) \
((v) >= MPC55XX_IRQ_MIN && \
@@ -171,9 +299,9 @@ rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
* @{
*/
#define BSP_INTERRUPT_VECTOR_MIN 0
#define BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN
#define BSP_INTERRUPT_VECTOR_MAX 328
#define BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX
#define BSP_INTERRUPT_USE_INDEX_TABLE
@@ -186,6 +314,10 @@ rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
/** @} */
/* Legacy API */
#define MPC55XX_IRQ_EDMA_GET_REQUEST(ch) MPC55XX_IRQ_EDMA(ch)
#define MPC55XX_IRQ_EMIOS_GET_REQUEST(ch) MPC55XX_IRQ_EMIOS(ch)
#ifdef __cplusplus
};
#endif /* __cplusplus */

38
c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h
View File

@@ -7,15 +7,19 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
/**
@@ -43,23 +47,11 @@
#include <stddef.h>
#include <stdint.h>
/* Defined in copy.S */
int mpc55xx_copy_8( const void *src, void *dest, size_t n);
/* Defined in fmpll.S */
int mpc55xx_get_system_clock(void);
/* Defined in fmpll.S */
void mpc55xx_fmpll_reset_config();
/* Defined in fmpll.S */
void mpc55xx_fmpll_wait_for_lock();
/* Defined in fmpll.S */
int mpc55xx_get_system_clock();
/* Defined in fmpll.S */
void mpc55xx_system_reset();
/* Defined in flash.S */
void mpc55xx_flash_config();
void mpc55xx_system_reset(void);
int mpc55xx_flash_copy(void *dest, const void *src, size_t nbytes);
int mpc55xx_flash_copy_op(void *rdest, const void *src, size_t nbytes,

23
c/src/lib/libcpu/powerpc/mpc55xx/include/reg-defs.h
View File

@@ -7,15 +7,19 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
@@ -47,9 +51,12 @@
#define FMPLL_SYNCR 0xC3F80000
#define FMPLL_SYNSR 0xC3F80004
#define FMPLL_ESYNCR1 0XC3F80008
#define FMPLL_ESYNCR2 0XC3F8000C
#define FLASH_BIUCR 0xC3F8801C
#define SIU_ECCR 0xC3F90984
#define SIU_SRCR 0xC3F90010
#define SIU_SYSDIV 0xC3F909A0
#endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
/*

693
c/src/lib/libcpu/powerpc/mpc55xx/include/regs-edma.h Normal file
View File

@@ -0,0 +1,693 @@
/**
* @file
*
* @ingroup mpc55xx
*/
/*
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
/*********************************************************************
*
* Copyright:
* Freescale Semiconductor, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Freescale
* Semiconductor, Inc. This software is provided on an "AS IS"
* basis and without warranty.
*
* To the maximum extent permitted by applicable law, Freescale
* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
* AND ANY ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Freescale Semiconductor assumes no responsibility for the
* maintenance and support of this software
*
********************************************************************/
#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H
#include <stdint.h>
#include <bspopts.h>
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************************/
/* MODULE : eDMA */
/****************************************************************************/
struct EDMA_tag {
union {
uint32_t R;
struct {
#if MPC55XX_CHIP_TYPE / 10 == 567
uint32_t:14;
uint32_t CX:1;
uint32_t ECX:1;
#else
uint32_t:16;
#endif
uint32_t GRP3PRI:2;
uint32_t GRP2PRI:2;
uint32_t GRP1PRI:2;
uint32_t GRP0PRI:2;
#if MPC55XX_CHIP_TYPE / 10 == 567
uint32_t EMLM:1;
uint32_t CLM:1;
uint32_t HALT:1;
uint32_t HOE:1;
#else
uint32_t:4;
#endif
uint32_t ERGA:1;
uint32_t ERCA:1;
uint32_t EDBG:1;
uint32_t EBW:1;
} B;
} CR; /* Control Register */
union {
uint32_t R;
struct {
uint32_t VLD:1;
#if MPC55XX_CHIP_TYPE / 10 == 567
uint32_t:14;
uint32_t ECX:1;
#else
uint32_t:15;
#endif
uint32_t GPE:1;
uint32_t CPE:1;
uint32_t ERRCHN:6;
uint32_t SAE:1;
uint32_t SOE:1;
uint32_t DAE:1;
uint32_t DOE:1;
uint32_t NCE:1;
uint32_t SGE:1;
uint32_t SBE:1;
uint32_t DBE:1;
} B;
} ESR; /* Error Status Register */
union {
uint32_t R;
struct {
uint32_t ERQ63:1;
uint32_t ERQ62:1;
uint32_t ERQ61:1;
uint32_t ERQ60:1;
uint32_t ERQ59:1;
uint32_t ERQ58:1;
uint32_t ERQ57:1;
uint32_t ERQ56:1;
uint32_t ERQ55:1;
uint32_t ERQ54:1;
uint32_t ERQ53:1;
uint32_t ERQ52:1;
uint32_t ERQ51:1;
uint32_t ERQ50:1;
uint32_t ERQ49:1;
uint32_t ERQ48:1;
uint32_t ERQ47:1;
uint32_t ERQ46:1;
uint32_t ERQ45:1;
uint32_t ERQ44:1;
uint32_t ERQ43:1;
uint32_t ERQ42:1;
uint32_t ERQ41:1;
uint32_t ERQ40:1;
uint32_t ERQ39:1;
uint32_t ERQ38:1;
uint32_t ERQ37:1;
uint32_t ERQ36:1;
uint32_t ERQ35:1;
uint32_t ERQ34:1;
uint32_t ERQ33:1;
uint32_t ERQ32:1;
} B;
} ERQRH; /* DMA Enable Request Register High */
union {
uint32_t R;
struct {
uint32_t ERQ31:1;
uint32_t ERQ30:1;
uint32_t ERQ29:1;
uint32_t ERQ28:1;
uint32_t ERQ27:1;
uint32_t ERQ26:1;
uint32_t ERQ25:1;
uint32_t ERQ24:1;
uint32_t ERQ23:1;
uint32_t ERQ22:1;
uint32_t ERQ21:1;
uint32_t ERQ20:1;
uint32_t ERQ19:1;
uint32_t ERQ18:1;
uint32_t ERQ17:1;
uint32_t ERQ16:1;
uint32_t ERQ15:1;
uint32_t ERQ14:1;
uint32_t ERQ13:1;
uint32_t ERQ12:1;
uint32_t ERQ11:1;
uint32_t ERQ10:1;
uint32_t ERQ09:1;
uint32_t ERQ08:1;
uint32_t ERQ07:1;
uint32_t ERQ06:1;
uint32_t ERQ05:1;
uint32_t ERQ04:1;
uint32_t ERQ03:1;
uint32_t ERQ02:1;
uint32_t ERQ01:1;
uint32_t ERQ00:1;
} B;
} ERQRL; /* DMA Enable Request Register Low */
union {
uint32_t R;
struct {
uint32_t EEI63:1;
uint32_t EEI62:1;
uint32_t EEI61:1;
uint32_t EEI60:1;
uint32_t EEI59:1;
uint32_t EEI58:1;
uint32_t EEI57:1;
uint32_t EEI56:1;
uint32_t EEI55:1;
uint32_t EEI54:1;
uint32_t EEI53:1;
uint32_t EEI52:1;
uint32_t EEI51:1;
uint32_t EEI50:1;
uint32_t EEI49:1;
uint32_t EEI48:1;
uint32_t EEI47:1;
uint32_t EEI46:1;
uint32_t EEI45:1;
uint32_t EEI44:1;
uint32_t EEI43:1;
uint32_t EEI42:1;
uint32_t EEI41:1;
uint32_t EEI40:1;
uint32_t EEI39:1;
uint32_t EEI38:1;
uint32_t EEI37:1;
uint32_t EEI36:1;
uint32_t EEI35:1;
uint32_t EEI34:1;
uint32_t EEI33:1;
uint32_t EEI32:1;
} B;
} EEIRH; /* DMA Enable Error Interrupt Register High */
union {
uint32_t R;
struct {
uint32_t EEI31:1;
uint32_t EEI30:1;
uint32_t EEI29:1;
uint32_t EEI28:1;
uint32_t EEI27:1;
uint32_t EEI26:1;
uint32_t EEI25:1;
uint32_t EEI24:1;
uint32_t EEI23:1;
uint32_t EEI22:1;
uint32_t EEI21:1;
uint32_t EEI20:1;
uint32_t EEI19:1;
uint32_t EEI18:1;
uint32_t EEI17:1;
uint32_t EEI16:1;
uint32_t EEI15:1;
uint32_t EEI14:1;
uint32_t EEI13:1;
uint32_t EEI12:1;
uint32_t EEI11:1;
uint32_t EEI10:1;
uint32_t EEI09:1;
uint32_t EEI08:1;
uint32_t EEI07:1;
uint32_t EEI06:1;
uint32_t EEI05:1;
uint32_t EEI04:1;
uint32_t EEI03:1;
uint32_t EEI02:1;
uint32_t EEI01:1;
uint32_t EEI00:1;
} B;
} EEIRL; /* DMA Enable Error Interrupt Register Low */
union { /* DMA Set Enable Request Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t SERQ:7;
} B;
} SERQR;
union { /* DMA Clear Enable Request Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t CERQ:7;
} B;
} CERQR;
union { /* DMA Set Enable Error Interrupt Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t SEEI:7;
} B;
} SEEIR;
union { /* DMA Clear Enable Error Interrupt Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t CEEI:7;
} B;
} CEEIR;
union { /* DMA Clear Interrupt Request Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t CINT:7;
} B;
} CIRQR;
union { /* DMA Clear error Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t CERR:7;
} B;
} CER;
union { /* Set Start Bit Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t SSB:7;
} B;
} SSBR;
union { /* Clear Done Status Bit Register */
uint8_t R;
struct {
uint8_t NOP:1;
uint8_t CDSB:7;
} B;
} CDSBR;
union {
uint32_t R;
struct {
uint32_t INT63:1;
uint32_t INT62:1;
uint32_t INT61:1;
uint32_t INT60:1;
uint32_t INT59:1;
uint32_t INT58:1;
uint32_t INT57:1;
uint32_t INT56:1;
uint32_t INT55:1;
uint32_t INT54:1;
uint32_t INT53:1;
uint32_t INT52:1;
uint32_t INT51:1;
uint32_t INT50:1;
uint32_t INT49:1;
uint32_t INT48:1;
uint32_t INT47:1;
uint32_t INT46:1;
uint32_t INT45:1;
uint32_t INT44:1;
uint32_t INT43:1;
uint32_t INT42:1;
uint32_t INT41:1;
uint32_t INT40:1;
uint32_t INT39:1;
uint32_t INT38:1;
uint32_t INT37:1;
uint32_t INT36:1;
uint32_t INT35:1;
uint32_t INT34:1;
uint32_t INT33:1;
uint32_t INT32:1;
} B;
} IRQRH; /* DMA Interrupt Request High */
union {
uint32_t R;
struct {
uint32_t INT31:1;
uint32_t INT30:1;
uint32_t INT29:1;
uint32_t INT28:1;
uint32_t INT27:1;
uint32_t INT26:1;
uint32_t INT25:1;
uint32_t INT24:1;
uint32_t INT23:1;
uint32_t INT22:1;
uint32_t INT21:1;
uint32_t INT20:1;
uint32_t INT19:1;
uint32_t INT18:1;
uint32_t INT17:1;
uint32_t INT16:1;
uint32_t INT15:1;
uint32_t INT14:1;
uint32_t INT13:1;
uint32_t INT12:1;
uint32_t INT11:1;
uint32_t INT10:1;
uint32_t INT09:1;
uint32_t INT08:1;
uint32_t INT07:1;
uint32_t INT06:1;
uint32_t INT05:1;
uint32_t INT04:1;
uint32_t INT03:1;
uint32_t INT02:1;
uint32_t INT01:1;
uint32_t INT00:1;
} B;
} IRQRL; /* DMA Interrupt Request Low */
union {
uint32_t R;
struct {
uint32_t ERR63:1;
uint32_t ERR62:1;
uint32_t ERR61:1;
uint32_t ERR60:1;
uint32_t ERR59:1;
uint32_t ERR58:1;
uint32_t ERR57:1;
uint32_t ERR56:1;
uint32_t ERR55:1;
uint32_t ERR54:1;
uint32_t ERR53:1;
uint32_t ERR52:1;
uint32_t ERR51:1;
uint32_t ERR50:1;
uint32_t ERR49:1;
uint32_t ERR48:1;
uint32_t ERR47:1;
uint32_t ERR46:1;
uint32_t ERR45:1;
uint32_t ERR44:1;
uint32_t ERR43:1;
uint32_t ERR42:1;
uint32_t ERR41:1;
uint32_t ERR40:1;
uint32_t ERR39:1;
uint32_t ERR38:1;
uint32_t ERR37:1;
uint32_t ERR36:1;
uint32_t ERR35:1;
uint32_t ERR34:1;
uint32_t ERR33:1;
uint32_t ERR32:1;
} B;
} ERH; /* DMA Error High */
union {
uint32_t R;
struct {
uint32_t ERR31:1;
uint32_t ERR30:1;
uint32_t ERR29:1;
uint32_t ERR28:1;
uint32_t ERR27:1;
uint32_t ERR26:1;
uint32_t ERR25:1;
uint32_t ERR24:1;
uint32_t ERR23:1;
uint32_t ERR22:1;
uint32_t ERR21:1;
uint32_t ERR20:1;
uint32_t ERR19:1;
uint32_t ERR18:1;
uint32_t ERR17:1;
uint32_t ERR16:1;
uint32_t ERR15:1;
uint32_t ERR14:1;
uint32_t ERR13:1;
uint32_t ERR12:1;
uint32_t ERR11:1;
uint32_t ERR10:1;
uint32_t ERR09:1;
uint32_t ERR08:1;
uint32_t ERR07:1;
uint32_t ERR06:1;
uint32_t ERR05:1;
uint32_t ERR04:1;
uint32_t ERR03:1;
uint32_t ERR02:1;
uint32_t ERR01:1;
uint32_t ERR00:1;
} B;
} ERL; /* DMA Error Low */
#if MPC55XX_CHIP_TYPE / 10 == 567
union { /* hardware request status high */
uint32_t R;
struct {
uint32_t HRS63:1;
uint32_t HRS62:1;
uint32_t HRS61:1;
uint32_t HRS60:1;
uint32_t HRS59:1;
uint32_t HRS58:1;
uint32_t HRS57:1;
uint32_t HRS56:1;
uint32_t HRS55:1;
uint32_t HRS54:1;
uint32_t HRS53:1;
uint32_t HRS52:1;
uint32_t HRS51:1;
uint32_t HRS50:1;
uint32_t HRS49:1;
uint32_t HRS48:1;
uint32_t HRS47:1;
uint32_t HRS46:1;
uint32_t HRS45:1;
uint32_t HRS44:1;
uint32_t HRS43:1;
uint32_t HRS42:1;
uint32_t HRS41:1;
uint32_t HRS40:1;
uint32_t HRS39:1;
uint32_t HRS38:1;
uint32_t HRS37:1;
uint32_t HRS36:1;
uint32_t HRS35:1;
uint32_t HRS34:1;
uint32_t HRS33:1;
uint32_t HRS32:1;
} B;
} HRSH;
union { /* hardware request status low */
uint32_t R;
struct {
uint32_t HRS31:1;
uint32_t HRS30:1;
uint32_t HRS29:1;
uint32_t HRS28:1;
uint32_t HRS27:1;
uint32_t HRS26:1;
uint32_t HRS25:1;
uint32_t HRS24:1;
uint32_t HRS23:1;
uint32_t HRS22:1;
uint32_t HRS21:1;
uint32_t HRS20:1;
uint32_t HRS19:1;
uint32_t HRS18:1;
uint32_t HRS17:1;
uint32_t HRS16:1;
uint32_t HRS15:1;
uint32_t HRS14:1;
uint32_t HRS13:1;
uint32_t HRS12:1;
uint32_t HRS11:1;
uint32_t HRS10:1;
uint32_t HRS09:1;
uint32_t HRS08:1;
uint32_t HRS07:1;
uint32_t HRS06:1;
uint32_t HRS05:1;
uint32_t HRS04:1;
uint32_t HRS03:1;
uint32_t HRS02:1;
uint32_t HRS01:1;
uint32_t HRS00:1;
} B;
} HRSL;
uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
#else
uint32_t edma_reserved1[52];
#endif
union {
uint8_t R;
struct {
uint8_t ECP:1;
#if MPC55XX_CHIP_TYPE / 10 == 567
uint8_t DPA:1;
#else
uint8_t:1;
#endif
uint8_t GRPPRI:2;
uint8_t CHPRI:4;
} B;
} CPR[64];
uint32_t edma_reserved2[944];
/****************************************************************************/
/* DMA2 Transfer Control Descriptor */
/****************************************************************************/
struct tcd_t {
uint32_t SADDR; /* source address */
/* Source and destination fields */
union tcd_SDF_tag {
uint32_t R;
struct {
uint16_t SMOD:5; /* source address modulo */
uint16_t SSIZE:3; /* source transfer size */
uint16_t DMOD:5; /* destination address modulo */
uint16_t DSIZE:3; /* destination transfer size */
int16_t SOFF; /* signed source address offset */
} B;
} SDF;
uint32_t NBYTES; /* inner (“minor”) byte count */
int32_t SLAST; /* last destination address adjustment, or
scatter/gather address (if e_sg = 1) */
uint32_t DADDR; /* destination address */
/* CITER and destination fields */
union tcd_CDF_tag {
uint32_t R;
struct {
uint16_t CITERE_LINK:1;
uint16_t CITER:15;
int16_t DOFF; /* signed destination address offset */
} B;
struct {
uint16_t CITERE_LINK:1;
uint16_t CITERLINKCH:6;
uint16_t CITER:9;
int16_t DOFF;
} B_ALT;
} CDF;
int32_t DLAST_SGA;
/* BITER and misc fields */
union tcd_BMF_tag {
uint32_t R;
struct {
uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */
uint32_t BITER:15;
uint32_t BWC:2; /* bandwidth control */
uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */
uint32_t DONE:1; /* channel done */
uint32_t ACTIVE:1; /* channel active */
uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */
uint32_t E_SG:1; /* enable scatter/gather descriptor */
uint32_t D_REQ:1; /* disable ipd_req when done */
uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
uint32_t INT_MAJ:1; /* interrupt on major loop completion */
uint32_t START:1; /* explicit channel start */
} B;
struct {
uint32_t BITERE_LINK:1;
uint32_t BITERLINKCH:6;
uint32_t BITER:9;
uint32_t BWC:2;
uint32_t MAJORLINKCH:6;
uint32_t DONE:1;
uint32_t ACTIVE:1;
uint32_t MAJORE_LINK:1;
uint32_t E_SG:1;
uint32_t D_REQ:1;
uint32_t INT_HALF:1;
uint32_t INT_MAJ:1;
uint32_t START:1;
} B_ALT;
} BMF;
} TCD[64]; /* transfer_control_descriptor */
};
#ifndef __cplusplus
static const struct tcd_t EDMA_TCD_DEFAULT = {
.SADDR = 0,
.SDF = { .R = 0 },
.NBYTES = 0,
.SLAST = 0,
.DADDR = 0,
.CDF = { .R = 0 },
.DLAST_SGA = 0,
.BMF = { .R = 0 }
};
#endif /* __cplusplus */
#define EDMA_TCD_BITER_MASK 0x7fff
#define EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1)
#define EDMA_TCD_BITER_LINKED_MASK 0x1ff
#define EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1)
#define EDMA_TCD_LINK_AND_BITER(link, biter) \
(((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK))
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */

172
c/src/lib/libcpu/powerpc/mpc55xx/include/regs-mmu.h Normal file
View File

@@ -0,0 +1,172 @@
/**
* @file
*
* @ingroup mpc55xx
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
/*********************************************************************
*
* Copyright:
* Freescale Semiconductor, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Freescale
* Semiconductor, Inc. This software is provided on an "AS IS"
* basis and without warranty.
*
* To the maximum extent permitted by applicable law, Freescale
* Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
* REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
* AND ANY ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
* BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
* PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Freescale Semiconductor assumes no responsibility for the
* maintenance and support of this software
*
********************************************************************/
#ifndef LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
#define LIBCPU_POWERPC_MPC55XX_REGS_MMU_H
#include <stdint.h>
#include <bspopts.h>
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************************/
/* MMU */
/****************************************************************************/
struct MMU_tag {
union {
uint32_t R;
struct {
uint32_t : 2;
uint32_t TLBSEL : 2;
uint32_t : 7;
uint32_t ESEL : 5;
uint32_t : 11;
uint32_t NV : 5;
} B;
} MAS0;
union {
uint32_t R;
struct {
uint32_t VALID : 1;
uint32_t IPROT : 1;
uint32_t : 6;
uint32_t TID : 8;
uint32_t : 3;
uint32_t TS : 1;
uint32_t TSIZE : 5;
uint32_t : 7;
} B;
} MAS1;
union {
uint32_t R;
struct {
uint32_t EPN : 22;
uint32_t : 4;
uint32_t VLE : 1;
uint32_t W : 1;
uint32_t I : 1;
uint32_t M : 1;
uint32_t G : 1;
uint32_t E : 1;
} B;
} MAS2;
union {
uint32_t R;
struct {
uint32_t RPN : 22;
uint32_t U0 : 1;
uint32_t U1 : 1;
uint32_t U2 : 1;
uint32_t U3 : 1;
uint32_t UX : 1;
uint32_t SX : 1;
uint32_t UW : 1;
uint32_t SW : 1;
uint32_t UR : 1;
uint32_t SR : 1;
} B;
} MAS3;
};
union MMU_MAS4_tag {
uint32_t R;
struct {
uint32_t : 2;
uint32_t TLBSELD : 2;
uint32_t : 10;
uint32_t TIDSELD : 2;
uint32_t : 4;
uint32_t TSIZED : 4;
uint32_t : 3;
uint32_t WD : 1;
uint32_t ID : 1;
uint32_t MD : 1;
uint32_t GD : 1;
uint32_t ED : 1;
} B;
};
union MMU_MAS6_tag {
uint32_t R;
struct {
uint32_t : 8;
uint32_t SPID : 8;
uint32_t : 15;
uint32_t SAS : 1;
} B;
};
#define MPC55XX_MMU_TAG_INITIALIZER(idx, addr, size, x, w, r, io) \
{ \
.MAS0 = { .B = { .TLBSEL = 1, .ESEL = (idx) } }, \
.MAS1 = { .B = { \
.VALID = 1, .IPROT = 1, .TID = 0, .TS = 0, .TSIZE = (size) } \
}, \
.MAS2 = { .B = { \
.EPN = (addr) >> 10, .VLE = 0, .W = 0, .I = (io), .M = 0, .G = (io), .E = 0 } \
}, \
.MAS3 = { .B = { \
.RPN = (addr) >> 10, .U0 = 0, .U1 = 0, .U2 = 0, .U3 = 0, .UX = 0, \
.SX = (x), .UW = 0, .SW = (w), .UR = 0, .SR = (r) } \
} \
}
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBCPU_POWERPC_MPC55XX_REGS_MMU_H */

4577
c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h
View File

File diff suppressed because it is too large Load Diff

24
c/src/lib/libcpu/powerpc/mpc55xx/include/siu.h
View File

@@ -7,25 +7,25 @@
*/
/*
* Copyright (c) 2010
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBCPU_POWERPC_MPC55XX_SIU_H
#define LIBCPU_POWERPC_MPC55XX_SIU_H
#include <stdbool.h>
#include <stdint.h>
#include <rtems.h>
#include <rtems/chain.h>
#include <mpc55xx/regs.h>
#ifdef __cplusplus
extern "C" {

2
c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S
View File

@@ -21,7 +21,7 @@
#include <libcpu/powerpc-utility.h>
#include <bspopts.h>
.section ".text"
.section ".bsp_start_text", "ax"
/**
* @fn int mpc55xx_copy_8( const void *src, void *dest, size_t n)

33
c/src/lib/libcpu/powerpc/mpc55xx/misc/flash.S
View File

@@ -7,36 +7,41 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
.section ".text"
.section ".bsp_start_text", "ax"
/* Optimized flash configurations (Table 13-15 [MPC5567 Microcontroller Reference Manual]) */
.equ FLASH_SETTINGS_RESET, 0xff00
.equ FLASH_SETTINGS_82, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_1 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
.equ FLASH_SETTINGS_102, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_1 | FLASH_BUICR_RWSC_2 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
.equ FLASH_SETTINGS_132, FLASH_BUICR_CPU_PREFTCH | FLASH_BUICR_APC_2 | FLASH_BUICR_RWSC_3 | FLASH_BUICR_WWSC_1 | FLASH_BUICR_DPFEN_3 | FLASH_BUICR_IPFEN_3 | FLASH_BUICR_PFLIM_6 | FLASH_BUICR_BFEN
.equ FLASH_SETTINGS_264, 0x01716B15
/**
* @fn void mpc55xx_flash_config()
* @fn void mpc55xx_flash_init()
* @brief Optimized flash configuration.
* @warning Code will be copied and executed on the stack. The stack pointer
* will not be updated, since this function has to work before memory
* initialization.
*/
GLOBAL_FUNCTION mpc55xx_flash_config
GLOBAL_FUNCTION mpc55xx_flash_init
mflr r31
/* Flash settings dependent on system clock */
@@ -50,6 +55,9 @@ GLOBAL_FUNCTION mpc55xx_flash_config
LWI r4, 132000000
cmpw r3, r4
ble clock_132
LWI r4, 264000000
cmpw r3, r4
ble clock_264
LWI r30, FLASH_SETTINGS_RESET
b settings_done
clock_82:
@@ -61,6 +69,9 @@ clock_102:
clock_132:
LWI r30, FLASH_SETTINGS_132
b settings_done
clock_264:
LWI r30, FLASH_SETTINGS_264
b settings_done
settings_done:
/* Copy store code on the stack */

63
c/src/lib/libcpu/powerpc/mpc55xx/misc/fmpll.S
View File

@@ -7,22 +7,32 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
#include <bspopts.h>
#define FMPLL_IS_MPC551X (5510 <= MPC55XX_CHIP_TYPE && MPC55XX_CHIP_TYPE <= 5517)
#define FMPLL_IS_MPC5674 (MPC55XX_CHIP_TYPE == 5674)
#define FMPLL_HAS_ENHANCED_FMPLL (FMPLL_IS_MPC551X || FMPLL_IS_MPC5674)
.section ".text"
.section ".bsp_start_text", "ax"
/* Timeout for delay in clocks */
.equ FMPLL_TIMEOUT, 6000
@@ -31,20 +41,18 @@
lwz r5, \setting
stw r5, 0(r4)
msync
bl mpc55xx_fmpll_wait_for_lock
bl fmpll_wait_for_lock
.endm
/**
* @fn void mpc55xx_fmpll_reset_config()
* @fn void mpc55xx_fmpll_init()
* @brief Configure FMPLL after reset.
*
* Sets the system clock from 12 MHz in two steps up to 128 MHz.
*/
GLOBAL_FUNCTION mpc55xx_fmpll_reset_config
GLOBAL_FUNCTION mpc55xx_fmpll_init
/* Save link register */
mflr r9
#if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
#if FMPLL_HAS_ENHANCED_FMPLL
/*
* for MPC5510: pass in ptr to array with:
* off 0: temp setting for ESYNCR2
@@ -60,10 +68,11 @@ GLOBAL_FUNCTION mpc55xx_fmpll_reset_config
lwz r5, 8(r3)
stw r5, (FMPLL_ESYNCR1-FMPLL_ESYNCR2)(r4)
msync
bl mpc55xx_fmpll_wait_for_lock
bl fmpll_wait_for_lock
DO_SETTING 4(r3)
#if FMPLL_IS_MPC551X
/*
* switch to PLL clock in SIU
*/
@@ -74,7 +83,8 @@ GLOBAL_FUNCTION mpc55xx_fmpll_reset_config
LWI r6, SIU_SYSCLK_SYSCLKSEL_PLL
or r5, r5, r6
stw r5, 0(r4)
#else
#endif /* FMPLL_IS_MPC551X */
#else /* !FMPLL_HAS_ENHANCED_FMPLL */
/*
* for MPC5566: pass in ptr to array with:
* off 0: temp setting for SYNCR
@@ -95,19 +105,13 @@ GLOBAL_FUNCTION mpc55xx_fmpll_reset_config
LWI r6, ~FMPLL_SYNCR_LOCRE & ~FMPLL_SYNCR_LOLRE
and r5, r5, r6
stw r5, 0(r4)
#endif
#endif /* !FMPLL_HAS_ENHANCED_FMPLL */
/* Restore link register and return */
mtlr r9
blr
/**
* @fn void mpc55xx_fmpll_wait_for_lock()
* @brief Wait for FMPLL lock.
* @warning If the lock cannot be obtained within some clock cycles a software
* system reset will be initiated.
*/
GLOBAL_FUNCTION mpc55xx_fmpll_wait_for_lock
fmpll_wait_for_lock:
LWI r6, FMPLL_TIMEOUT
mtctr r6
@@ -126,12 +130,14 @@ fmpll_continue:
blr
.section ".text", "aw"
/**
* @fn int mpc55xx_get_system_clock()
* @brief Returns the system clock.
*/
GLOBAL_FUNCTION mpc55xx_get_system_clock
#if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
#if FMPLL_HAS_ENHANCED_FMPLL
LA r4, FMPLL_ESYNCR1
lwz r3, 0(r4)
/* EPREDIV */
@@ -152,8 +158,7 @@ GLOBAL_FUNCTION mpc55xx_get_system_clock
divw r3, r8, r5 /* REF_CLOCK/PREDIV */
mullw r3, r6, r3 /* REF_CLOCK/PREDIV*MFD */
divw r3, r3, r7 /* REF_CLOCK/PREDIV*MFD/RFD */
#else
#else /* !FMPLL_HAS_ENHANCED_FMPLL */
LA r4, FMPLL_SYNCR
lwz r3, 0(r4)
@@ -172,7 +177,7 @@ GLOBAL_FUNCTION mpc55xx_get_system_clock
mullw r6, r6, r8
sraw r6, r6, r7
divw r3, r6, r5
#endif
#endif /* !FMPLL_HAS_ENHANCED_FMPLL */
blr

28
c/src/lib/libcpu/powerpc/preinstall.am
View File

@@ -278,10 +278,38 @@ $(PROJECT_INCLUDE)/mpc55xx/siu.h: mpc55xx/include/siu.h $(PROJECT_INCLUDE)/mpc55
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/siu.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/siu.h
$(PROJECT_INCLUDE)/mpc55xx/irq.h: mpc55xx/include/irq.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/irq.h
$(PROJECT_INCLUDE)/mpc55xx/watchdog.h: mpc55xx/include/watchdog.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/watchdog.h
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h: mpc55xx/include/fsl-mpc551x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc551x.h
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h: mpc55xx/include/fsl-mpc555x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc555x.h
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h: mpc55xx/include/fsl-mpc556x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc556x.h
$(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h: mpc55xx/include/fsl-mpc567x.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/fsl-mpc567x.h
$(PROJECT_INCLUDE)/mpc55xx/regs-edma.h: mpc55xx/include/regs-edma.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/regs-edma.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/regs-edma.h
$(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h: mpc55xx/include/regs-mmu.h $(PROJECT_INCLUDE)/mpc55xx/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc55xx/regs-mmu.h
$(PROJECT_INCLUDE)/bsp/irq.h: mpc55xx/include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h