startup/bspstart.c: Clean up non-FPGA use of EPORT interrupts.

network/network.c: Track half/full-duplex changes from 4.7 branch.
This commit is contained in:
Eric Norum
2008-04-08 03:19:53 +00:00
parent eaa58dc9aa
commit 97979915c8
4 changed files with 68 additions and 22 deletions

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@@ -1,3 +1,11 @@
2008-04-07 Eric Norum <norume@aps.anl.gov>
* startup/bspstart.c: Clean up non-FPGA use of EPORT interrupts.
2008-04-07 Eric Norum <norume@aps.anl.gov>
* network/network.c: Track half/fullduplex changes from 4.7 branch.
2008-03-03 Joel Sherrill <joel.sherrill@OARcorp.com> 2008-03-03 Joel Sherrill <joel.sherrill@OARcorp.com>
* startup/linkcmds: Add wildcard to gcc_except_table section so * startup/linkcmds: Add wildcard to gcc_except_table section so

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@@ -85,7 +85,9 @@ port into RAM then executed or programmed into flash memory.
This forces the network link to half-duplex. If your network link is This forces the network link to half-duplex. If your network link is
locked at full duplex you'll have to find another port! locked at full duplex you'll have to find another port!
The RTEMS network driver can be forced to 100 Mbs/full-duplex by setting The RTEMS network driver can be forced to 100 Mbs/full-duplex by setting
the bootstrap environment variable IPADDR0_100FULL to Y. the bootstrap environment variable IPADDR0_100FULL to Y. The driver can
be forced to 10 Mbs/half-duplex by setting the bootstrap environment
variable IPADDR0_10HALF to Y.
4) Run 'tftp' on your host machine: 4) Run 'tftp' on your host machine:
tftp> binary tftp> binary

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@@ -118,7 +118,8 @@ struct mcf5282_enet_struct {
/* /*
* Link parameters * Link parameters
*/ */
int force100Full; enum { link_auto, link_100Full, link_10Half } link;
uint16_t mii_cr;
uint16_t mii_sr2; uint16_t mii_sr2;
}; };
static struct mcf5282_enet_struct enet_driver[NIFACES]; static struct mcf5282_enet_struct enet_driver[NIFACES];
@@ -280,9 +281,12 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
/* /*
* Set up Transmit Control Register: * Set up Transmit Control Register:
* Full duplex * Full or half duplex
* No heartbeat * No heartbeat
*/ */
if (sc->link == link_10Half)
MCF5282_FEC_TCR = 0;
else
MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN; MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
/* /*
@@ -307,17 +311,38 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
* LED1 receive status, LED2 link status, LEDs stretched * LED1 receive status, LED2 link status, LEDs stretched
* Advertise 100 Mb/s, full-duplex, IEEE-802.3 * Advertise 100 Mb/s, full-duplex, IEEE-802.3
* Turn off auto-negotiate * Turn off auto-negotiate
* Enable speed-change, duplex-change and link-status-change interrupts * Clear status
* Set 100/full and perhaps auto-negotiate
*/ */
setMII(1, 20, 0x24F2); setMII(1, 20, 0x24F2);
setMII(1, 4, 0x0181); setMII(1, 4, 0x0181);
setMII(1, 0, 0x2100); setMII(1, 0, 0x0);
rtems_task_wake_after(2); rtems_task_wake_after(2);
sc->mii_sr2 = getMII(1, 17); sc->mii_sr2 = getMII(1, 17);
switch (sc->link) {
case link_auto:
/*
* Enable speed-change, duplex-change and link-status-change interrupts
* Enable auto-negotiate (start at 100/FULL)
*/
setMII(1, 18, 0x0072); setMII(1, 18, 0x0072);
if (!sc->force100Full)
setMII(1, 0, 0x3100); setMII(1, 0, 0x3100);
break;
case link_10Half:
/*
* Force 10/HALF
*/
setMII(1, 0, 0x0);
break;
case link_100Full:
/*
* Force 100/FULL
*/
setMII(1, 0, 0x2100);
break;
}
sc->mii_cr = getMII(1, 0);
/* /*
* Set up receive buffer descriptors * Set up receive buffer descriptors
@@ -799,9 +824,23 @@ enet_stats(struct mcf5282_enet_struct *sc)
printf("LINK DOWN!\n"); printf("LINK DOWN!\n");
} }
else { else {
printf("Link speed %d Mb/s, %s-duplex.\n", int speed;
sc->mii_sr2 & 0x4000 ? 100 : 10, int full;
sc->mii_sr2 & 0x200 ? "full" : "half"); int fixed;
if (sc->mii_cr & 0x1000) {
fixed = 0;
speed = sc->mii_sr2 & 0x4000 ? 100 : 10;
full = sc->mii_sr2 & 0x200 ? 1 : 0;
}
else {
fixed = 1;
speed = sc->mii_cr & 0x2000 ? 100 : 10;
full = sc->mii_cr & 0x100 ? "full" : "half";
}
printf("Link %s %d Mb/s, %s-duplex.\n",
fixed ? "fixed" : "auto-negotiate",
speed,
full ? "full" : "half");
} }
printf(" EIR:%8.8lx ", MCF5282_FEC_EIR); printf(" EIR:%8.8lx ", MCF5282_FEC_EIR);
printf("EIMR:%8.8lx ", MCF5282_FEC_EIMR); printf("EIMR:%8.8lx ", MCF5282_FEC_EIMR);
@@ -967,7 +1006,12 @@ rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
*/ */
if (((env = bsp_getbenv("IPADDR0_100FULL")) != NULL) if (((env = bsp_getbenv("IPADDR0_100FULL")) != NULL)
&& ((*env == 'y') || (*env == 'Y'))) && ((*env == 'y') || (*env == 'Y')))
sc->force100Full = 1; sc->link = link_100Full;
else if (((env = bsp_getbenv("IPADDR0_10HALF")) != NULL)
&& ((*env == 'y') || (*env == 'Y')))
sc->link = link_10Half;
else
sc->link = link_auto;
/* /*
* Attach the interface * Attach the interface

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@@ -425,10 +425,6 @@ int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
*/ */
#define NVECTOR 256 #define NVECTOR 256
#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL
#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
#define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe)) #define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe))
static struct handlerTab { static struct handlerTab {
@@ -576,7 +572,9 @@ rtems_interrupt_level level;
for (p = 0 ; p < 8 ; p++) { for (p = 0 ; p < 8 ; p++) {
if ((source < 8) if ((source < 8)
|| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
if (source >= 8) if (source < 8)
MCF5282_EPORT_EPIER |= 1 << source;
else
*(&MCF5282_INTC0_ICR1 + (source - 1)) = *(&MCF5282_INTC0_ICR1 + (source - 1)) =
MCF5282_INTC_ICR_IL(l) | MCF5282_INTC_ICR_IL(l) |
MCF5282_INTC_ICR_IP(p); MCF5282_INTC_ICR_IP(p);
@@ -615,12 +613,6 @@ BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
rtems_interrupt_enable(level); rtems_interrupt_enable(level);
return 0; return 0;
} }
MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
MCF5282_EPORT_EPIER |= FPGA_EPIER;
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
MCF5282_INTC_IMRL_MASKALL);
setupDone = 1;
handlerTab[vector].func = NULL; handlerTab[vector].func = NULL;
handlerTab[vector].arg = NULL; handlerTab[vector].arg = NULL;
rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler); rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);