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2001-10-11 Alexandra Kossovsky <sasha@oktet.ru>

Browse Source 
* Makefile.am, README, bsp_specs, .cvsignore, include/Makefile.am,
	include/bsp.h, include/coverhd.h, include/sdram.h, include/.cvsignore,
	start/Makefile.am, start/start.S, start/.cvsignore, startup/Makefile.am,
	startup/bspstart.c, startup/linkcmds, startup/linkcmds.rom,
	startup/linkcmds.rom2ram, startup/.cvsignore, wrapup/Makefile.am,
	wrapup/.cvsignore, hw_init/Makefile.am, hw_init/hw_init.c,
	hw_init/.cvsignore, times, configure.ac:  New files.
	Reviewed and updated to latest automake and autoconf standards
	by Ralf Corsepius <corsepiu@faw.uni-ulm.de>.
This commit is contained in:
Joel Sherrill
2001-10-11 19:04:12 +00:00
parent 09eb8a2ee8
commit 96462044ce
29 changed files with 2197 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
c/src/lib/libbsp/sh/.cvsignore
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@@ -1,6 +1,7 @@
Makefile
Makefile.in
aclocal.m4
autom4te.cache
config.cache
config.guess
config.log

1
c/src/lib/libbsp/sh/gensh1/.cvsignore
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@@ -1,6 +1,7 @@
Makefile
Makefile.in
aclocal.m4
autom4te.cache
config.cache
config.guess
config.log

1
c/src/lib/libbsp/sh/gensh2/.cvsignore
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@@ -1,6 +1,7 @@
Makefile
Makefile.in
aclocal.m4
autom4te.cache
config.cache
config.guess
config.log

14
c/src/lib/libbsp/sh/gensh4/.cvsignore Normal file
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@@ -0,0 +1,14 @@
Makefile
Makefile.in
aclocal.m4
autom4te.cache
config.cache
config.guess
config.log
config.status
config.sub
configure
depcomp
install-sh
missing
mkinstalldirs

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c/src/lib/libbsp/sh/gensh4/Makefile.am Normal file
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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
## wrapup is the one that actually builds and installs the library
## from the individual .rel files built in other directories
SUBDIRS = include start startup hw_init wrapup
include $(top_srcdir)/../../bsp.am
EXTRA_DIST = bsp_specs times
include $(top_srcdir)/../../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../../automake/local.am

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c/src/lib/libbsp/sh/gensh4/README Normal file
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#
# $Id$
#
# Author: Alexandra Kossovsky <sasha@oktet.ru>
# Victor Vengerov <vvv@oktet.ru>
# OKTET Ltd, http://www.oktet.ru
#
BSP NAME: generic SH4 (gensh4)
BOARD: n/a
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7750
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb (sh-ipl-g+ loader/stub)
PERIPHERALS
===========
TIMERS: on-chip
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: n/a
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/console
STDIO
=====
PORT: /dev/console
ELECTRICAL: n/a
BAUD: n/a
BITS PER CHARACTER: n/a
PARITY: n/a
STOP BITS: n/a
NOTES
=====
(1) Driver for the on-chip serial devices is tested only with 1st serial
port. We cannot test it on serial port with FIFO.
Console driver has 4 modes -- 2 with termios (interrupt-driven &
poll-driven modes), one raw mode working with serial port directly,
without termios, and one mode working with gdb stub (using 'trapa'
handled by sh-ipl-g+).
(2) The present 'hw_init.c' file provides 'early_hw_init'(void) which
is normally called from 'start.S' to provide such minimal HW setup.
It is written in C, but it should be noted that any accesses to memory
(except hardware registers) are prohibited until hardware not
initialized. To avoid access to stack, hw_init.c should be compiled with
-fomit-frame-pointer.
hw_init.c also provides 'bsp_cache_on'(void) normally called from
'start.S' after copying all data from rom to ram.
(3) In 'make/custom/gensh4.cfg' you should properly set 'HZ=XXXX', which
is frequency fed to the CPU core (external clock frequency can be
multiplied by on-chip PLLs). Please note that it is not a frequency of
external oscillator! See Hardware Manual, section 10, for details.
Global variable 'SH4_CPU_HZ_Frequency' is declared in 'bsp.h' and
initilized in 'bspstart.c' to ${HZ}. It is used by console driver,
which exists in 'libcpu/sh/sh7750'.
(4) There is SH4_WITH_IPL macro in console driver 'sh4_uart.h'.
When it is defined, the application works under
gdb-stub (it is able to turn cache on by 'trapa', use gdb mode in console
driver and get out from gdb to use other console modes).
(5) There are 3 likcmds:
- linkcmds: code and data loaded to RAM. No code/data moving required.
- linkcmds.rom: code executed from the ROM; .data section moved to the
RAM on initialization.
- linkcmds.rom2ram: execution started from the ROM (after reset); code
and data moved to the RAM and execution continued from RAM.
The same 'start.S' is used for all cases.
(6) You can get gdb stub from http://www.oktet.ru/download/sh4/sh-ipl.tar.gz.
It is based on 'sh-ipl-g+' package used in sh-linux project.
(7) This project was done in cooperation with Transas company
http://www.transas.com

22
c/src/lib/libbsp/sh/gensh4/bsp_specs Normal file
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%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
*lib:
%{!qrtems: %(old_lib)} \
%{qrtems: --start-group %{!qrtems_debug: -lrtemsall } %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
*startfile:
%{!qrtems: %(old_startfile)} \
%{qrtems: %{qrtems_debug: start_g.o%s} %{!qrtems_debug: start.o%s}}
*link:
%(old_link) %{qrtems: -dc -dp -N -e _start}

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c/src/lib/libbsp/sh/gensh4/configure.ac Normal file
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dnl Process this file with autoconf to produce a configure script.
dnl
dnl $Id$
AC_PREREQ(2.52)
AC_INIT
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
AC_CONFIG_AUX_DIR(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE(rtems-c-src-lib-libbsp-sh-gensh4,$RTEMS_VERSION,no)
AM_MAINTAINER_MODE
RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
RTEMS_CANONICALIZE_TOOLS
RTEMS_ENV_RTEMSBSP
RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
RTEMS_CANONICAL_HOST
RTEMS_PROJECT_ROOT
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile
include/Makefile
start/Makefile
startup/Makefile
hw_init/Makefile
wrapup/Makefile
])
AC_OUTPUT

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c/src/lib/libbsp/sh/gensh4/hw_init/.cvsignore Normal file
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Makefile
Makefile.in

39
c/src/lib/libbsp/sh/gensh4/hw_init/Makefile.am Normal file
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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
PGM = $(ARCH)/hw_init.rel
#C_FILES = hw_init.c bsplibc.c bsppost.c bspstart.c bspclean.c sbrk.c \
# bootcard.c main.c gnatinstallhandler.c
C_FILES = hw_init.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
#
AM_CPPFLAGS += -DHZ=$(HZ)
AM_CFLAGS += -fomit-frame-pointer
$(PGM): $(OBJS)
$(make-rel)
all-local: $(ARCH) $(OBJS) $(PGM)
.PRECIOUS: $(PGM)
EXTRA_DIST = hw_init.c
include $(top_srcdir)/../../../../../../automake/local.am

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c/src/lib/libbsp/sh/gensh4/hw_init/hw_init.c Normal file
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/*
* SMFD board hardware initialization.
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* @(#) $Id$
*/
#include "rtems/score/sh7750_regs.h"
#include "rtems/score/sh_io.h"
#include "sdram.h"
#include "bsp.h"
/* early_hw_init --
* Perform initial hardware initialization:
* - setup clock generator
* - initialize bus state controller, memory settings, SDRAM
* - disable DMA
* - setup external ports, etc.
* - initialize interrupt controller
*
* This function should not access the memory! It should be compiled
* with -fomit-frame-pointer to avoid stack access.
*
* PARAMETERS:
* none
*
* RETURNS:
* none
*/
void
early_hw_init(void)
{
/* Explicitly turn off the MMU */
write32(0, SH7750_MMUCR);
/* Disable instruction and operand caches */
write32(0, SH7750_CCR);
/* Setup Clock Generator */
/*
* Input clock frequency is 16 MHz, MD0=1,
* CPU clock frequency already selected to 96MHz.
* Bus clock frequency should be set to 48 MHz, therefore divider 2
* should be applied (bus frequency is 48 MHz, clock period is 20.84ns).
* Peripheral frequency should be set to 24 MHz, therefore divider 4
* should be used.
*/
/* Prepare watchdog timer for frequency changing */
write16((read8(SH7750_WTCSR) & ~SH7750_WTCSR_TME) |
SH7750_WTCSR_KEY, SH7750_WTCSR);
write16(SH7750_WTCSR_MODE_IT | SH7750_WTCSR_CKS_DIV4096 |
SH7750_WTCSR_KEY, SH7750_WTCSR);
/* Turn PLL1 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL1EN, SH7750_FRQCR);
/* Perform Frequency Selection */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(SH7750_FRQCR_CKOEN | SH7750_FRQCR_PLL1EN |
SH7750_FRQCR_IFCDIV1 | SH7750_FRQCR_BFCDIV2 | SH7750_FRQCR_PFCDIV4,
SH7750_FRQCR);
/* Turn PLL2 on */
write16(0x40 | SH7750_WTCNT_KEY, SH7750_WTCNT);
write16(read16(SH7750_FRQCR) | SH7750_FRQCR_PLL2EN, SH7750_FRQCR);
/* Bus State Controller Initialization */
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
write32(
/* Pull-ups (IPUP, OPUP) enabled */
/* No Byte-Control SRAM mode for Area 1 and Area 3 */
SH7750_BCR1_BREQEN | /* Enable external bus requests */
/* No Partial Sharing Mode */
/* No MPX interface */
/* Memory and Control Signals are in HiZ */
SH7750_BCR1_A0BST_SRAM | /* No burst ROM in flash */
SH7750_BCR1_A5BST_SRAM | /* Area 5 is not in use */
SH7750_BCR1_A6BST_SRAM | /* Area 6 is not in use */
SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM /* Select Area 2 SDRAM type */
/* Area 5,6 programmed as a SRAM interface (not PCMCIA) */,
SH7750_BCR1);
write16(
(SH7750_BCR2_SZ_8 << SH7750_BCR2_A0SZ_S) | /* These bits is read-only
and set during reset */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A6SZ_S) | /* Area 6 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A5SZ_S) | /* Area 5 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A4SZ_S) | /* Area 4 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A3SZ_S) | /* Area 3 not used */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A2SZ_S) | /* SDRAM is 32-bit width */
(SH7750_BCR2_SZ_32 << SH7750_BCR2_A1SZ_S) | /* GDC is 32-bit width */
SH7750_BCR2_PORTEN, /* Use D32-D51 as a port */
SH7750_BCR2);
write32(
(0 << SH7750_WCR1_DMAIW_S) | /* 0 required for SDRAM RAS down mode */
(7 << SH7750_WCR1_A6IW_S) | /* Area 6 not used */
(7 << SH7750_WCR1_A5IW_S) | /* Area 5 not used */
(7 << SH7750_WCR1_A4IW_S) | /* Area 4 not used */
(7 << SH7750_WCR1_A3IW_S) | /* Area 3 not used */
(1 << SH7750_WCR1_A2IW_S) | /* 1 idle cycles inserted between acc */
(7 << SH7750_WCR1_A1IW_S) | /* Don't have GDC specs... Set safer. */
(1 << SH7750_WCR1_A0IW_S), /* 1 idle cycles inserted between acc */
SH7750_WCR1);
write32(
(SH7750_WCR2_WS15 << SH7750_WCR2_A6W_S) | /* Area 6 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A6B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A5W_S) | /* Area 5 not used */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A5B_S) |
(SH7750_WCR2_WS15 << SH7750_WCR2_A4W_S) | /* Area 4 not used */
(SH7750_WCR2_WS15 << SH7750_WCR2_A3W_S) | /*Area 3 not used*/
(SH7750_WCR2_SDRAM_CAS_LAT2 << SH7750_WCR2_A2W_S) | /* SDRAM CL = 2 */
(SH7750_WCR2_WS15 << SH7750_WCR2_A1W_S) | /* Area 1 (GDC)
requirements not known*/
(SH7750_WCR2_WS6 << SH7750_WCR2_A0W_S) | /* 4 wait states required
at 48MHz for 70ns mem.,
set closest greater */
(SH7750_WCR2_BPWS7 << SH7750_WCR2_A0B_S), /* burst mode disabled for
Area 0 flash ROM */
SH7750_WCR2);
write32(
SH7750_WCR3_A6S | /* Area 6 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A6H_S) |
SH7750_WCR3_A5S | /* Area 5 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A5H_S) |
SH7750_WCR3_A4S | /* Area 4 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A4H_S) |
SH7750_WCR3_A3S | /* Area 3 not used */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A3H_S) |
SH7750_WCR3_A2S | /* SDRAM - ignored */
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A2H_S) |
SH7750_WCR3_A1S | /* GDC - unknown, set max*/
(SH7750_WCR3_DHWS_3 << SH7750_WCR3_A1H_S) |
0 | /* flash ROM - no write strobe setup time required */
(SH7750_WCR3_DHWS_0 << SH7750_WCR3_A0H_S),
SH7750_WCR3);
#define MCRDEF \
/* SH7750_MCR_RASD | */ /* Set RAS Down mode */ \
(SH7750_MCR_TRC_0 | SH7750_MCR_TRAS_SDRAM_TRC_4 | \
/* RAS precharge time is 63ns; it corresponds to 4 clocks */ \
/* TCAS valid only for DRAM interface */ \
SH7750_MCR_TPC_SDRAM_1 | /* TPC = 20ns = 1 clock */ \
SH7750_MCR_RCD_SDRAM_2 | /* RCD = 21ns = 2 clock */ \
/* After write, next active command is not issued for a period of \
TPC + TRWL. SDRAM specifies that it should be BL+Trp clocks when \
CL=2. Trp = 20ns = 1clock; BL=8. Therefore we should wait 9 \
clocks. Don't know why, but 6 clocks (TRWL=5 and TPC=1) seems \
working. May be, something wrong in documentation? */ \
SH7750_MCR_TRWL_5 | /* TRWL = 5 clock */ \
SH7750_MCR_BE | /* Always enabled for SDRAM */ \
SH7750_MCR_SZ_32 | /* Memory data size is 32 bit */ \
(4 << SH7750_MCR_AMX_S) | /* Select memory device type */ \
SH7750_MCR_RFSH | /* Refresh is performed */ \
SH7750_MCR_RMODE_NORMAL) /* Auto-Refresh mode */
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Time between auto-refresh commands is 15.6 microseconds; refresh
timer counter frequency is 12 MHz; 1.56e-5*1.2e7= 187.2, therefore
program the refresh timer divider to 187 */
/* Sasha, try to run it with period 187 -- it should work! */
write16(SH7750_RTCOR_KEY | 187, SH7750_RTCOR);
/* write16(SH7750_RTCOR_KEY | 90, SH7750_RTCOR); */
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Select refresh counter base frequency as bus frequency/4 = 12 MHz */
write16(SH7750_RTCSR_CKS_CKIO_DIV4 | SH7750_RTCSR_KEY, SH7750_RTCSR);
/* Initialize Memory Control Register; disable refresh */
write32((MCRDEF & ~SH7750_MCR_RFSH) | SH7750_MCR_PALL, SH7750_MCR);
/* SDRAM power-up initialization require 100 microseconds delay after
stable power and clock fed; 100 microseconds corresponds to 7 refresh
intervals */
while (read16(SH7750_RFCR) <= 7);
/* Clear refresh timer counter */
write16(SH7750_RTCNT_KEY | 0, SH7750_RTCNT);
/* Clear refresh counter */
write16(SH7750_RFCR_KEY | 0, SH7750_RFCR);
/* Execute Precharge All command */
write32(0, SH7750_SDRAM_MODE_A2_32BIT(0));
/* Initialize Memory Control Register; enable refresh, prepare to
SDRAM mode register setting */
write32(MCRDEF | SH7750_MCR_MRSET, SH7750_MCR);
/* Wait until at least 2 auto-refresh commands to be executed */
while (read16(SH7750_RFCR) <= 10);
/* SDRAM data width is 32 bit (4 bytes), cache line size is 32 bytes,
therefore burst length is 8 (32 / 4) */
write8(0,SH7750_SDRAM_MODE_A2_32BIT(
SDRAM_MODE_BL_8 |
SDRAM_MODE_BT_SEQ | /* Only sequential burst mode supported
in SH7750 */
SDRAM_MODE_CL_2 | /* CAS latency is 2 */
SDRAM_MODE_OPC_BRBW) /* Burst read/burst write */
);
/* Bus State Controller initialized now */
/* Disable DMA controller */
write32(0, SH7750_DMAOR);
/* I/O port setup */
/* Configure all port bits as output - to fasciliate debugging */
write32(
SH7750_PCTRA_PBOUT(0) | SH7750_PCTRA_PBOUT(1) |
SH7750_PCTRA_PBOUT(2) | SH7750_PCTRA_PBOUT(3) |
SH7750_PCTRA_PBOUT(4) | SH7750_PCTRA_PBOUT(5) |
SH7750_PCTRA_PBOUT(6) | SH7750_PCTRA_PBOUT(7) |
SH7750_PCTRA_PBOUT(8) | SH7750_PCTRA_PBOUT(9) |
SH7750_PCTRA_PBOUT(10) | SH7750_PCTRA_PBOUT(11) |
SH7750_PCTRA_PBOUT(12) | SH7750_PCTRA_PBOUT(13) |
SH7750_PCTRA_PBOUT(14) | SH7750_PCTRA_PBOUT(15),
SH7750_PCTRA);
write32(
SH7750_PCTRB_PBOUT(16) | SH7750_PCTRB_PBOUT(17) |
SH7750_PCTRB_PBOUT(18) | SH7750_PCTRB_PBOUT(19),
SH7750_PCTRB);
/* Clear data in port */
write32(0, SH7750_PDTRA);
write32(0, SH7750_PDTRB);
/* Interrupt Controller Initialization */
write16(SH7750_ICR_IRLM, SH7750_ICR); /* IRLs serves as an independent
interrupt request lines */
/* Mask all requests at this time */
write16(
(0 << SH7750_IPRA_TMU0_S) |
(0 << SH7750_IPRA_TMU1_S) |
(0 << SH7750_IPRA_TMU2_S) |
(0 << SH7750_IPRA_RTC_S),
SH7750_IPRA);
write16(
(0 << SH7750_IPRB_WDT_S) |
(0 << SH7750_IPRB_REF_S) |
(0 << SH7750_IPRB_SCI1_S),
SH7750_IPRB);
write16(
(0 << SH7750_IPRC_GPIO_S) |
(0 << SH7750_IPRC_DMAC_S) |
(0 << SH7750_IPRC_SCIF_S) |
(0 << SH7750_IPRC_HUDI_S),
SH7750_IPRC);
}
/*
* cache_on --
* Enable instruction and operand caches
*/
void bsp_cache_on(void)
{
switch (boot_mode)
{
case SH4_BOOT_MODE_FLASH:
write32(SH7750_CCR_ICI | SH7750_CCR_ICE |
SH7750_CCR_OCI | SH7750_CCR_CB | SH7750_CCR_OCE,
SH7750_CCR);
break;
case SH4_BOOT_MODE_IPL:
asm volatile (
"mov #6, r0\n"
"xor r4, r4\n"
"trapa #0x3f\n"
: : : "r0", "r4");
break;
default: /* unreachable */
break;
}
}

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c/src/lib/libbsp/sh/gensh4/include/.cvsignore Normal file
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Makefile
Makefile.in

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c/src/lib/libbsp/sh/gensh4/include/Makefile.am Normal file
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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
include_HEADERS = bsp.h coverhd.h sdram.h
$(PROJECT_INCLUDE)/%.h: %.h
$(INSTALL_DATA) $< $@
PREINSTALL_FILES = $(PROJECT_INCLUDE) \
$(include_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
all-local: $(PREINSTALL_FILES)
include $(top_srcdir)/../../../../../../automake/local.am

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c/src/lib/libbsp/sh/gensh4/include/bsp.h Normal file
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/*
* This include file contains all board IO definitions.
*
* generic sh4 BSP
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Minor adaptations for sh2 by:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* $Id$
*/
#ifndef __gensh4_h
#define __gensh4_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems.h>
#include <clockdrv.h>
#include <console.h>
#include "rtems/score/sh7750_regs.h"
/*
* confdefs.h overrides for this BSP:
* - number of termios serial ports (defaults to 1)
* - Interrupt stack space is not minimum if defined.
*/
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
/*
* Define the time limits for RTEMS Test Suite test durations.
* Long test and short test duration limits are provided. These
* values are in seconds and need to be converted to ticks for the
* application.
*
*/
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
#ifndef SH7750_EVT_WDT_ITI
# error "..."
#endif
#define Install_tm27_vector( handler ) \
{ \
rtems_isr_entry old_handler; \
rtems_status_code status; \
status = rtems_interrupt_catch( (handler), \
SH7750_EVT_TO_NUM(SH7750_EVT_WDT_ITI), &old_handler); \
if (status != RTEMS_SUCCESSFUL) \
printf("Status of rtems_interrupt_catch = %d", status); \
}
#define Cause_tm27_intr() \
{ \
*(volatile rtems_unsigned16 *)SH7750_IPRB |= 0xf000; \
*(volatile rtems_unsigned16 *)SH7750_WTCSR = SH7750_WTCSR_KEY; \
*(volatile rtems_unsigned16 *)SH7750_WTCNT = SH7750_WTCNT_KEY | 0xfe; \
*(volatile rtems_unsigned16 *)SH7750_WTCSR = \
SH7750_WTCSR_KEY | SH7750_WTCSR_TME; \
}
#define Clear_tm27_intr() \
{ \
*(volatile rtems_unsigned16 *)SH7750_WTCSR = SH7750_WTCSR_KEY; \
}
#define Lower_tm27_intr() \
{ \
sh_set_interrupt_level((SH7750_IPRB & 0xf000) << SH4_SR_IMASK_S); \
}
/* Constants */
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*/
#define delay( microseconds ) CPU_delay(microseconds)
#define sh_delay( microseconds ) CPU_delay( microseconds )
/*
* Defined in the linker script 'linkcmds'
*/
extern unsigned32 HeapStart ;
extern unsigned32 HeapEnd ;
extern unsigned32 WorkSpaceStart ;
extern unsigned32 WorkSpaceEnd ;
extern void *CPU_Interrupt_stack_low ;
extern void *CPU_Interrupt_stack_high ;
/*
* This variable is nesessary for console driver.
*/
extern rtems_unsigned32 SH4_CPU_HZ_Frequency;
/*
* Defined in start.S
*/
extern unsigned32 boot_mode;
#define SH4_BOOT_MODE_FLASH 0
#define SH4_BOOT_MODE_IPL 1
/* miscellaneous stuff assumed to exist */
extern rtems_configuration_table BSP_Configuration;
extern void bsp_cleanup( void );
/*
* Device Driver Table Entries
*/
/*
* We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console
*/
#undef CONSOLE_DRIVER_TABLE_ENTRY
#define CONSOLE_DRIVER_TABLE_ENTRY \
{ console_initialize, console_open, console_close, \
console_read, console_write, console_control }
/*
* NOTE: Use the standard Clock driver entry
*/
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include all
* all calling overhead including passing of arguments.
*
*
* These are the figures tmoverhd.exe reported with gcc-2.95.1 -O4
* on a Hitachi SH7045F Evaluation Board with SH7045F at 29 MHz
*
* These results are assumed to be applicable to most SH7045/29MHz boards
*
* Author: John M.Mills (jmills@tga.com)
*
* COPYRIGHT (c) 1999. TGA Technologies, Inc., Norcross, GA, USA
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* This file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* $Id$
*/
#ifndef __COVERHD_h
#define __COVERHD_h
#ifdef __cplusplus
extern "C" {
#endif
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0
#define CALLING_OVERHEAD_TASK_CREATE 0
#define CALLING_OVERHEAD_TASK_IDENT 0
#define CALLING_OVERHEAD_TASK_START 0
#define CALLING_OVERHEAD_TASK_RESTART 0
#define CALLING_OVERHEAD_TASK_DELETE 0
#define CALLING_OVERHEAD_TASK_SUSPEND 0
#define CALLING_OVERHEAD_TASK_RESUME 0
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0
#define CALLING_OVERHEAD_TASK_MODE 0
#define CALLING_OVERHEAD_TASK_GET_NOTE 0
#define CALLING_OVERHEAD_TASK_SET_NOTE 0
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
#define CALLING_OVERHEAD_CLOCK_GET 0
#define CALLING_OVERHEAD_CLOCK_SET 0
#define CALLING_OVERHEAD_CLOCK_TICK 0
#define CALLING_OVERHEAD_TIMER_CREATE 0
#define CALLING_OVERHEAD_TIMER_IDENT 0
#define CALLING_OVERHEAD_TIMER_DELETE 0
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0
#define CALLING_OVERHEAD_TIMER_RESET 0
#define CALLING_OVERHEAD_TIMER_CANCEL 0
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0
#define CALLING_OVERHEAD_EVENT_SEND 0
#define CALLING_OVERHEAD_EVENT_RECEIVE 0
#define CALLING_OVERHEAD_SIGNAL_CATCH 0
#define CALLING_OVERHEAD_SIGNAL_SEND 0
#define CALLING_OVERHEAD_PARTITION_CREATE 0
#define CALLING_OVERHEAD_PARTITION_IDENT 0
#define CALLING_OVERHEAD_PARTITION_DELETE 0
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0
#define CALLING_OVERHEAD_REGION_CREATE 0
#define CALLING_OVERHEAD_REGION_IDENT 0
#define CALLING_OVERHEAD_REGION_DELETE 0
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0
#define CALLING_OVERHEAD_PORT_CREATE 0
#define CALLING_OVERHEAD_PORT_IDENT 0
#define CALLING_OVERHEAD_PORT_DELETE 0
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
#define CALLING_OVERHEAD_IO_INITIALIZE 0
#define CALLING_OVERHEAD_IO_OPEN 0
#define CALLING_OVERHEAD_IO_CLOSE 0
#define CALLING_OVERHEAD_IO_READ 0
#define CALLING_OVERHEAD_IO_WRITE 0
#define CALLING_OVERHEAD_IO_CONTROL 0
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/*
* SDRAM Mode Register
* Based on Fujitsu MB81F643242B data sheet.
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* @(#) $Id$
*/
#ifndef __SDRAM_H__
#define __SDRAM_H__
/* SDRAM Mode Register */
#define SDRAM_MODE_BL 0x0007 /* Burst Length: */
#define SDRAM_MODE_BL_1 0x0000 /* 0 */
#define SDRAM_MODE_BL_2 0x0001 /* 2 */
#define SDRAM_MODE_BL_4 0x0002 /* 4 */
#define SDRAM_MODE_BL_8 0x0003 /* 8 */
#define SDRAM_MODE_BL_16 0x0004 /* 16 */
#define SDRAM_MODE_BL_32 0x0005 /* 32 */
#define SDRAM_MODE_BL_64 0x0006 /* 64 */
#define SDRAM_MODE_BL_FULL 0x0007 /* Full column */
#define SDRAM_MODE_BT 0x0008 /* Burst Type: */
#define SDRAM_MODE_BT_SEQ 0x0000 /* Sequential */
#define SDRAM_MODE_BT_ILV 0x0008 /* Interleave */
#define SDRAM_MODE_CL 0x0070 /* CAS Latency: */
#define SDRAM_MODE_CL_1 0x0010 /* 1 */
#define SDRAM_MODE_CL_2 0x0020 /* 2 */
#define SDRAM_MODE_CL_3 0x0030 /* 3 */
#define SDRAM_MODE_OPC 0x0200 /* Opcode: */
#define SDRAM_MODE_OPC_BRBW 0x0000 /* Burst read & Burst write */
#define SDRAM_MODE_OPC_BRSW 0x0200 /* Burst read & Single write */
#endif

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Makefile
Makefile.in

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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
PGMS = $(ARCH)/start.o
S_FILES = start.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
OBJS = $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
#
$(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o: $(PGMS)
$(INSTALL_DATA) $< $@
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o
all-local: $(ARCH) $(OBJS) $(TMPINSTALL_FILES)
EXTRA_DIST = start.S
include $(top_srcdir)/../../../../../../automake/local.am

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/*
* start.S -- Initialization code for SH7750 generic BSP
*
* Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* Based on work:
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
* Modified to reflect Hitachi EDK SH7045F:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
* developmental purposes without any warranty nor representation
* by the authors or by TGA Technologies.
*
* COPYRIGHT (c) 1999-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include "asm.h"
#include "rtems/score/sh4_regs.h"
#include "rtems/score/sh7750_regs.h"
BEGIN_CODE
PUBLIC(start)
/*
* Algorithm of the first part of the start():
*
* 1. Initialize stack
* 2. Are we from reset or from gdb? Set value for boot_mode in r9.
* 3. Initialize hardware if we are from reset. Cache is off.
* 4. Copy data from flash to ram; set up boot mode and jump to real address.
* 5. Zero out bss.
* 6. Turn memory cach on.
*/
SYM (start):
! install the stack pointer
mov.l stack_k,r15
mov.l initial_sr_k,r0
ldc r0,ssr
ldc r0,sr
! let us see if we are from gdb stub or from power-on reset
bsr fake_func
nop
fake_func:
sts pr, r0
shlr8 r0
mov.l reset_pc_value_shift_8_k, r1
cmp/eq r0, r1
movt r9 ! r9 == ! boot_mode
neg r9, r9
add #1, r9 ! r9 == boot_mode
! what is in boot_mode?
cmp/pl r9 ! r9 > 0 -> T = 1
! if boot_mode != SH4_BOOT_MODE_FLASH
bt hw_init_end
nop
#if defined(START_HW_INIT) /* from $RTEMS_BSP.cfg */
! Initialize minimal hardware
! to run hw_init we need to calculate its address
! as it is before data coping
mov.l hw_init_k, r0
mov.l copy_start_k, r1
mov.l copy_end_k, r2
cmp/ge r0, r1
bt 0f
cmp/ge r0, r2
bf 0f
! if copy_start <= hw_init <= copy_end then
neg r1, r1
mov.l copy_start_in_rom_k, r3
add r1,r0
add r3, r0
0:
jsr @r0
nop !delay slot
#endif /* START_HW_INIT */
hw_init_end:
! copy data from rom to ram
mov.l copy_start_k, r0
mov.l copy_end_k, r1
mov.l copy_start_in_rom_k, r2
! if copy_from == copy_to do not copy anything
cmp/eq r0, r2
bt real_address
nop
copy_data_cycle:
cmp/ge r1, r0
bt end_of_copy_data_cycle
nop
mov.l @r2+, r3
mov.l r3, @r0
add #4, r0
bra copy_data_cycle
nop
end_of_copy_data_cycle:
! go to 0x8....... adresses
mov.l real_address_k, r0
lds r0, pr
rts
nop
real_address:
! write boot_mode to ram
mov.l boot_mode_k, r5
mov.l r9, @r5
zero_bss:
! zero out bss
mov.l __bss_start_k,r0
mov.l __bss_end_k,r1
mov #0,r2
0:
mov.l r2,@r0
add #4,r0
cmp/ge r0,r1
bt 0b
nop
! Turn cache on
mov.l cache_on_k, r0
jsr @r0
nop !delay slot
! Save old value of VBR register. We will need it to allow
! debugger agent hook exceptions.
mov.l __VBR_Saved_k,r0
stc vbr,r5
mov.l r5,@r0
! Set up VBR register
mov.l _vbr_base_k,r0
ldc r0,vbr
! initialise fpscr for gcc
mov.l set_fpscr_k, r1
jsr @r1
nop
! Set FPSCR register
mov.l initial_fpscr_k,r0
lds r0,fpscr
! call the mainline
mov #0,r4 ! argc
mov.l main_k,r0
jsr @r0
mov #0,r5 ! argv - can place in dead slot
! call exit
mov r0,r4
mov.l exit_k,r0
jsr @r0
or r0,r0
.global _stop
_stop:
mov #11,r0
mov #0,r4
trapa #0x3f
nop
__stop:
bra __stop
nop
END_CODE
.align 2
copy_start_k:
.long copy_start
copy_end_k:
.long copy_end
copy_start_in_rom_k:
.long copy_start_in_rom
real_address_k:
.long real_address
set_fpscr_k:
.long ___set_fpscr
_vbr_base_k:
.long SYM(_vbr_base)
__VBR_Saved_k:
.long SYM(_VBR_Saved)
stack_k:
.long SYM(stack)
__bss_start_k:
.long __bss_start
__bss_end_k:
.LONG __bss_end
main_k:
.long SYM(boot_card)
exit_k:
.long SYM(_exit)
#ifdef START_HW_INIT /* from $RTEMS_BSP.cfg */
hw_init_k:
.long SYM(early_hw_init)
#endif /* START_HW_INIT */
cache_on_k:
.long SYM(bsp_cache_on)
vects_k:
.long SYM(vectab)
vects_size:
.word 255
.align 2
initial_sr_k:
.long SH4_SR_MD | SH4_SR_IMASK
initial_fpscr_k:
#ifdef __SH4__
.long SH4_FPSCR_DN | SH4_FPSCR_PR | SH4_FPSCR_RM
#else
.long SH4_FPSCR_DN | SH4_FPSCR_RM
#endif
reset_pc_value_shift_8_k:
.long 0xa00000
boot_mode_k:
.long _boot_mode
#ifdef __ELF__
.section .stack,"aw"
#else
.section .stack
#endif
SYM(stack):
.long 0xdeaddead
#ifdef __ELF__
.section .bss,"aw"
#else
.section .bss
#endif
.global __sh4sim_dummy_register
__sh4sim_dummy_register:
.long 0
.section .data
.global _boot_mode
_boot_mode:
.long 0

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Makefile
Makefile.in

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##
## $Id$
##
AUTOMAKE_OPTIONS = foreign 1.4
VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
PGM = $(ARCH)/startup.rel
C_FILES = bsplibc.c bsppost.c bspstart.c bspclean.c sbrk.c \
bootcard.c main.c gnatinstallhandler.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
OBJS = $(C_O_FILES)
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
#
$(PROJECT_RELEASE)/lib/linkcmds: linkcmds
$(INSTALL_DATA) $< $@
$(PROJECT_RELEASE)/lib/linkcmds.rom: linkcmds.rom
$(INSTALL_DATA) $< $@
$(PROJECT_RELEASE)/lib/linkcmds.rom2ram: linkcmds.rom2ram
$(INSTALL_DATA) $< $@
$(PGM): $(OBJS)
$(make-rel)
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/linkcmds $(PROJECT_RELEASE)/lib/linkcmds.rom \
$(PROJECT_RELEASE)/lib/linkcmds.rom2ram
all-local: $(ARCH) $(TMPINSTALL_FILES) $(OBJS) $(PGM)
.PRECIOUS: $(PGM)
EXTRA_DIST = bspclean.c bspstart.c linkcmds linkcmds.rom linkcmds.rom2ram
include $(top_srcdir)/../../../../../../automake/local.am

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/*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <string.h>
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern void bsp_hw_init(void);
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
char *rtems_progname;
/*
* This variable is nesessary for console driver.
*/
unsigned32 SH4_CPU_HZ_Frequency = HZ;
/*
* Use the shared implementations of the following routines
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, unsigned32, int );
/*
* Function: bsp_pretasking_hook
*
* Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
void bsp_pretasking_hook(void)
{
bsp_libc_init(&HeapStart, (&HeapEnd - &HeapStart), 0);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start(void)
{
/*
For real boards you need to setup the hardware
and need to copy the vector table from rom to ram.
Depending on the board this can ether be done from inside the rom
startup code, rtems startup code or here.
*/
#ifndef START_HW_INIT
/* board hardware setup here, or from 'start.S' */
bsp_hw_init();
#endif
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ;
BSP_Configuration.work_space_size =
(unsigned32) &WorkSpaceEnd -
(unsigned32) &WorkSpaceStart ;
/*
* initialize the CPU table for this BSP
*/
#if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE )
_CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low ;
_CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ;
/* This isn't used anywhere */
Cpu_table.interrupt_stack_size =
(unsigned32) (&CPU_Interrupt_stack_high) -
(unsigned32) (&CPU_Interrupt_stack_low) ;
#endif
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE )
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
#endif
Cpu_table.clicks_per_second = HZ ;
}

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/*
* This file contains GNU linker directives for an general SH4
* board.
*
* Variations in memory size and allocation can be made by
* overriding some values with linker command-line arguments.
*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
OUTPUT_FORMAT("elf32-shl", "elf32-shl",
"elf32-shl")
OUTPUT_ARCH(sh)
ENTRY(_start)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
_WorkspaceSize = DEFINED(_WorkspaceSize) ? _WorkspaceSize : (1024 * 1024);
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
MEMORY
{
ram : o = 0x88100000, l = 7M
rom : o = 0x80000000, l = 4M
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
.init :
{
KEEP (*(.init))
} =0
.text :
{
*(.text)
*(.text.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.fini :
{
KEEP (*(.fini))
} =0
.rodata :
{
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
} > ram
.ctors :
{
___ctors = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
___ctors_end = .;
} > ram
.dtors :
{
___dtors = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
___dtors_end = .;
copy_start_in_rom = .;
} > ram
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data :
{
copy_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
copy_end = .;
} > ram
.eh_frame : { *(.eh_frame) } > ram
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.bss :
{
__bss_start = .;
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
__bss_end = .;
} > ram
. = ALIGN(16);
_HeapStart = . ;
. = . + _HeapSize ;
PROVIDE( _HeapEnd = . );
. = ALIGN(16);
_WorkSpaceStart = . ;
. = . + _WorkspaceSize ;
PROVIDE(_WorkSpaceEnd = .);
. = ALIGN(16);
.stack . : {
. = . + 4096;
}
. = ALIGN(16);
_CPU_Interrupt_stack_low = . ;
_CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
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.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
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.stab.index 0 : { *(.stab.index) }
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.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
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.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
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.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
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/* SGI/MIPS DWARF 2 extensions */
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/* These must appear regardless of . */
}

200
c/src/lib/libbsp/sh/gensh4/startup/linkcmds.rom Normal file
View File

@@ -0,0 +1,200 @@
/*
* This file contains GNU linker directives for an general SH4
* board.
*
* Variations in memory size and allocation can be made by
* overriding some values with linker command-line arguments.
*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
OUTPUT_FORMAT("elf32-shl", "elf32-shl",
"elf32-shl")
OUTPUT_ARCH(sh)
ENTRY(_start)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
_WorkspaceSize = DEFINED(_WorkspaceSize) ? _WorkspaceSize : (1024 * 1024);
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
MEMORY
{
/*
* Real values
*/
ram : o = 0x88000000, l = 8M
rom : o = 0x80000000, l = 4M
/*
* Fake values to test from gdb
*/
/*
ram : o = 0x88100000, l = 4M
rom : o = 0x88500000, l = 3M
*/
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
.init :
{
KEEP (*(.init))
} =0
.text :
{
*(.text)
*(.text.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > rom
_etext = .;
PROVIDE (etext = .);
.fini :
{
KEEP (*(.fini))
} =0
.rodata :
{
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
. = ALIGN(32);
} > rom
.ctors :
{
___ctors = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
___ctors_end = .;
} > rom
.dtors :
{
___dtors = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
___dtors_end = .;
copy_start_in_rom = .;
} > rom
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
{
copy_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
copy_end = .;
} > ram
.eh_frame : { *(.eh_frame) } > ram
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.bss :
{
__bss_start = .;
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
__bss_end = .;
} > ram
. = ALIGN(16);
_HeapStart = . ;
. = . + _HeapSize ;
PROVIDE( _HeapEnd = . );
. = ALIGN(16);
_WorkSpaceStart = . ;
. = . + _WorkspaceSize ;
PROVIDE(_WorkSpaceEnd = .);
. = ALIGN(16);
.stack . : {
stack_start = .;
. = . + 4096;
stack_end = .;
}
. = ALIGN(16);
_CPU_Interrupt_stack_low = . ;
_CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
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.stabstr 0 : { *(.stabstr) }
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Symbols in the DWARF debugging sections are relative to the beginning
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/* DWARF 1 */
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.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
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.debug_sfnames 0 : { *(.debug_sfnames) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
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/* These must appear regardless of . */
}

203
c/src/lib/libbsp/sh/gensh4/startup/linkcmds.rom2ram Normal file
View File

@@ -0,0 +1,203 @@
/*
* This file contains GNU linker directives for an general SH4
* board.
*
* Variations in memory size and allocation can be made by
* overriding some values with linker command-line arguments.
*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
OUTPUT_FORMAT("elf32-shl", "elf32-shl",
"elf32-shl")
OUTPUT_ARCH(sh)
ENTRY(_start)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
_WorkspaceSize = DEFINED(_WorkspaceSize) ? _WorkspaceSize : (1024 * 1024);
/*
* Area assignments:
* Area 0: Flash memory, SRAM interface
* Area 1: GDC
* Area 2: SDRAM
* Area 3-6: unused
*/
MEMORY
{
/*
* Real values
*/
ram : o = 0x88000000, l = 8M
rom : o = 0x80000000, l = 4M
/*
* Fake values to test from gdb
*/
/*
ram : o = 0x88100000, l = 4M
rom : o = 0x88500000, l = 3M
*/
}
SECTIONS
{
rom : {
copy_start_in_rom = .;
} >rom
/* Read-only sections, merged into text segment: */
.init :
{
KEEP (*(.init))
} =0
.text : AT(copy_start_in_rom)
{
copy_start = .;
*(.text)
*(.text.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} > ram
_etext = .;
PROVIDE (etext = .);
.fini :
{
KEEP (*(.fini))
} =0
.rodata : AT(LOADADDR(.text) + SIZEOF(.text))
{
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
. = ALIGN(32);
} > ram
.ctors : AT(LOADADDR(.rodata) + SIZEOF(.rodata))
{
___ctors = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
___ctors_end = .;
} > ram
.dtors : AT(LOADADDR(.ctors) + SIZEOF(.ctors))
{
___dtors = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
___dtors_end = .;
} > ram
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(128) + (. & (128 - 1));
.data : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
SORT(CONSTRUCTORS)
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/* We want the small data sections together, so single-instruction offsets
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we can shorten the on-disk segment size. */
.bss :
{
__bss_start = .;
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
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__bss_end = .;
} > ram
. = ALIGN(16);
_HeapStart = . ;
. = . + _HeapSize ;
PROVIDE( _HeapEnd = . );
. = ALIGN(16);
_WorkSpaceStart = . ;
. = . + _WorkspaceSize ;
PROVIDE(_WorkSpaceEnd = .);
. = ALIGN(16);
.stack . : {
stack_start = .;
. = . + 4096;
stack_end = .;
}
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_CPU_Interrupt_stack_low = . ;
_CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
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Symbols in the DWARF debugging sections are relative to the beginning
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/* DWARF 1 */
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/* GNU DWARF 1 extensions */
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/* These must appear regardless of . */
}

179
c/src/lib/libbsp/sh/gensh4/times Normal file
View File

@@ -0,0 +1,179 @@
#
# Timing Test Suite Results for the SH-4 BSP
#
# $Id$
#
Board: SH-4 based
CPU: SH-4
Clock Speed: 96 MHz
Memory Configuration: SDRAM
Times Reported in: microseconds
Timer Source: on-chip
RTEMS Version: ss-20010816
# DESCRIPTION time
== ================================================================= ====
SEMAPHORES
1 rtems_semaphore_create 19
rtems_semaphore_delete 20
rtems_semaphore_obtain: available 2
rtems_semaphore_obtain: not available -- NO_WAIT 2
rtems_semaphore_release: no waiting tasks 3
2 rtems_semaphore_obtain: not available -- caller blocks 18
3 rtems_semaphore_release: task readied -- preempts caller 18
TASKS
4 rtems_task_restart: blocked task -- preempts caller 36
rtems_task_restart: ready task -- preempts caller 26
rtems_semaphore_release: task readied -- returns to caller 5
rtems_task_create 25
rtems_task_start 15
rtems_task_restart: suspended task -- returns to caller 17
rtems_task_delete: suspended task 18
rtems_task_restart: ready task -- returns to caller 18
rtems_task_restart: blocked task -- returns to caller 22
rtems_task_delete: blocked task 19
5 rtems_task_suspend: calling task 13
rtems_task_resume: task readied -- preempts caller 12
6 rtems_task_restart: calling task 17
rtems_task_suspend: returns to caller 4
rtems_task_resume: task readied -- returns to caller 4
rtems_task_delete: ready task 23
7 rtems_task_restart: suspended task -- preempts caller 24
TASK MODES
8 rtems_task_set_priority: obtain current priority 2
rtems_task_set_priority: returns to caller 7
rtems_task_mode: obtain current mode 1
rtems_task_mode: no reschedule 1
rtems_task_mode: reschedule -- returns to caller 7
rtems_task_mode: reschedule -- preempts caller 21
rtems_task_set_note 1
rtems_task_get_note 2
rtems_clock_set 5
rtems_clock_get 0
QUEUES
9 rtems_message_queue_create 66
rtems_message_queue_send: no waiting tasks 5
rtems_message_queue_urgent: no waiting tasks 4
rtems_message_queue_receive: available 6
rtems_message_queue_flush: no messages flushed 4
rtems_message_queue_flush: messages flushed 4
rtems_message_queue_delete 22
10 rtems_message_queue_receive: not available -- NO_WAIT 4
rtems_message_queue_receive: not available -- caller blocks 27
11 rtems_message_queue_send: task readied -- preempts caller 19
12 rtems_message_queue_send: task readied -- returns to caller 9
13 rtems_message_queue_urgent: task readied -- preempts caller 18
14 rtems_message_queue_urgent: task readied -- returns to caller 7
EVENTS
15 rtems_event_receive: obtain current events 0
rtems_event_receive: not available -- NO_WAIT 2
rtems_event_receive: not available -- caller blocks 19
rtems_event_send: no task readied 2
rtems_event_receive: available 7
rtems_event_send: task readied -- returns to caller 6
16 rtems_event_send: task readied -- preempts caller 19
SCHEDULER
17 rtems_task_set_priority: preempts caller 22
18 rtems_task_delete: calling task 36
SIGNALS
19 rtems_signal_catch 6
rtems_signal_send: returns to caller 11
rtems_signal_send: signal to self 17
exit ASR overhead: returns to calling task 14
exit ASR overhead: returns to preempting task 13
PARTITIONS
20 rtems_partition_create 23
rtems_region_create 17
rtems_partition_get_buffer: available 8
rtems_partition_get_buffer: not available 3
rtems_partition_return_buffer 8
rtems_partition_delete 7
REGIONS
rtems_region_get_segment: available 5
rtems_region_get_segment: not available -- NO_WAIT 8
rtems_region_return_segment: no waiting tasks 4
rtems_region_get_segment: not available -- caller blocks 28
rtems_region_return_segment: task readied -- preempts caller 36
rtems_region_return_segment: task readied -- returns to caller 14
rtems_region_delete 7
IO
rtems_io_initialize 0
rtems_io_open 0
rtems_io_close 0
rtems_io_read 0
rtems_io_write 0
rtems_io_control 0
IDENT
21 rtems_task_ident 20
rtems_message_queue_ident 19
rtems_semaphore_ident 21
rtems_partition_ident 19
rtems_region_ident 20
rtems_port_ident 19
rtems_timer_ident 20
rtems_rate_monotonic_ident 20
QUEUE BROADCAST
22 rtems_message_queue_broadcast: task readied -- returns to caller 21
rtems_message_queue_broadcast: no waiting tasks 4
rtems_message_queue_broadcast: task readied -- preempts caller 22
TIMER
23 rtems_timer_create 3
rtems_timer_fire_after: inactive 6
rtems_timer_fire_after: active 5
rtems_timer_cancel: active 3
rtems_timer_cancel: inactive 3
rtems_timer_reset: inactive 5
rtems_timer_reset: active 5
rtems_timer_fire_when: inactive 6
rtems_timer_fire_when: active 6
rtems_timer_delete: active 4
rtems_timer_delete: inactive 3
rtems_task_wake_when 21
24 rtems_task_wake_after: yield -- returns to caller 1
rtems_task_wake_after: yields -- preempts caller 13
25 rtems_clock_tick 9
ISR & MULTITASKING
26 _ISR_Disable 1
_ISR_Flash 0
_ISR_Enable 0
_Thread_Disable_dispatch 0
_Thread_Enable_dispatch 1
_Thread_Set_state 3
_Thread_Disptach (NO FP) 14
context switch: no floating point contexts 7
context switch: self 1
context switch: to another task 1
fp context switch: restore 1st FP task 11
fp context switch: save idle, restore initialized 3
fp context switch: save idle, restore idle 12
fp context switch: save initialized, restore initialized 2
_Thread_Resume 6
_Thread_Unblock 4
_Thread_Ready 4
_Thread_Get 0
_Semaphore_Get 0
_Thread_Get: invalid id 0
ISR OVERHEAD
27 interrupt entry overhead: returns to interrupted task 11
interrupt exit overhead: returns to interrupted task 5
interrupt entry overhead: returns to nested interrupt 6
interrupt exit overhead: returns to nested interrupt 3
interrupt entry overhead: returns to preempting task 7
interrupt exit overhead: returns to preempting task 20
DUAL-PORTED MEMORY
28 rtems_port_create 9
rtems_port_external_to_internal 1
rtems_port_internal_to_external 1
rtems_port_delete 12
MONOTONIC RATE
29 rtems_rate_monotonic_create 11
rtems_rate_monotonic_period: initiate period -- returns to caller 14
rtems_rate_monotonic_period: obtain status 7
rtems_rate_monotonic_cancel 12
rtems_rate_monotonic_delete: inactive 12
rtems_rate_monotonic_delete: active 9
rtems_rate_monotonic_period: conclude periods -- caller blocks 18

2
c/src/lib/libbsp/sh/gensh4/wrapup/.cvsignore Normal file
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@@ -0,0 +1,2 @@
Makefile
Makefile.in

40
c/src/lib/libbsp/sh/gensh4/wrapup/Makefile.am Normal file
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##
## $Id$
##
## build and install libbsp
##
AUTOMAKE_OPTIONS = foreign 1.4
BSP_PIECES = startup hw_init
# pieces to pick up out of libcpu/sh/sh7750
CPU_PIECES = clock sci timer score
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \
$(foreach piece, $(CPU_PIECES), ../../../../libcpu/$(RTEMS_CPU)/sh7750/$(piece)/$(ARCH)/$(piece).rel)
LIB = $(ARCH)/libbsp.a
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/compile.am
include $(top_srcdir)/../../../../../../automake/lib.am
#
# (OPTIONAL) Add local stuff here using +=
#
$(LIB): $(OBJS)
$(make-library)
$(PROJECT_RELEASE)/lib/libbsp$(LIB_VARIANT).a: $(LIB)
$(INSTALL_DATA) $< $@
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/libbsp$(LIB_VARIANT).a
all-local: $(ARCH) $(OBJS) $(LIB) $(TMPINSTALL_FILES)
.PRECIOUS: $(LIB)
include $(top_srcdir)/../../../../../../automake/local.am

1
c/src/lib/libbsp/sh/shsim/.cvsignore
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@@ -1,6 +1,7 @@
Makefile
Makefile.in
aclocal.m4
autom4te.cache
config.cache
config.guess
config.log