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2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>

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This modification is part of the submitted modifications necessary to
	support the IBM PPC405 family.  This submission was reviewed by
	Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
	not negatively impact the ppc403 BSPs.  The submission and tracking
	process was captured as PR50.
	* shared/asm.h, shared/ppc.h: Added PPC405 support.
This commit is contained in:
Joel Sherrill
2001-11-08 23:32:59 +00:00
parent 0aa0960866
commit 95e0ca9337
9 changed files with 76 additions and 18 deletions
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9
c/src/exec/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,12 @@
2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>
This modification is part of the submitted modifications necessary to
support the IBM PPC405 family. This submission was reviewed by
Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
not negatively impact the ppc403 BSPs. The submission and tracking
process was captured as PR50.
* shared/asm.h, shared/ppc.h: Added PPC405 support.
2001-10-22 Andy Dachs <a.dachs@sstl.co.uk> 2001-10-22 Andy Dachs <a.dachs@sstl.co.uk>
* shared/ppc.h: Added mpc8260 support. * shared/ppc.h: Added mpc8260 support.

13
c/src/exec/score/cpu/powerpc/asm.h
View File

@@ -164,10 +164,10 @@
*/ */
#define srr0 0x01a #define srr0 0x01a
#define srr1 0x01b #define srr1 0x01b
#ifdef ppc403 #if defined(ppc403) || defined(ppc405)
#define srr2 0x3de /* IBM 400 series only */ #define srr2 0x3de /* IBM 400 series only */
#define srr3 0x3df /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */
#endif /* ppc403 */ #endif /* ppc403 or ppc405 */
#define sprg0 0x110 #define sprg0 0x110
#define sprg1 0x111 #define sprg1 0x111
@@ -177,15 +177,22 @@
#define dar 0x013 /* Data Address Register */ #define dar 0x013 /* Data Address Register */
#define dec 0x016 /* Decrementer Register */ #define dec 0x016 /* Decrementer Register */
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */ /* the following SPR/DCR registers exist only in IBM 400 series */
#define dear 0x3d5 #define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */ #define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */ #define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */
#if defined (ppc403)
#define exisr 0x040 /* DCR: external interrupt status register */ #define exisr 0x040 /* DCR: external interrupt status register */
#define exier 0x042 /* DCR: external interrupt enable register */ #define exier 0x042 /* DCR: external interrupt enable register */
#endif /* ppc403 */
#if defined(ppc405)
#define exisr 0x0C0 /* DCR: external interrupt status register */
#define exier 0x0C2 /* DCR: external interrupt enable register */
#endif /* ppc405 */
#define br0 0x080 /* DCR: memory bank register 0 */ #define br0 0x080 /* DCR: memory bank register 0 */
#define br1 0x081 /* DCR: memory bank register 1 */ #define br1 0x081 /* DCR: memory bank register 1 */
#define br2 0x082 /* DCR: memory bank register 2 */ #define br2 0x082 /* DCR: memory bank register 2 */

8
c/src/exec/score/cpu/powerpc/rtems/score/ppc.h
View File

@@ -124,7 +124,7 @@ extern "C" {
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0 #define PPC_HAS_DOUBLE 0
#elif defined(ppc403) #elif defined(ppc403) || defined(ppc405)
/* /*
* IBM 403 * IBM 403
* *
@@ -133,7 +133,11 @@ extern "C" {
* Does not have user mode. * Does not have user mode.
*/ */
#if defined(ppc403)
#define CPU_MODEL_NAME "PowerPC 403" #define CPU_MODEL_NAME "PowerPC 403"
#elif defined (ppc405)
#define CPU_MODEL_NAME "PowerPC 405"
#endif
#define PPC_ALIGNMENT 4 #define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16 #define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1 #define PPC_HAS_RFCI 1
@@ -504,7 +508,7 @@ extern "C" {
#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/

13
c/src/exec/score/cpu/powerpc/shared/asm.h
View File

@@ -164,10 +164,10 @@
*/ */
#define srr0 0x01a #define srr0 0x01a
#define srr1 0x01b #define srr1 0x01b
#ifdef ppc403 #if defined(ppc403) || defined(ppc405)
#define srr2 0x3de /* IBM 400 series only */ #define srr2 0x3de /* IBM 400 series only */
#define srr3 0x3df /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */
#endif /* ppc403 */ #endif /* ppc403 or ppc405 */
#define sprg0 0x110 #define sprg0 0x110
#define sprg1 0x111 #define sprg1 0x111
@@ -177,15 +177,22 @@
#define dar 0x013 /* Data Address Register */ #define dar 0x013 /* Data Address Register */
#define dec 0x016 /* Decrementer Register */ #define dec 0x016 /* Decrementer Register */
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */ /* the following SPR/DCR registers exist only in IBM 400 series */
#define dear 0x3d5 #define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */ #define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */ #define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */
#if defined (ppc403)
#define exisr 0x040 /* DCR: external interrupt status register */ #define exisr 0x040 /* DCR: external interrupt status register */
#define exier 0x042 /* DCR: external interrupt enable register */ #define exier 0x042 /* DCR: external interrupt enable register */
#endif /* ppc403 */
#if defined(ppc405)
#define exisr 0x0C0 /* DCR: external interrupt status register */
#define exier 0x0C2 /* DCR: external interrupt enable register */
#endif /* ppc405 */
#define br0 0x080 /* DCR: memory bank register 0 */ #define br0 0x080 /* DCR: memory bank register 0 */
#define br1 0x081 /* DCR: memory bank register 1 */ #define br1 0x081 /* DCR: memory bank register 1 */
#define br2 0x082 /* DCR: memory bank register 2 */ #define br2 0x082 /* DCR: memory bank register 2 */

8
c/src/exec/score/cpu/powerpc/shared/ppc.h
View File

@@ -124,7 +124,7 @@ extern "C" {
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0 #define PPC_HAS_DOUBLE 0
#elif defined(ppc403) #elif defined(ppc403) || defined(ppc405)
/* /*
* IBM 403 * IBM 403
* *
@@ -133,7 +133,11 @@ extern "C" {
* Does not have user mode. * Does not have user mode.
*/ */
#if defined(ppc403)
#define CPU_MODEL_NAME "PowerPC 403" #define CPU_MODEL_NAME "PowerPC 403"
#elif defined (ppc405)
#define CPU_MODEL_NAME "PowerPC 405"
#endif
#define PPC_ALIGNMENT 4 #define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16 #define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1 #define PPC_HAS_RFCI 1
@@ -504,7 +508,7 @@ extern "C" {
#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/

9
cpukit/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,12 @@
2001-11-08 Dennis Ehlin (ECS) <Dennis.Ehlin@ecs.ericsson.se>
This modification is part of the submitted modifications necessary to
support the IBM PPC405 family. This submission was reviewed by
Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
not negatively impact the ppc403 BSPs. The submission and tracking
process was captured as PR50.
* shared/asm.h, shared/ppc.h: Added PPC405 support.
2001-10-22 Andy Dachs <a.dachs@sstl.co.uk> 2001-10-22 Andy Dachs <a.dachs@sstl.co.uk>
* shared/ppc.h: Added mpc8260 support. * shared/ppc.h: Added mpc8260 support.

13
cpukit/score/cpu/powerpc/asm.h
View File

@@ -164,10 +164,10 @@
*/ */
#define srr0 0x01a #define srr0 0x01a
#define srr1 0x01b #define srr1 0x01b
#ifdef ppc403 #if defined(ppc403) || defined(ppc405)
#define srr2 0x3de /* IBM 400 series only */ #define srr2 0x3de /* IBM 400 series only */
#define srr3 0x3df /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */
#endif /* ppc403 */ #endif /* ppc403 or ppc405 */
#define sprg0 0x110 #define sprg0 0x110
#define sprg1 0x111 #define sprg1 0x111
@@ -177,15 +177,22 @@
#define dar 0x013 /* Data Address Register */ #define dar 0x013 /* Data Address Register */
#define dec 0x016 /* Decrementer Register */ #define dec 0x016 /* Decrementer Register */
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */ /* the following SPR/DCR registers exist only in IBM 400 series */
#define dear 0x3d5 #define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */ #define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */ #define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */
#if defined (ppc403)
#define exisr 0x040 /* DCR: external interrupt status register */ #define exisr 0x040 /* DCR: external interrupt status register */
#define exier 0x042 /* DCR: external interrupt enable register */ #define exier 0x042 /* DCR: external interrupt enable register */
#endif /* ppc403 */
#if defined(ppc405)
#define exisr 0x0C0 /* DCR: external interrupt status register */
#define exier 0x0C2 /* DCR: external interrupt enable register */
#endif /* ppc405 */
#define br0 0x080 /* DCR: memory bank register 0 */ #define br0 0x080 /* DCR: memory bank register 0 */
#define br1 0x081 /* DCR: memory bank register 1 */ #define br1 0x081 /* DCR: memory bank register 1 */
#define br2 0x082 /* DCR: memory bank register 2 */ #define br2 0x082 /* DCR: memory bank register 2 */

13
cpukit/score/cpu/powerpc/rtems/asm.h
View File

@@ -164,10 +164,10 @@
*/ */
#define srr0 0x01a #define srr0 0x01a
#define srr1 0x01b #define srr1 0x01b
#ifdef ppc403 #if defined(ppc403) || defined(ppc405)
#define srr2 0x3de /* IBM 400 series only */ #define srr2 0x3de /* IBM 400 series only */
#define srr3 0x3df /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */
#endif /* ppc403 */ #endif /* ppc403 or ppc405 */
#define sprg0 0x110 #define sprg0 0x110
#define sprg1 0x111 #define sprg1 0x111
@@ -177,15 +177,22 @@
#define dar 0x013 /* Data Address Register */ #define dar 0x013 /* Data Address Register */
#define dec 0x016 /* Decrementer Register */ #define dec 0x016 /* Decrementer Register */
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
/* the following SPR/DCR registers exist only in IBM 400 series */ /* the following SPR/DCR registers exist only in IBM 400 series */
#define dear 0x3d5 #define dear 0x3d5
#define evpr 0x3d6 /* SPR: exception vector prefix register */ #define evpr 0x3d6 /* SPR: exception vector prefix register */
#define iccr 0x3fb /* SPR: instruction cache control reg. */ #define iccr 0x3fb /* SPR: instruction cache control reg. */
#define dccr 0x3fa /* SPR: data cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */
#if defined (ppc403)
#define exisr 0x040 /* DCR: external interrupt status register */ #define exisr 0x040 /* DCR: external interrupt status register */
#define exier 0x042 /* DCR: external interrupt enable register */ #define exier 0x042 /* DCR: external interrupt enable register */
#endif /* ppc403 */
#if defined(ppc405)
#define exisr 0x0C0 /* DCR: external interrupt status register */
#define exier 0x0C2 /* DCR: external interrupt enable register */
#endif /* ppc405 */
#define br0 0x080 /* DCR: memory bank register 0 */ #define br0 0x080 /* DCR: memory bank register 0 */
#define br1 0x081 /* DCR: memory bank register 1 */ #define br1 0x081 /* DCR: memory bank register 1 */
#define br2 0x082 /* DCR: memory bank register 2 */ #define br2 0x082 /* DCR: memory bank register 2 */

8
cpukit/score/cpu/powerpc/rtems/score/ppc.h
View File

@@ -124,7 +124,7 @@ extern "C" {
#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
#define PPC_HAS_DOUBLE 0 #define PPC_HAS_DOUBLE 0
#elif defined(ppc403) #elif defined(ppc403) || defined(ppc405)
/* /*
* IBM 403 * IBM 403
* *
@@ -133,7 +133,11 @@ extern "C" {
* Does not have user mode. * Does not have user mode.
*/ */
#if defined(ppc403)
#define CPU_MODEL_NAME "PowerPC 403" #define CPU_MODEL_NAME "PowerPC 403"
#elif defined (ppc405)
#define CPU_MODEL_NAME "PowerPC 405"
#endif
#define PPC_ALIGNMENT 4 #define PPC_ALIGNMENT 4
#define PPC_CACHE_ALIGNMENT 16 #define PPC_CACHE_ALIGNMENT 16
#define PPC_HAS_RFCI 1 #define PPC_HAS_RFCI 1
@@ -504,7 +508,7 @@ extern "C" {
#define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET
#if defined(ppc403) #if defined(ppc403) || defined(ppc405)
#define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
#define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/