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Added CPU_ISR_PASSES_FRAME_POINTER so some ports could pass just the

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vector number to user ISR's and other ports could pass both the vector
number and a pointer to the ISF.
This commit is contained in:
Joel Sherrill
1998-06-03 19:00:17 +00:00
parent 75d0b0b83a
commit 937a6f3cef
14 changed files with 140 additions and 0 deletions
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8
c/src/exec/score/cpu/a29k/cpu.h
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@@ -159,6 +159,14 @@ extern void a29k_sigdfl_sup(void);
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*

8
c/src/exec/score/cpu/hppa1.1/cpu.h
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@@ -40,6 +40,14 @@ extern "C" {
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* HPPA has hardware FP, it is assumed to exist by GCC so all tasks
* may implicitly use it (especially for integer multiplies). Because

8
c/src/exec/score/cpu/i386/cpu.h
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@@ -39,6 +39,14 @@ extern "C" {
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP, some have an FPU such as the i387
* for the i386, others have it built in (i486DX, Pentium).

8
c/src/exec/score/cpu/i960/cpu.h
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@@ -40,6 +40,14 @@ extern "C" {
#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP (SA/KA/CA/CF), others have it built in
* (KB/MC/MX). There does not appear to be an external coprocessor

8
c/src/exec/score/cpu/m68k/cpu.h
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@@ -46,6 +46,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK 1
#endif
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP, some have an FPU such as the
* MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).

8
c/src/exec/score/cpu/mips64orion/cpu.h
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@@ -146,6 +146,14 @@ extern void mips_fatal_error ( int error );
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*

8
c/src/exec/score/cpu/no_cpu/cpu.h
View File

@@ -122,6 +122,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*

40
c/src/exec/score/cpu/powerpc/cpu.h
View File

@@ -146,6 +146,14 @@ struct CPU_Interrupt_frame;
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
/*
* Does the CPU have hardware floating point?
*
@@ -1094,6 +1102,38 @@ static inline unsigned int CPU_swap_u32(
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
/*
* Routines to access the decrementer register
*/
#define PPC_Set_decrementer( _clicks ) \
do { \
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
/*
* Routines to access the time base register
*/
static inline unsigned64 PPC_Get_timebase_register( void )
{
unsigned32 tbr_low;
unsigned32 tbr_high;
unsigned32 tbr_high_old;
unsigned64 tbr;
do {
asm volatile( "mftbu %0" : "=r" (tbr_high_old));
asm volatile( "mftb %0" : "=r" (tbr_low));
asm volatile( "mftbu %0" : "=r" (tbr_high));
} while ( tbr_high_old != tbr_high );
tbr = tbr_high;
tbr <<= 32;
tbr |= tbr_low;
return tbr;
}
#ifdef __cplusplus
}
#endif

7
c/src/exec/score/cpu/sh/cpu.h
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@@ -108,6 +108,13 @@ extern "C" {
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?

8
c/src/exec/score/cpu/sparc/cpu.h
View File

@@ -93,6 +93,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*

8
c/src/exec/score/cpu/unix/cpu.h
View File

@@ -133,6 +133,14 @@ extern "C" {
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*

7
c/src/exec/score/headers/isr.h
View File

@@ -46,9 +46,16 @@ typedef void ISR_Handler;
* Pointer to an ISR Handler
*/
#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number,
CPU_Interrupt_frame *
);
#else
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number
);
#endif
/*
* This constant promotes out the number of vectors truly supported by
* the current CPU being used. This is usually the number of distinct vectors

7
c/src/exec/score/include/rtems/score/isr.h
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@@ -46,9 +46,16 @@ typedef void ISR_Handler;
* Pointer to an ISR Handler
*/
#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number,
CPU_Interrupt_frame *
);
#else
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number
);
#endif
/*
* This constant promotes out the number of vectors truly supported by
* the current CPU being used. This is usually the number of distinct vectors