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2001-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>

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* include/iosh7045.h: Add SCI0_SMR, SCI1_SMR for sh7032
	compatibility to make simsh happy.
This commit is contained in:
Joel Sherrill
2001-11-14 18:40:22 +00:00
parent 1ea5087f79
commit 92cf35dbd3
2 changed files with 9 additions and 0 deletions
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5
c/src/lib/libcpu/sh/sh7045/ChangeLog
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@@ -1,3 +1,8 @@
2001-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* include/iosh7045.h: Add SCI0_SMR, SCI1_SMR for sh7032
compatibility to make simsh happy.
2001-10-12 Joel Sherrill <joel@OARcorp.com> 2001-10-12 Joel Sherrill <joel@OARcorp.com>
* clock/ckinit.c, include/iosh7045.h, include/ispsh7045.h, * clock/ckinit.c, include/iosh7045.h, include/ispsh7045.h,

4
c/src/lib/libcpu/sh/sh7045/include/iosh7045.h
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@@ -66,6 +66,8 @@
#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */ #define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */
#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */ #define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */
#define SCI0_SMR SCI_SMR0
/* SCI1 Registers */ /* SCI1 Registers */
#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */ #define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */
#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */ #define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */
@@ -74,6 +76,8 @@
#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */ #define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */
#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */ #define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */
#define SCI1_SMR SCI_SMR1
/* ADI */ /* ADI */
/* High Speed A/D (Excluding A-Mask Part)*/ /* High Speed A/D (Excluding A-Mask Part)*/
#define ADDRA (REG_BASE + 0x03F0) /* short */ #define ADDRA (REG_BASE + 0x03F0) /* short */