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2007-05-09 Ray Xu <rayx@gmail.com>

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* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
          implement a compact do_data_abort() in simple_abort.c
This commit is contained in:
Joel Sherrill
2007-05-15 17:59:47 +00:00
parent 40a1237662
commit 91e07d0d89
2 changed files with 10 additions and 150 deletions
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10
cpukit/score/cpu/arm/ChangeLog
View File

@@ -1,3 +1,13 @@
2007-05-09 Ray Xu <rayx@gmail.com>
* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
implement a compact do_data_abort() in simple_abort.c
2007-05-09 Ray Xu <rayx@gmail.com>
* cpu.c: move do_data_abort() to libbsp/arm/shared/abort/
implement a compact do_data_abort() in simple_abort.c
2007-05-09 Ralf Corsépius <ralf.corsepius@rtems.org>
* rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.

150
cpukit/score/cpu/arm/cpu.c
View File

@@ -32,9 +32,6 @@
*
*/
uint32_t g_data_abort_cnt = 0;
uint32_t g_data_abort_insn_list[1024];
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch) /* ignored on this CPU */
@@ -221,150 +218,3 @@ void rtems_exception_init_mngt()
#define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v)
#define GET_OFFSET(insn) (insn & 0xfff)
char *_print_full_context_mode2txt[0x20]={
[0x10]="user", /* User */
[0x11]="fiq", /* FIQ - Fast Interrupt Request */
[0x12]="irq", /* IRQ - Interrupt Request */
[0x13]="super", /* Supervisor */
[0x17]="abort", /* Abort */
[0x1b]="undef", /* Undefined */
[0x1f]="system" /* System */
};
void _print_full_context(uint32_t spsr)
{
char *mode;
uint32_t prev_sp,prev_lr,cpsr,tmp;
int i;
printk("active thread thread 0x%08x\n", _Thread_Executing->Object.id);
mode=_print_full_context_mode2txt[spsr&0x1f];
if(!mode) mode="unknown";
asm volatile (" MRS %[cpsr], cpsr \n"
" ORR %[tmp], %[spsr], #0xc0 \n"
" MSR cpsr_c, %[tmp] \n"
" MOV %[prev_sp], sp \n"
" MOV %[prev_lr], lr \n"
" MSR cpsr_c, %[cpsr] \n"
: [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
[cpsr] "=&r" (cpsr), [tmp] "=&r" (tmp)
: [spsr] "r" (spsr)
: "cc");
printk("Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n", prev_sp, prev_lr, cpsr);
for(i=0;i<48;){
printk(" 0x%08x",((uint32_t*)prev_sp)[i++]);
if((i%6) == 0)
printk("\n");
}
}
/* This function is supposed to figure out what caused the
* data abort, do that, then return.
*
* All unhandled instructions cause the system to hang.
*/
void do_data_abort(uint32_t insn, uint32_t spsr,
Context_Control *ctx)
{
/* Clarify, which type is correct, CPU_Exception_frame or Context_Control */
uint8_t decode;
uint8_t insn_type;
#if 0
uint32_t rn;
uint32_t rd;
uint8_t *src_addr;
#endif
uint32_t tmp;
g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
g_data_abort_cnt++;
decode = ((insn >> 20) & 0xff);
insn_type = decode & INSN_MASK;
switch(insn_type) {
case INSN_STM1:
printk("\n\nINSN_STM1\n");
break;
case INSN_STM2:
printk("\n\nINSN_STM2\n");
break;
case INSN_STR:
printk("\n\nINSN_STR\n");
break;
case INSN_STRB:
printk("\n\nINSN_STRB\n");
break;
case INSN_LDM1:
printk("\n\nINSN_LDM1\n");
break;
case INSN_LDM23:
printk("\n\nINSN_LDM23\n");
break;
case INSN_LDR:
printk("\n\nINSN_LDR\n");
#if 0
rn = GET_RN(insn);
rd = GET_RD(insn);
/* immediate offset/index */
if (GET_I(insn) == 0) {
switch(decode & 0x12) { /* P and W bits */
case 0x00: /* P=0, W=0 -> base is updated, post-indexed */
printk("\tPost-indexed\n");
break;
case 0x02: /* P=0, W=1 -> user mode access */
printk("\tUser mode\n");
break;
case 0x10: /* P=1, W=0 -> base not updated */
src_addr = (uint8_t *)GET_REG(rn, ctx);
if (GET_U(insn) == 0) {
src_addr -= GET_OFFSET(insn);
} else {
src_addr += GET_OFFSET(insn);
}
tmp = (src_addr[0] |
(src_addr[1] << 8) |
(src_addr[2] << 16) |
(src_addr[3] << 24));
SET_REG(rd, ctx, tmp);
return;
break;
case 0x12: /* P=1, W=1 -> base is updated, pre-indexed */
printk("\tPre-indexed\n");
break;
}
}
#endif
break;
case INSN_LDRB:
printk("\n\nINSN_LDRB\n");
break;
default:
printk("\n\nUnrecognized instruction\n");
break;
}
printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n",
ctx->register_lr - 8, insn, spsr);
_print_full_context(spsr);
/* disable interrupts, wait forever */
_CPU_ISR_Disable(tmp);
while(1) {
continue;
}
return;
}