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nios2: Use Per_CPU_Control::isr_dispatch_disable

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This commit is contained in:
Sebastian Huber
2021-01-12 07:13:08 +01:00
parent c968b27fbd
commit 9165349d39
5 changed files with 23 additions and 35 deletions
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14
cpukit/score/cpu/nios2/include/rtems/score/cpu.h
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@@ -106,11 +106,6 @@ extern "C" {
*
* There is no need to save the global pointer (gp) since it is a system wide
* constant and set-up with the C runtime environment.
*
* The @a thread_dispatch_disabled field is used for the external interrupt
* controller (EIC) support.
*
* @see _Nios2_Thread_dispatch_disabled
*/
typedef struct {
uint32_t r16;
@@ -125,7 +120,14 @@ typedef struct {
uint32_t status;
uint32_t sp;
uint32_t ra;
uint32_t thread_dispatch_disabled;
/**
* @brief This member is used for the external interrupt controller (EIC) support.
*
* It corresponds to Per_CPU_Control::isr_dispatch_disable.
*/
uint32_t isr_dispatch_disable;
uint32_t stack_mpubase;
uint32_t stack_mpuacc;
} Context_Control;

13
cpukit/score/cpu/nios2/include/rtems/score/nios2-utility.h
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@@ -47,7 +47,7 @@
#define NIOS2_CONTEXT_OFFSET_STATUS 36
#define NIOS2_CONTEXT_OFFSET_SP 40
#define NIOS2_CONTEXT_OFFSET_RA 44
#define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48
#define NIOS2_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE 48
#define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52
#define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56
@@ -143,17 +143,6 @@
extern "C" {
#endif /* __cplusplus */
/**
* @brief Nios II specific thread dispatch disabled indicator.
*
* This global variable is used by the interrupt dispatch support for the
* external interrupt controller (EIC) with shadow registers. This makes it
* possible to do the thread dispatch after an interrupt without disabled
* interrupts and thus probably reduce the maximum interrupt latency. Its
* purpose is to prevent unbounded stack usage of the interrupted thread.
*/
extern uint32_t _Nios2_Thread_dispatch_disabled;
/**
* @brief This global symbol specifies the status register mask used to disable
* interrupts.

12
cpukit/score/cpu/nios2/nios2-context-switch.S
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@@ -15,17 +15,17 @@
#include "config.h"
#endif
#include <rtems/score/cpu.h>
#include <rtems/score/percpu.h>
#include <rtems/score/nios2-utility.h>
.extern _Nios2_Thread_dispatch_disabled
.extern _Per_CPU_Information
.globl _CPU_Context_switch
.globl _CPU_Context_restore
_CPU_Context_switch:
ldw r9, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
ldw r9, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
rdctl r8, status
stw r16, NIOS2_CONTEXT_OFFSET_R16(r4)
stw r17, NIOS2_CONTEXT_OFFSET_R17(r4)
@@ -39,11 +39,11 @@ _CPU_Context_switch:
stw r8, NIOS2_CONTEXT_OFFSET_STATUS(r4)
stw sp, NIOS2_CONTEXT_OFFSET_SP(r4)
stw ra, NIOS2_CONTEXT_OFFSET_RA(r4)
stw r9, NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED(r4)
stw r9, NIOS2_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r4)
restore:
ldw r10, NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED(r5)
ldw r10, NIOS2_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE(r5)
ldw r16, NIOS2_CONTEXT_OFFSET_R16(r5)
ldw r17, NIOS2_CONTEXT_OFFSET_R17(r5)
ldw r18, NIOS2_CONTEXT_OFFSET_R18(r5)
@@ -53,7 +53,7 @@ restore:
ldw r22, NIOS2_CONTEXT_OFFSET_R22(r5)
ldw r23, NIOS2_CONTEXT_OFFSET_R23(r5)
ldw fp, NIOS2_CONTEXT_OFFSET_FP(r5)
stw r10, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
stw r10, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
ldw r11, NIOS2_CONTEXT_OFFSET_STATUS(r5)
ldw sp, NIOS2_CONTEXT_OFFSET_SP(r5)
ldw ra, NIOS2_CONTEXT_OFFSET_RA(r5)

15
cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
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@@ -41,7 +41,6 @@
.section .text
.extern _Per_CPU_Information
.extern _Nios2_Thread_dispatch_disabled
.extern _Nios2_ISR_Status_interrupts_disabled
.globl _Nios2_ISR_Dispatch_with_shadow_non_preemptive
@@ -65,8 +64,8 @@ _Nios2_ISR_Dispatch_with_shadow_non_preemptive:
/* Load thread dispatch necessary */
ldb r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp)
/* Load Nios II specific thread dispatch disabled */
ldw r13, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
/* Load thread dispatch after ISR disable indicator */
ldw r13, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
/* Read status */
rdctl r14, status
@@ -92,14 +91,14 @@ _Nios2_ISR_Dispatch_with_shadow_non_preemptive:
andhi r14, r14, 0x3f
bne r14, zero, no_thread_dispatch
/* Is Nios II specific thread dispatch allowed? */
/* Is thread dispatch after ISR allowed? */
bne r13, zero, no_thread_dispatch
/* Obtain stack frame in normal register set */
rdprs r15, sp, -FRAME_SIZE
/* Disable Nios II specific thread dispatch */
stw r12, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
/* Disable thread dispatch after ISR */
stw r12, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
/* Save context */
stw sstatus, FRAME_OFFSET_STATUS(r15)
@@ -184,8 +183,8 @@ do_thread_dispatch:
/* Is thread dispatch necessary? */
bne r13, zero, enable_interrupts_before_thread_dispatch
/* Enable Nios II specific thread dispatch */
stw zero, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
/* Enable thread dispatch after ISR */
stw zero, %gprel(_Per_CPU_Information + PER_CPU_ISR_DISPATCH_DISABLE)(gp)
/* Restore remaining volatile register */
ldw r13, FRAME_OFFSET_R13(sp)

4
cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c
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@@ -43,8 +43,6 @@ NIOS2_ASSERT_OFFSET(fp, FP);
NIOS2_ASSERT_OFFSET(status, STATUS);
NIOS2_ASSERT_OFFSET(sp, SP);
NIOS2_ASSERT_OFFSET(ra, RA);
NIOS2_ASSERT_OFFSET(thread_dispatch_disabled, THREAD_DISPATCH_DISABLED);
NIOS2_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
NIOS2_ASSERT_OFFSET(stack_mpubase, STACK_MPUBASE);
NIOS2_ASSERT_OFFSET(stack_mpuacc, STACK_MPUACC);
uint32_t _Nios2_Thread_dispatch_disabled;