bsps: Move interrupt controller support to bsps

This patch is a part of the BSP source reorganization.

Update #3285.
This commit is contained in:
Sebastian Huber
2018-04-23 09:50:39 +02:00
parent 276afd2b48
commit 8f8ccee0d9
116 changed files with 95 additions and 95 deletions

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/*
* Copyright (c) 2011-2012 Sebastian Huber. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <string.h>
#include <rtems/score/armv7m.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/linker-symbols.h>
#include <bsp/armv7m-irq.h>
#ifdef ARM_MULTILIB_ARCH_V7M
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
_ARMV7M_NVIC_Set_enable((int) vector);
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
{
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
_ARMV7M_NVIC_Clear_enable((int) vector);
}
rtems_status_code bsp_interrupt_facility_initialize(void)
{
int i;
ARMV7M_Exception_handler *vector_table =
(ARMV7M_Exception_handler *) bsp_vector_table_begin;
if (bsp_vector_table_begin != bsp_start_vector_table_begin) {
memcpy(
vector_table,
bsp_start_vector_table_begin,
(size_t) bsp_vector_table_size
);
}
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR | ARMV7M_SCB_ICSR_PENDSTCLR;
for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
vector_table [ARMV7M_VECTOR_IRQ(i)] = _ARMV7M_NVIC_Interrupt_dispatch;
_ARMV7M_NVIC_Clear_enable(i);
_ARMV7M_NVIC_Clear_pending(i);
_ARMV7M_NVIC_Set_priority(i, BSP_ARMV7M_IRQ_PRIORITY_DEFAULT);
}
_ARMV7M_SCB->vtor = vector_table;
return RTEMS_SUCCESSFUL;
}
#endif /* ARM_MULTILIB_ARCH_V7M */

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/*
* Copyright (c) 2011-2012 Sebastian Huber. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/armv7m.h>
#include <bsp/irq-generic.h>
#include <bsp/armv7m-irq.h>
#ifdef ARM_MULTILIB_ARCH_V7M
void _ARMV7M_NVIC_Interrupt_dispatch(void)
{
rtems_vector_number vector =
ARMV7M_SCB_ICSR_VECTACTIVE_GET(_ARMV7M_SCB->icsr);
_ARMV7M_Interrupt_service_enter();
bsp_interrupt_handler_dispatch(ARMV7M_IRQ_OF_VECTOR(vector));
_ARMV7M_Interrupt_service_leave();
}
#endif /* ARM_MULTILIB_ARCH_V7M */

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/*
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <info@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp/arm-gic.h>
#include <rtems/score/armv4.h>
#include <libcpu/arm-cp15.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
#define PRIORITY_DEFAULT 127
void bsp_interrupt_dispatch(void)
{
volatile gic_cpuif *cpuif = GIC_CPUIF;
uint32_t icciar = cpuif->icciar;
rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
rtems_vector_number spurious = 1023;
if (vector != spurious) {
uint32_t psr = _ARMV4_Status_irq_enable();
bsp_interrupt_handler_dispatch(vector);
_ARMV4_Status_restore(psr);
cpuif->icceoir = icciar;
}
}
void bsp_interrupt_vector_enable(rtems_vector_number vector)
{
volatile gic_dist *dist = ARM_GIC_DIST;
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
gic_id_enable(dist, vector);
}
void bsp_interrupt_vector_disable(rtems_vector_number vector)
{
volatile gic_dist *dist = ARM_GIC_DIST;
bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
gic_id_disable(dist, vector);
}
static inline uint32_t get_id_count(volatile gic_dist *dist)
{
uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
id_count = 32 * (id_count + 1);
id_count = id_count <= 1020 ? id_count : 1020;
return id_count;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
{
volatile gic_cpuif *cpuif = GIC_CPUIF;
volatile gic_dist *dist = ARM_GIC_DIST;
uint32_t id_count = get_id_count(dist);
uint32_t id;
arm_cp15_set_exception_handler(
ARM_EXCEPTION_IRQ,
_ARMV4_Exception_interrupt
);
for (id = 0; id < id_count; id += 32) {
dist->icdicer[id / 32] = 0xffffffff;
}
for (id = 0; id < id_count; ++id) {
gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
}
for (id = 32; id < id_count; ++id) {
gic_id_set_targets(dist, id, 0x01);
}
cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
dist->icddcr = GIC_DIST_ICDDCR_ENABLE;
return RTEMS_SUCCESSFUL;
}
#ifdef RTEMS_SMP
BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
{
volatile gic_cpuif *cpuif = GIC_CPUIF;
volatile gic_dist *dist = ARM_GIC_DIST;
while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
/* Wait */
}
cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
}
#endif
rtems_status_code arm_gic_irq_set_priority(
rtems_vector_number vector,
uint8_t priority
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (bsp_interrupt_is_valid_vector(vector)) {
volatile gic_dist *dist = ARM_GIC_DIST;
gic_id_set_priority(dist, vector, priority);
} else {
sc = RTEMS_INVALID_ID;
}
return sc;
}
rtems_status_code arm_gic_irq_get_priority(
rtems_vector_number vector,
uint8_t *priority
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (bsp_interrupt_is_valid_vector(vector)) {
volatile gic_dist *dist = ARM_GIC_DIST;
*priority = gic_id_get_priority(dist, vector);
} else {
sc = RTEMS_INVALID_ID;
}
return sc;
}
void bsp_interrupt_set_affinity(
rtems_vector_number vector,
const Processor_mask *affinity
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
gic_id_set_targets(dist, vector, targets);
}
void bsp_interrupt_get_affinity(
rtems_vector_number vector,
Processor_mask *affinity
)
{
volatile gic_dist *dist = ARM_GIC_DIST;
uint8_t targets = gic_id_get_targets(dist, vector);
_Processor_mask_From_uint32_t(affinity, targets, 0);
}