forked from Imagelibrary/rtems
bsps: Move interrupt controller support to bsps
This patch is a part of the BSP source reorganization. Update #3285.
This commit is contained in:
67
bsps/arm/shared/irq/irq-armv7m.c
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67
bsps/arm/shared/irq/irq-armv7m.c
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/*
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* Copyright (c) 2011-2012 Sebastian Huber. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <string.h>
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#include <rtems/score/armv7m.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <bsp/linker-symbols.h>
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#include <bsp/armv7m-irq.h>
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#ifdef ARM_MULTILIB_ARCH_V7M
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void bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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_ARMV7M_NVIC_Set_enable((int) vector);
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}
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void bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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_ARMV7M_NVIC_Clear_enable((int) vector);
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}
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rtems_status_code bsp_interrupt_facility_initialize(void)
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{
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int i;
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ARMV7M_Exception_handler *vector_table =
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(ARMV7M_Exception_handler *) bsp_vector_table_begin;
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if (bsp_vector_table_begin != bsp_start_vector_table_begin) {
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memcpy(
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vector_table,
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bsp_start_vector_table_begin,
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(size_t) bsp_vector_table_size
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);
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}
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_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR | ARMV7M_SCB_ICSR_PENDSTCLR;
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for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
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vector_table [ARMV7M_VECTOR_IRQ(i)] = _ARMV7M_NVIC_Interrupt_dispatch;
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_ARMV7M_NVIC_Clear_enable(i);
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_ARMV7M_NVIC_Clear_pending(i);
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_ARMV7M_NVIC_Set_priority(i, BSP_ARMV7M_IRQ_PRIORITY_DEFAULT);
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}
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_ARMV7M_SCB->vtor = vector_table;
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return RTEMS_SUCCESSFUL;
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}
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#endif /* ARM_MULTILIB_ARCH_V7M */
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32
bsps/arm/shared/irq/irq-dispatch-armv7m.c
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32
bsps/arm/shared/irq/irq-dispatch-armv7m.c
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@@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2011-2012 Sebastian Huber. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/score/armv7m.h>
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#include <bsp/irq-generic.h>
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#include <bsp/armv7m-irq.h>
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#ifdef ARM_MULTILIB_ARCH_V7M
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void _ARMV7M_NVIC_Interrupt_dispatch(void)
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{
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rtems_vector_number vector =
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ARMV7M_SCB_ICSR_VECTACTIVE_GET(_ARMV7M_SCB->icsr);
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_ARMV7M_Interrupt_service_enter();
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bsp_interrupt_handler_dispatch(ARMV7M_IRQ_OF_VECTOR(vector));
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_ARMV7M_Interrupt_service_leave();
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}
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#endif /* ARM_MULTILIB_ARCH_V7M */
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180
bsps/arm/shared/irq/irq-gic.c
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180
bsps/arm/shared/irq/irq-gic.c
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/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp/arm-gic.h>
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#include <rtems/score/armv4.h>
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#include <libcpu/arm-cp15.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <bsp/start.h>
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#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
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#define PRIORITY_DEFAULT 127
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void bsp_interrupt_dispatch(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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uint32_t icciar = cpuif->icciar;
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rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
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rtems_vector_number spurious = 1023;
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if (vector != spurious) {
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uint32_t psr = _ARMV4_Status_irq_enable();
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bsp_interrupt_handler_dispatch(vector);
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_ARMV4_Status_restore(psr);
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cpuif->icceoir = icciar;
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}
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}
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void bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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gic_id_enable(dist, vector);
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}
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void bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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gic_id_disable(dist, vector);
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}
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static inline uint32_t get_id_count(volatile gic_dist *dist)
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{
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uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
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id_count = 32 * (id_count + 1);
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id_count = id_count <= 1020 ? id_count : 1020;
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return id_count;
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}
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rtems_status_code bsp_interrupt_facility_initialize(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint32_t id_count = get_id_count(dist);
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uint32_t id;
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arm_cp15_set_exception_handler(
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ARM_EXCEPTION_IRQ,
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_ARMV4_Exception_interrupt
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);
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for (id = 0; id < id_count; id += 32) {
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dist->icdicer[id / 32] = 0xffffffff;
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}
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for (id = 0; id < id_count; ++id) {
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gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
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}
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for (id = 32; id < id_count; ++id) {
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gic_id_set_targets(dist, id, 0x01);
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}
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cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
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cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
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cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
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dist->icddcr = GIC_DIST_ICDDCR_ENABLE;
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return RTEMS_SUCCESSFUL;
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}
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#ifdef RTEMS_SMP
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BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
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{
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volatile gic_cpuif *cpuif = GIC_CPUIF;
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volatile gic_dist *dist = ARM_GIC_DIST;
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while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
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/* Wait */
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}
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cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
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cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
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cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
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}
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#endif
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rtems_status_code arm_gic_irq_set_priority(
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rtems_vector_number vector,
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uint8_t priority
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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gic_id_set_priority(dist, vector, priority);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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rtems_status_code arm_gic_irq_get_priority(
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rtems_vector_number vector,
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uint8_t *priority
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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volatile gic_dist *dist = ARM_GIC_DIST;
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*priority = gic_id_get_priority(dist, vector);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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void bsp_interrupt_set_affinity(
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rtems_vector_number vector,
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const Processor_mask *affinity
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)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint8_t targets = (uint8_t) _Processor_mask_To_uint32_t(affinity, 0);
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gic_id_set_targets(dist, vector, targets);
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}
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void bsp_interrupt_get_affinity(
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rtems_vector_number vector,
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Processor_mask *affinity
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)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint8_t targets = gic_id_get_targets(dist, vector);
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_Processor_mask_From_uint32_t(affinity, targets, 0);
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}
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