forked from Imagelibrary/rtems
bsp/genmcf548x: Add initial values for INTC_ICRn
According to the manual the application must use unique and non-overlapping level and priority definitions for enabled interrupts.
This commit is contained in:
@@ -55,6 +55,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
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libbsp_a_SOURCES += ../../shared/src/irq-server.c
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libbsp_a_SOURCES += ../../shared/src/irq-shell.c
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libbsp_a_SOURCES += irq/irq.c
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libbsp_a_SOURCES += irq/intc-icr-init-values.c
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if HAS_NETWORKING
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network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
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@@ -90,8 +90,6 @@
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#define Clock_driver_support_initialize_hardware() \
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do { \
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int level; \
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MCF548X_INTC_ICR54 = MCF548X_INTC_ICRn_IL(SLT0_IRQ_LEVEL) | \
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MCF548X_INTC_ICRn_IP(SLT0_IRQ_PRIORITY); \
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rtems_interrupt_disable( level ); \
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MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK54); \
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rtems_interrupt_enable( level ); \
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@@ -487,26 +487,18 @@ IntUartInitialize(void)
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rtems_interrupt_disable(level);
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switch(chan) {
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case 0:
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MCF548X_INTC_ICR35 = MCF548X_INTC_ICRn_IL(PSC0_IRQ_LEVEL) |
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MCF548X_INTC_ICRn_IP(PSC0_IRQ_PRIORITY);
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MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK35);
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break;
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case 1:
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MCF548X_INTC_ICR34 = MCF548X_INTC_ICRn_IL(PSC1_IRQ_LEVEL) |
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MCF548X_INTC_ICRn_IP(PSC1_IRQ_PRIORITY);
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MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK34);
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break;
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case 2:
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MCF548X_INTC_ICR33 = MCF548X_INTC_ICRn_IL(PSC2_IRQ_LEVEL) |
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MCF548X_INTC_ICRn_IP(PSC2_IRQ_PRIORITY);
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MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK33);
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break;
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case 3:
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MCF548X_INTC_ICR32 = MCF548X_INTC_ICRn_IL(PSC3_IRQ_LEVEL) |
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MCF548X_INTC_ICRn_IP(PSC3_IRQ_PRIORITY);
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MCF548X_INTC_IMRH &= ~(MCF548X_INTC_IMRH_INT_MASK32);
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break;
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}
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@@ -86,24 +86,8 @@ rtems_isr_entry set_vector(
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int type
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);
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/*
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* Interrupt assignments
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* Highest-priority listed first
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*/
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#define SLT0_IRQ_LEVEL 4
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#define SLT0_IRQ_PRIORITY 0
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#define PSC0_IRQ_LEVEL 3
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#define PSC0_IRQ_PRIORITY 7
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#define PSC1_IRQ_LEVEL 3
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#define PSC1_IRQ_PRIORITY 6
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#define PSC2_IRQ_LEVEL 3
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#define PSC2_IRQ_PRIORITY 5
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#define PSC3_IRQ_LEVEL 3
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#define PSC3_IRQ_PRIORITY 4
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#define FEC_IRQ_LEVEL 2
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#define FEC_IRQ_PRIORITY 3
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/* Initial values for the interrupt level and priority registers (INTC_ICRn) */
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extern const uint8_t mcf548x_intc_icr_init_values[64];
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/*
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* Network driver configuration
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29
c/src/lib/libbsp/m68k/genmcf548x/irq/intc-icr-init-values.c
Normal file
29
c/src/lib/libbsp/m68k/genmcf548x/irq/intc-icr-init-values.c
Normal file
@@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#include <bsp.h>
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#include <bsp/irq.h>
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#define ICR(lvl, prio) (MCF548X_INTC_ICRn_IL(lvl) | MCF548X_INTC_ICRn_IP(prio))
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const uint8_t mcf548x_intc_icr_init_values[64] = {
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[MCF548X_IRQ_SLT0] = ICR(4, 7),
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[MCF548X_IRQ_SLT1] = ICR(4, 6),
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[MCF548X_IRQ_PSC0] = ICR(3, 7),
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[MCF548X_IRQ_PSC1] = ICR(3, 6),
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[MCF548X_IRQ_PSC2] = ICR(3, 5),
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[MCF548X_IRQ_PSC3] = ICR(3, 4),
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[MCF548X_IRQ_FEC0] = ICR(2, 7),
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[MCF548X_IRQ_FEC1] = ICR(2, 6)
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};
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@@ -1288,10 +1288,6 @@ static void mcf548x_fec_init(void *arg)
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rtems_panic ("Can't attach MFC54xx FEX interrupt handler\n");
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}
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MCF548X_INTC_ICRn(MCF548X_FEC_IRQ_VECTOR(chan) % 64) =
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MCF548X_INTC_ICRn_IL(FEC_IRQ_LEVEL) |
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MCF548X_INTC_ICRn_IP(FEC_IRQ_PRIORITY);
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MCF548X_INTC_IMRH &= ~(1 << (MCF548X_FEC_IRQ_VECTOR(chan) % 32));
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MCF548X_FEC_EIMR(chan) = FEC_INTR_MASK_USED;
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@@ -78,6 +78,8 @@ void mcf548x_init(void);
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void mcf548x_init(void)
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{
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size_t i;
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#if defined(HAS_LOW_LEVEL_INIT)
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/* set XLB arbiter timeouts */
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MCF548X_XLB_ADRTO = 0x00000100;
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@@ -108,6 +110,12 @@ void mcf548x_init(void)
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/* Zero uninitialized data */
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memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
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for (i = 8; i < RTEMS_ARRAY_SIZE(mcf548x_intc_icr_init_values); ++i) {
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volatile uint8_t *icr = &MCF548X_INTC_ICR0;
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icr[i] = mcf548x_intc_icr_init_values[i];
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}
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}
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/********************************************************************/
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#if defined(HAS_LOW_LEVEL_INIT)
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