forked from Imagelibrary/rtems
bsp/atsam: Add support for TCM
This commit is contained in:
committed by
Sebastian Huber
parent
9bb3ce3918
commit
891fa3eb5b
@@ -59,6 +59,34 @@ typedef struct {
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uint8_t phy_addr;
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} if_atsam_config;
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extern char atsam_memory_dtcm_begin[];
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extern char atsam_memory_dtcm_end[];
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extern char atsam_memory_dtcm_size[];
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extern char atsam_memory_intflash_begin[];
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extern char atsam_memory_intflash_end[];
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extern char atsam_memory_intflash_size[];
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extern char atsam_memory_intsram_begin[];
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extern char atsam_memory_intsram_end[];
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extern char atsam_memory_intsram_size[];
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extern char atsam_memory_itcm_begin[];
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extern char atsam_memory_itcm_end[];
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extern char atsam_memory_itcm_size[];
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extern char atsam_memory_nocache_begin[];
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extern char atsam_memory_nocache_end[];
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extern char atsam_memory_nocache_size[];
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extern char atsam_memory_qspiflash_begin[];
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extern char atsam_memory_qspiflash_end[];
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extern char atsam_memory_qspiflash_size[];
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extern char atsam_memory_sdram_begin[];
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extern char atsam_memory_sdram_end[];
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extern char atsam_memory_sdram_size[];
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/** @} */
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#ifdef __cplusplus
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@@ -168,6 +168,7 @@ void _SetupMemoryRegion(void)
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START_Addr:- 0x20440000UL
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END_Addr:- 0x2045FFFFUL
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******************************************************/
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#ifndef __rtems__
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/* SRAM memory region */
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dwRegionBaseAddr =
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SRAM_SECOND_START_ADDRESS |
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@@ -181,6 +182,7 @@ void _SetupMemoryRegion(void)
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MPU_REGION_ENABLE;
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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#endif /* __rtems__ */
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#ifdef MPU_HAS_NOCACHE_REGION
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dwRegionBaseAddr =
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@@ -29,6 +29,9 @@
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#ifndef _MPU_H_
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#define _MPU_H_
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#ifdef __rtems__
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#include <bsp.h>
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#endif /* __rtems__ */
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/*----------------------------------------------------------------------------
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* Definitions
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@@ -125,17 +128,29 @@
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#endif
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/* Regions should be a 2^(N+1) where 4 < N < 31 */
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#ifdef __rtems__
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#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
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#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
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#else /* __rtems__ */
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#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
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#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
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#endif /* __rtems__ */
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#if defined MPU_HAS_NOCACHE_REGION
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#ifdef __rtems__
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#define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
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#define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
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#else /* __rtems__ */
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#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
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#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
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#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
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#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
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#endif /* __rtems__ */
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#else
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#ifndef __rtems__
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#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
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#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
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#endif /* __rtems__ */
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#endif
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/************** Peripherals memory region macros ********/
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#define PERIPHERALS_START_ADDRESS 0x40000000UL
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@@ -20,8 +20,60 @@
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#include <include/board_lowlevel.h>
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#include <include/board_memories.h>
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#define SIZE_0K 0
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#define SIZE_32K (32 * 1024)
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#define SIZE_64K (64 * 1024)
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#define SIZE_128K (128 * 1024)
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#define ITCMCR_SZ_0K 0x0
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#define ITCMCR_SZ_32K 0x6
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#define ITCMCR_SZ_64K 0x7
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#define ITCMCR_SZ_128K 0x8
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static BSP_START_TEXT_SECTION void efc_send_command(uint32_t eefc)
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{
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EFC->EEFC_FCR = eefc | EEFC_FCR_FKEY_PASSWD;
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}
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static BSP_START_TEXT_SECTION void tcm_enable(void)
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{
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SCB->ITCMCR |= SCB_ITCMCR_EN_Msk;
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SCB->DTCMCR |= SCB_DTCMCR_EN_Msk;
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}
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static BSP_START_TEXT_SECTION void tcm_disable(void)
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{
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SCB->ITCMCR &= ~SCB_ITCMCR_EN_Msk;
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SCB->DTCMCR &= ~SCB_DTCMCR_EN_Msk;
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}
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static BSP_START_TEXT_SECTION bool tcm_setup_and_check_if_do_efc_config(
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uintptr_t tcm_size,
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uint32_t itcmcr_sz
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)
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{
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if (tcm_size == SIZE_0K && itcmcr_sz == ITCMCR_SZ_0K) {
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tcm_disable();
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return false;
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} else if (tcm_size == SIZE_32K && itcmcr_sz == ITCMCR_SZ_32K) {
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tcm_enable();
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return false;
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} else if (tcm_size == SIZE_64K && itcmcr_sz == ITCMCR_SZ_64K) {
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tcm_enable();
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return false;
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} else if (tcm_size == SIZE_128K && itcmcr_sz == ITCMCR_SZ_128K) {
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tcm_enable();
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return false;
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} else {
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return true;
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}
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}
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void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
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{
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uintptr_t tcm_size;
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uint32_t itcmcr_sz;
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system_init_flash(BOARD_MCK);
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SystemInit();
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@@ -41,6 +93,31 @@ void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
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}
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_SetupMemoryRegion();
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/* Configure tightly coupled memory interfaces */
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tcm_size = (uintptr_t) atsam_memory_itcm_size;
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itcmcr_sz = (SCB->ITCMCR & SCB_ITCMCR_SZ_Msk) >> SCB_ITCMCR_SZ_Pos;
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if (tcm_setup_and_check_if_do_efc_config(tcm_size, itcmcr_sz)) {
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if (tcm_size == SIZE_128K) {
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efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
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efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
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tcm_enable();
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} else if (tcm_size == SIZE_64K) {
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efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
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efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
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tcm_enable();
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} else if (tcm_size == SIZE_32K) {
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efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
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efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
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tcm_enable();
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} else {
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efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
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efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
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tcm_disable();
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}
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}
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}
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void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
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@@ -7,3 +7,31 @@ MEMORY {
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SDRAM : ORIGIN = 0x70000000, LENGTH = @ATSAM_MEMORY_SDRAM_SIZE@
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QSPIFLASH : ORIGIN = 0x80000000, LENGTH = @ATSAM_MEMORY_QSPIFLASH_SIZE@
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}
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atsam_memory_itcm_begin = ORIGIN (ITCM);
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atsam_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM);
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atsam_memory_itcm_size = LENGTH (ITCM);
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atsam_memory_intflash_begin = ORIGIN (INTFLASH);
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atsam_memory_intflash_end = ORIGIN (INTFLASH) + LENGTH (INTFLASH);
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atsam_memory_intflash_size = LENGTH (INTFLASH);
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atsam_memory_dtcm_begin = ORIGIN (DTCM);
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atsam_memory_dtcm_end = ORIGIN (DTCM) + LENGTH (DTCM);
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atsam_memory_dtcm_size = LENGTH (DTCM);
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atsam_memory_intsram_begin = ORIGIN (INTSRAM);
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atsam_memory_intsram_end = ORIGIN (INTSRAM) + LENGTH (INTSRAM);
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atsam_memory_intsram_size = LENGTH (INTSRAM);
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atsam_memory_nocache_begin = ORIGIN (NOCACHE);
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atsam_memory_nocache_end = ORIGIN (NOCACHE) + LENGTH (NOCACHE);
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atsam_memory_nocache_size = LENGTH (NOCACHE);
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atsam_memory_sdram_begin = ORIGIN (SDRAM);
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atsam_memory_sdram_end = ORIGIN (SDRAM) + LENGTH (SDRAM);
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atsam_memory_sdram_size = LENGTH (SDRAM);
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atsam_memory_qspiflash_begin = ORIGIN (QSPIFLASH);
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atsam_memory_qspiflash_end = ORIGIN (QSPIFLASH) + LENGTH (QSPIFLASH);
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atsam_memory_qspiflash_size = LENGTH (QSPIFLASH);
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