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2002-11-13 Jay Monkman <jtm@smoothsmoothie.com>

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* intr_NOTIMES.t: Real version submitted.
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Joel Sherrill
2002-11-13 16:58:09 +00:00
parent dd1ad07b2c
commit 87b721f5ed
2 changed files with 60 additions and 130 deletions
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doc/supplements/arm/ChangeLog
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@@ -1,3 +1,7 @@
2002-11-13 Jay Monkman <jtm@smoothsmoothie.com>
* intr_NOTIMES.t: Real version submitted.
2002-10-24 Joel Sherrill <joel@OARcorp.com> 2002-10-24 Joel Sherrill <joel@OARcorp.com>
* stamp-vti, version.texi: Regenerated. * stamp-vti, version.texi: Regenerated.

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doc/supplements/arm/intr_NOTIMES.t
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@@ -23,140 +23,74 @@ special control mechanisms to return to the normal processing
stream. Although RTEMS hides many of the processor dependent stream. Although RTEMS hides many of the processor dependent
details of interrupt processing, it is important to understand details of interrupt processing, it is important to understand
how the RTEMS interrupt manager is mapped onto the processor's how the RTEMS interrupt manager is mapped onto the processor's
unique architecture. Discussed in this chapter are the XXX's unique architecture. Discussed in this chapter are the ARM's
interrupt response and control mechanisms as they pertain to interrupt response and control mechanisms as they pertain to
RTEMS. RTEMS.
The ARM has 7 exception types:
@itemize @bullet
@item Reset
@item Undefined instruction
@item Software interrupt (SWI)
@item Prefetch Abort
@item Data Abort
@item Interrupt (IRQ)
@item Fast Interrupt (FIQ)
@end itemize
Of these types, only IRQ and FIQ are handled through RTEMS's interrupt
vectoring.
@section Vectoring of an Interrupt Handler @section Vectoring of an Interrupt Handler
Depending on whether or not the particular CPU
supports a separate interrupt stack, the XXX family has two
different interrupt handling models.
@subsection Models Without Separate Interrupt Stacks Unlike many other architectures, the ARM has seperate stacks for each
interrupt. When the CPU receives an interrupt, it:
Upon receipt of an interrupt the XXX family
members without separate interrupt stacks automatically perform
the following actions:
@itemize @bullet @itemize @bullet
@item To Be Written @item switches to the exception mode corresponding to the interrupt,
@item saves the Current Processor Status Register (CPSR) to the
exception mode's Saved Processor Status Register (SPSR),
@item masks off the IRQ and if the interrupt source was FIQ, the FIQ
is masked off as well,
@item saves the Program Counter (PC) to the exception mode's Link
Register (LR - same as R14),
@item and sets the PC to the exception's vector address.
@end itemize @end itemize
@subsection Models With Separate Interrupt Stacks The vectors for both IRQ and FIQ point to the _ISR_Handler function.
_ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before
Upon receipt of an interrupt the XXX family calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so
members with separate interrupt stacks automatically perform the that it is safe to call C functions. Even ExecuteITHandler() can be written
following actions: in C.
@itemize @bullet
@item saves the current status register (SR),
@item clears the master/interrupt (M) bit of the SR to
indicate the switch from master state to interrupt state,
@item sets the privilege mode to supervisor,
@item suppresses tracing,
@item sets the interrupt mask level equal to the level of the
interrupt being serviced,
@item pushes an interrupt stack frame (ISF), which includes
the program counter (PC), the status register (SR), and the
format/exception vector offset (FVO) word, onto the supervisor
and interrupt stacks,
@item switches the current stack to the interrupt stack and
vectors to an interrupt service routine (ISR). If the ISR was
installed with the interrupt_catch directive, then the RTEMS
interrupt handler will begin execution. The RTEMS interrupt
handler saves all registers which are not preserved according to
the calling conventions and invokes the application's ISR.
@end itemize
A nested interrupt is processed similarly by these
CPU models with the exception that only a single ISF is placed
on the interrupt stack and the current stack need not be
switched.
The FVO word in the Interrupt Stack Frame is examined
by RTEMS to determine when an outer most interrupt is being
exited. Since the FVO is used by RTEMS for this purpose, the
user application code MUST NOT modify this field.
The following shows the Interrupt Stack Frame for
XXX CPU models with separate interrupt stacks:
@ifset use-ascii
@example
@group
+----------------------+
| Status Register | 0x0
+----------------------+
| Program Counter High | 0x2
+----------------------+
| Program Counter Low | 0x4
+----------------------+
| Format/Vector Offset | 0x6
+----------------------+
@end group
@end example
@end ifset
@ifset use-tex
@sp 1
@tex
\centerline{\vbox{\offinterlineskip\halign{
\strut\vrule#&
\hbox to 2.00in{\enskip\hfil#\hfil}&
\vrule#&
\hbox to 0.50in{\enskip\hfil#\hfil}
\cr
\multispan{3}\hrulefill\cr
& Status Register && 0x0\cr
\multispan{3}\hrulefill\cr
& Program Counter High && 0x2\cr
\multispan{3}\hrulefill\cr
& Program Counter Low && 0x4\cr
\multispan{3}\hrulefill\cr
& Format/Vector Offset && 0x6\cr
\multispan{3}\hrulefill\cr
}}\hfil}
@end tex
@end ifset
@ifset use-html
@html
<CENTER>
<TABLE COLS=2 WIDTH="40%" BORDER=2>
<TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD>
<TD ALIGN=center>0x0</TD></TR>
<TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD>
<TD ALIGN=center>0x2</TD></TR>
<TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD>
<TD ALIGN=center>0x4</TD></TR>
<TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD>
<TD ALIGN=center>0x6</TD></TR>
</TABLE>
</CENTER>
@end html
@end ifset
@section Interrupt Levels @section Interrupt Levels
Eight levels (0-7) of interrupt priorities are The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ
supported by XXX family members with level seven (7) being has a higher priority than IRQ, and has its own version of register R8 - R14,
the highest priority. Level zero (0) indicates that interrupts however RTEMS does not take advantage of them. Both interrupts are enabled
are fully enabled. Interrupt requests for interrupts with through the CPSR.
priorities less than or equal to the current interrupt mask
level are ignored. The RTEMS interrupt level mapping scheme for the AEM is not a numeric level
as on most RTEMS ports. It is a bit mapping that corresponds the enable
bits's postions in the CPSR:
@table @b
@item FIQ
Setting bit 6 (0 is least significant bit) disables the FIQ.
@item IRQ
Setting bit 7 (0 is least significant bit) disables the IRQ.
@end table
Although RTEMS supports 256 interrupt levels, the
XXX family only supports eight. RTEMS interrupt levels 0
through 7 directly correspond to XXX interrupt levels. All
other RTEMS interrupt levels are undefined and their behavior is
unpredictable.
@section Disabling of Interrupts by RTEMS @section Disabling of Interrupts by RTEMS
@@ -183,14 +117,6 @@ execute as non-maskable interrupts.
@section Interrupt Stack @section Interrupt Stack
RTEMS allocates the interrupt stack from the RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory
Workspace Area. The amount of memory allocated for the for the stacks is reserved in the linker script.
interrupt stack is determined by the interrupt_stack_size field
in the CPU Configuration Table. During the initialization
process, RTEMS will install its interrupt stack.
The XXX port of RTEMS supports a software managed
dedicated interrupt stack on those CPU models which do not
support a separate interrupt stack in hardware.