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bsps/aarch64: Homogenize ZynqMP ECC info structs

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This fixes the ECC info struct naming such that they all use the _Info
suffix. This also adds comments describing which structures are paired
with which event types.
This commit is contained in:
Kinsey Moore
2024-07-24 15:15:42 -05:00
committed by Chris Johns
parent 5580f70bbd
commit 8611d3d91f
2 changed files with 7 additions and 5 deletions
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4
bsps/aarch64/xilinx-zynqmp/ecc/cache.c
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@@ -85,7 +85,7 @@ static void cache_handler(void *arg)
if (l1val & AARCH64_CPUMERRSR_EL1_VALID) { if (l1val & AARCH64_CPUMERRSR_EL1_VALID) {
/* parse L1 data */ /* parse L1 data */
Cache_Error_Event cerr = {0, }; Cache_Error_Info cerr = {0, };
cerr.abort = l1val & AARCH64_CPUMERRSR_EL1_FATAL; cerr.abort = l1val & AARCH64_CPUMERRSR_EL1_FATAL;
cerr.repeats = AARCH64_CPUMERRSR_EL1_REPEATERR_GET(l1val); cerr.repeats = AARCH64_CPUMERRSR_EL1_REPEATERR_GET(l1val);
cerr.other_errors = AARCH64_CPUMERRSR_EL1_OTHERERR_GET(l1val); cerr.other_errors = AARCH64_CPUMERRSR_EL1_OTHERERR_GET(l1val);
@@ -98,7 +98,7 @@ static void cache_handler(void *arg)
if (l2val & AARCH64_L2MERRSR_EL1_VALID) { if (l2val & AARCH64_L2MERRSR_EL1_VALID) {
/* parse L2 data */ /* parse L2 data */
Cache_Error_Event cerr = {0, }; Cache_Error_Info cerr = {0, };
cerr.abort = l2val & AARCH64_L2MERRSR_EL1_FATAL; cerr.abort = l2val & AARCH64_L2MERRSR_EL1_FATAL;
cerr.repeats = AARCH64_L2MERRSR_EL1_REPEATERR_GET(l2val); cerr.repeats = AARCH64_L2MERRSR_EL1_REPEATERR_GET(l2val);
cerr.other_errors = AARCH64_L2MERRSR_EL1_OTHERERR_GET(l2val); cerr.other_errors = AARCH64_L2MERRSR_EL1_OTHERERR_GET(l2val);

8
bsps/aarch64/xilinx-zynqmp/include/bsp/ecc.h
View File

@@ -55,9 +55,9 @@ extern "C" {
* @brief Enumeration describing the possible types of ECC events * @brief Enumeration describing the possible types of ECC events
*/ */
typedef enum { typedef enum {
/* L1 Cache event information is delivered via Cache_Error_Event struct. */ /* L1 Cache event information is delivered via Cache_Error_Info struct. */
L1_CACHE, L1_CACHE,
/* L2 Cache event information is delivered via Cache_Error_Event struct. */ /* L2 Cache event information is delivered via Cache_Error_Info struct. */
L2_CACHE, L2_CACHE,
/* /*
* L1 and L2 cache are on a combined interrupt on ZynqMP. They are enabled as * L1 and L2 cache are on a combined interrupt on ZynqMP. They are enabled as
@@ -66,7 +66,9 @@ typedef enum {
* both. * both.
*/ */
L1_L2_CACHE, L1_L2_CACHE,
/* OCM RAM event information is delivered via OCM_Error_Info struct. */
OCM_RAM, OCM_RAM,
/* DDR RAM event information is delivered via DDR_Error_Info struct. */
DDR_RAM, DDR_RAM,
} ECC_Event_Type; } ECC_Event_Type;
@@ -106,7 +108,7 @@ typedef struct {
uint8_t other_errors; uint8_t other_errors;
/* Whether any of the errors represented have caused a data abort */ /* Whether any of the errors represented have caused a data abort */
bool abort; bool abort;
} Cache_Error_Event; } Cache_Error_Info;
/** /**
* @brief Typedef for ECC handlers * @brief Typedef for ECC handlers