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New version of this file from Eric Norum.

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This commit is contained in:
Joel Sherrill
1997-10-13 17:38:18 +00:00
parent d9fe8e230a
commit 84ff8b7bf9
1 changed files with 534 additions and 536 deletions
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20
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
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@@ -71,8 +71,7 @@ void _Init68360 (void)
* Step 8: Initialize system protection * Step 8: Initialize system protection
* Enable watchdog * Enable watchdog
* Watchdog causes system reset * Watchdog causes system reset
* Next-to-slowest watchdog timeout * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
* (21 seconds with 25 MHz oscillator)
* Enable double bus fault monitor * Enable double bus fault monitor
* Enable bus monitor for external cycles * Enable bus monitor for external cycles
* 1024 clocks for external timeout * 1024 clocks for external timeout
@@ -218,14 +217,14 @@ void _Init68360 (void)
/* /*
* Step 8: Initialize system protection * Step 8: Initialize system protection
* Disable watchdog FIXME: Should use watchdog!!!! * Enable watchdog
* Watchdog causes system reset * Watchdog causes system reset
* Slowest watchdog timeout * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
* Enable double bus fault monitor * Enable double bus fault monitor
* Enable bus monitor external * Enable bus monitor for external cycles
* 128 clocks for external timeout * 1024 clocks for external timeout
*/ */
m360.sypcr = 0x7F; m360.sypcr = 0xEC;
/* /*
* Step 9: Clear parameter RAM and reset communication processor module * Step 9: Clear parameter RAM and reset communication processor module
@@ -307,7 +306,7 @@ void _Init68360 (void)
/* /*
* Step 14: More system initialization * Step 14: More system initialization
* SDCR (Serial DMA configuration register) * SDCR (Serial DMA configuration register)
* Disable SDMA during FREEZE * Enable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers * Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4 * Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register): * CICR (CPM interrupt configuration register):
@@ -320,7 +319,7 @@ void _Init68360 (void)
* Vector base 128 * Vector base 128
* SCCs priority grouped at top of table * SCCs priority grouped at top of table
*/ */
m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4; m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) | m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128); (4 << 13) | (0x1F << 8) | (128);
@@ -371,8 +370,7 @@ void _Init68360 (void)
* Step 8: Initialize system protection * Step 8: Initialize system protection
* Enable watchdog * Enable watchdog
* Watchdog causes system reset * Watchdog causes system reset
* Next-to-slowest watchdog timeout * Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
* (21 seconds with 25 MHz oscillator)
* Enable double bus fault monitor * Enable double bus fault monitor
* Enable bus monitor for external cycles * Enable bus monitor for external cycles
* 1024 clocks for external timeout * 1024 clocks for external timeout