forked from Imagelibrary/rtems
2006-08-23 Joel Sherrill <joel@OARcorp.com>
* Makefile.am, configure.ac, FAQ/stamp-vti, FAQ/version.texi, common/cpright.texi: Merging CPU Supplements into a single document. As part of this removed the obsolete and impossible to maintain size and timing information. * cpu_supplement/.cvsignore, cpu_supplement/Makefile.am, cpu_supplement/arm.t, cpu_supplement/i386.t, cpu_supplement/m68k.t, cpu_supplement/mips.t, cpu_supplement/powerpc.t, cpu_supplement/preface.texi, cpu_supplement/sh.t, cpu_supplement/sparc.t, cpu_supplement/tic4x.t: New files. * supplements/.cvsignore, supplements/Makefile.am, supplements/supplement.am, supplements/arm/.cvsignore, supplements/arm/BSP_TIMES, supplements/arm/ChangeLog, supplements/arm/Makefile.am, supplements/arm/arm.texi, supplements/arm/bsp.t, supplements/arm/callconv.t, supplements/arm/cpumodel.t, supplements/arm/cputable.t, supplements/arm/fatalerr.t, supplements/arm/intr_NOTIMES.t, supplements/arm/memmodel.t, supplements/arm/preface.texi, supplements/arm/timeBSP.t, supplements/c4x/.cvsignore, supplements/c4x/BSP_TIMES, supplements/c4x/ChangeLog, supplements/c4x/Makefile.am, supplements/c4x/bsp.t, supplements/c4x/c4x.texi, supplements/c4x/callconv.t, supplements/c4x/cpumodel.t, supplements/c4x/cputable.t, supplements/c4x/fatalerr.t, supplements/c4x/intr_NOTIMES.t, supplements/c4x/memmodel.t, supplements/c4x/preface.texi, supplements/c4x/timeBSP.t, supplements/i386/.cvsignore, supplements/i386/ChangeLog, supplements/i386/FORCE386_TIMES, supplements/i386/Makefile.am, supplements/i386/bsp.t, supplements/i386/callconv.t, supplements/i386/cpumodel.t, supplements/i386/cputable.t, supplements/i386/fatalerr.t, supplements/i386/i386.texi, supplements/i386/intr_NOTIMES.t, supplements/i386/memmodel.t, supplements/i386/preface.texi, supplements/i386/timeFORCE386.t, supplements/m68k/.cvsignore, supplements/m68k/ChangeLog, supplements/m68k/MVME136_TIMES, supplements/m68k/Makefile.am, supplements/m68k/bsp.t, supplements/m68k/callconv.t, supplements/m68k/cpumodel.t, supplements/m68k/cputable.t, supplements/m68k/fatalerr.t, supplements/m68k/intr_NOTIMES.t, supplements/m68k/m68k.texi, supplements/m68k/memmodel.t, supplements/m68k/preface.texi, supplements/m68k/timeMVME136.t, supplements/m68k/timedata.t, supplements/mips/.cvsignore, supplements/mips/BSP_TIMES, supplements/mips/ChangeLog, supplements/mips/Makefile.am, supplements/mips/bsp.t, supplements/mips/callconv.t, supplements/mips/cpumodel.t, supplements/mips/cputable.t, supplements/mips/fatalerr.t, supplements/mips/intr_NOTIMES.t, supplements/mips/memmodel.t, supplements/mips/mips.texi, supplements/mips/preface.texi, supplements/mips/timeBSP.t, supplements/powerpc/.cvsignore, supplements/powerpc/ChangeLog, supplements/powerpc/DMV177_TIMES, supplements/powerpc/Makefile.am, supplements/powerpc/PSIM_TIMES, supplements/powerpc/bsp.t, supplements/powerpc/callconv.t, supplements/powerpc/cpumodel.t, supplements/powerpc/cputable.t, supplements/powerpc/fatalerr.t, supplements/powerpc/intr_NOTIMES.t, supplements/powerpc/memmodel.t, supplements/powerpc/powerpc.texi, supplements/powerpc/preface.texi, supplements/powerpc/timeDMV177.t, supplements/powerpc/timePSIM.t, supplements/sh/.cvsignore, supplements/sh/BSP_TIMES, supplements/sh/ChangeLog, supplements/sh/Makefile.am, supplements/sh/bsp.t, supplements/sh/callconv.t, supplements/sh/cpumodel.t, supplements/sh/cputable.t, supplements/sh/fatalerr.t, supplements/sh/intr_NOTIMES.t, supplements/sh/memmodel.t, supplements/sh/preface.texi, supplements/sh/sh.texi, supplements/sh/timeBSP.t, supplements/sparc/.cvsignore, supplements/sparc/ChangeLog, supplements/sparc/ERC32_TIMES, supplements/sparc/Makefile.am, supplements/sparc/bsp.t, supplements/sparc/callconv.t, supplements/sparc/cpumodel.t, supplements/sparc/cputable.t, supplements/sparc/fatalerr.t, supplements/sparc/intr_NOTIMES.t, supplements/sparc/memmodel.t, supplements/sparc/preface.texi, supplements/sparc/sparc.texi, supplements/sparc/timeERC32.t, supplements/template/.cvsignore, supplements/template/BSP_TIMES, supplements/template/ChangeLog, supplements/template/Makefile.am, supplements/template/bsp.t, supplements/template/callconv.t, supplements/template/cpumodel.t, supplements/template/cputable.t, supplements/template/fatalerr.t, supplements/template/intr_NOTIMES.t, supplements/template/memmodel.t, supplements/template/preface.texi, supplements/template/template.texi, supplements/template/timeBSP.t: Removed.
This commit is contained in:
Joel Sherrill
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doc/cpu_supplement/sh.t
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@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@ifinfo
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@end ifinfo
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@chapter SuperH Specific Information
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The Real Time Executive for Multiprocessor Systems (RTEMS)
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is designed to be portable across multiple processor
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architectures. However, the nature of real-time systems makes
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it essential that the application designer understand certain
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processor dependent implementation details. These processor
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dependencies include calling convention, board support package
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issues, interrupt processing, exact RTEMS memory requirements,
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performance data, header files, and the assembly language
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interface to the executive.
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This document discusses the VENDOR XXX
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architecture dependencies in this port of RTEMS. The XXX
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family has a wide variety of CPU models within it. The part
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numbers ...
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XXX fill in some things here
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It is highly recommended that the XXX
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RTEMS application developer obtain and become familiar with the
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documentation for the processor being used as well as the
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documentation for the family as a whole.
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@subheading Architecture Documents
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For information on the XXX architecture,
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refer to the following documents available from VENDOR
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(@file{http//www.XXX.com/}):
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@itemize @bullet
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@item @cite{XXX Family Reference, VENDOR, PART NUMBER}.
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@end itemize
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@subheading MODEL SPECIFIC DOCUMENTS
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For information on specific processor models and
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their associated coprocessors, refer to the following documents:
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@itemize @bullet
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@item @cite{XXX MODEL Manual, VENDOR, PART NUMBER}.
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@item @cite{XXX MODEL Manual, VENDOR, PART NUMBER}.
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@end itemize
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@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@section CPU Model Dependent Features
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Microprocessors are generally classified into
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families with a variety of CPU models or implementations within
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that family. Within a processor family, there is a high level
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of binary compatibility. This family may be based on either an
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architectural specification or on maintaining compatibility with
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a popular processor. Recent microprocessor families such as the
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SPARC or PowerPC are based on an architectural specification
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which is independent or any particular CPU model or
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implementation. Older families such as the M68xxx and the iX86
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evolved as the manufacturer strived to produce higher
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performance processor models which maintained binary
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compatibility with older models.
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RTEMS takes advantage of the similarity of the
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various models within a CPU family. Although the models do vary
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in significant ways, the high level of compatibility makes it
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possible to share the bulk of the CPU dependent executive code
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across the entire family. Each processor family supported by
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RTEMS has a list of features which vary between CPU models
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within a family. For example, the most common model dependent
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feature regardless of CPU family is the presence or absence of a
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floating point unit or coprocessor. When defining the list of
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features present on a particular CPU model, one simply notes
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that floating point hardware is or is not present and defines a
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single constant appropriately. Conditional compilation is
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utilized to include the appropriate source code for this CPU
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model's feature set. It is important to note that this means
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that RTEMS is thus compiled using the appropriate feature set
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and compilation flags optimal for this CPU model used. The
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alternative would be to generate a binary which would execute on
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all family members using only the features which were always
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present.
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This chapter presents the set of features which vary
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across SPARC implementations and are of importance to RTEMS.
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The set of CPU model feature macros are defined in the file
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cpukit/score/cpu/XXX/XXX.h based upon the particular CPU
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model defined on the compilation command line.
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@subsection CPU Model Name
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The macro CPU_MODEL_NAME is a string which designates
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the name of this CPU model. For example, for the MODEL
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processor, this macro is set to the string "XXX".
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@subsection Floating Point Unit
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The macro XXX_HAS_FPU is set to 1 to indicate that
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this CPU model has a hardware floating point unit and 0
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otherwise. It does not matter whether the hardware floating
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point support is incorporated on-chip or is an external
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coprocessor.
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@subsection Another Optional Feature
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The macro XXX
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@c
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@c COPYRIGHT (c) 1988-2002.
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||||
@c On-Line Applications Research Corporation (OAR).
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||||
@c All rights reserved.
|
||||
@c
|
||||
@c $Id$
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||||
@c
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||||
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||||
@section Calling Conventions
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Each high-level language compiler generates
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subroutine entry and exit code based upon a set of rules known
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as the compiler's calling convention. These rules address the
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following issues:
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@itemize @bullet
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@item register preservation and usage
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@item parameter passing
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@item call and return mechanism
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@end itemize
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A compiler's calling convention is of importance when
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interfacing to subroutines written in another language either
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assembly or high-level. Even when the high-level language and
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target processor are the same, different compilers may use
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different calling conventions. As a result, calling conventions
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are both processor and compiler dependent.
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The Hitachi SH architecture supports a simple yet
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effective call and return mechanism. A subroutine is invoked
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via the branch to subroutine (XXX) or the jump to subroutine
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(XXX) instructions. These instructions push the return address
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on the current stack. The return from subroutine (rts)
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instruction pops the return address off the current stack and
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transfers control to that instruction. It is is important to
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note that the MC68xxx call and return mechanism does not
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automatically save or restore any registers. It is the
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responsibility of the high-level language compiler to define the
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register preservation and usage convention.
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@subsection Calling Mechanism
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All RTEMS directives are invoked using either a bsr
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or jsr instruction and return to the user application via the
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rts instruction.
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@subsection Register Usage
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As discussed above, the bsr and jsr instructions do
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not automatically save any registers. RTEMS uses the registers
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D0, D1, A0, and A1 as scratch registers. These registers are
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not preserved by RTEMS directives therefore, the contents of
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these registers should not be assumed upon return from any RTEMS
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directive.
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> > The SH1 has 16 general registers (r0..r15)
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> > r0..r3 used as general volatile registers
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> > r4..r7 used to pass up to 4 arguments to functions, arguments above 4 are
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> > passed via the stack)
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> > r8..13 caller saved registers (i.e. push them to the stack if you need them
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> > inside of a function)
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> > r14 frame pointer
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> > r15 stack pointer
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>
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@subsection Parameter Passing
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RTEMS assumes that arguments are placed on the
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current stack before the directive is invoked via the bsr or jsr
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instruction. The first argument is assumed to be closest to the
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return address on the stack. This means that the first argument
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of the C calling sequence is pushed last. The following
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pseudo-code illustrates the typical sequence used to call a
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RTEMS directive with three (3) arguments:
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@example
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@group
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push third argument
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push second argument
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push first argument
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invoke directive
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remove arguments from the stack
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@end group
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@end example
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The arguments to RTEMS are typically pushed onto the
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stack using a move instruction with a pre-decremented stack
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pointer as the destination. These arguments must be removed
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from the stack after control is returned to the caller. This
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removal is typically accomplished by adding the size of the
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argument list in bytes to the current stack pointer.
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@subsection User-Provided Routines
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All user-provided routines invoked by RTEMS, such as
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user extensions, device drivers, and MPCI routines, must also
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adhere to these calling conventions.
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@c
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||||
@c COPYRIGHT (c) 1988-2002.
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||||
@c On-Line Applications Research Corporation (OAR).
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||||
@c All rights reserved.
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||||
@c
|
||||
@c $Id$
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||||
@c
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||||
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@section Memory Model
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A processor may support any combination of memory
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models ranging from pure physical addressing to complex demand
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paged virtual memory systems. RTEMS supports a flat memory
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model which ranges contiguously over the processor's allowable
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address space. RTEMS does not support segmentation or virtual
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memory of any kind. The appropriate memory model for RTEMS
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provided by the targeted processor and related characteristics
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of that model are described in this chapter.
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@subsection Flat Memory Model
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The XXX family supports a flat 32-bit address
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space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
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gigabytes). Each address is represented by a 32-bit value and
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is byte addressable. The address may be used to reference a
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single byte, word (2-bytes), or long word (4 bytes). Memory
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accesses within this address space are performed in big endian
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fashion by the processors in this family.
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Some of the XXX family members such as the
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XXX, XXX, and XXX support virtual memory and
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segmentation. The XXX requires external hardware support
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such as the XXX Paged Memory Management Unit coprocessor
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which is typically used to perform address translations for
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these systems. RTEMS does not support virtual memory or
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segmentation on any of the XXX family members.
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@c
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@c Interrupt Stack Frame Picture
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@c
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||||
@c COPYRIGHT (c) 1988-2002.
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||||
@c On-Line Applications Research Corporation (OAR).
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||||
@c All rights reserved.
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||||
@c
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||||
@c $Id$
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@c
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||||
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@section Interrupt Processing
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||||
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Different types of processors respond to the
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occurrence of an interrupt in its own unique fashion. In
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addition, each processor type provides a control mechanism to
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allow for the proper handling of an interrupt. The processor
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||||
dependent response to the interrupt modifies the current
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execution state and results in a change in the execution stream.
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Most processors require that an interrupt handler utilize some
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special control mechanisms to return to the normal processing
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stream. Although RTEMS hides many of the processor dependent
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details of interrupt processing, it is important to understand
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how the RTEMS interrupt manager is mapped onto the processor's
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unique architecture. Discussed in this chapter are the SH's
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interrupt response and control mechanisms as they pertain to
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RTEMS.
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@subsection Vectoring of an Interrupt Handler
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||||
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Depending on whether or not the particular CPU
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supports a separate interrupt stack, the SH family has two
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different interrupt handling models.
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||||
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||||
@subsubsection Models Without Separate Interrupt Stacks
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||||
Upon receipt of an interrupt the SH family
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members without separate interrupt stacks automatically perform
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||||
the following actions:
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||||
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||||
@itemize @bullet
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||||
@item To Be Written
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||||
@end itemize
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||||
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||||
@subsubsection Models With Separate Interrupt Stacks
|
||||
|
||||
Upon receipt of an interrupt the SH family
|
||||
members with separate interrupt stacks automatically perform the
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||||
following actions:
|
||||
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||||
@itemize @bullet
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||||
@item saves the current status register (SR),
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||||
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||||
@item clears the master/interrupt (M) bit of the SR to
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||||
indicate the switch from master state to interrupt state,
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||||
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@item sets the privilege mode to supervisor,
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||||
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@item suppresses tracing,
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||||
@item sets the interrupt mask level equal to the level of the
|
||||
interrupt being serviced,
|
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||||
@item pushes an interrupt stack frame (ISF), which includes
|
||||
the program counter (PC), the status register (SR), and the
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||||
format/exception vector offset (FVO) word, onto the supervisor
|
||||
and interrupt stacks,
|
||||
|
||||
@item switches the current stack to the interrupt stack and
|
||||
vectors to an interrupt service routine (ISR). If the ISR was
|
||||
installed with the interrupt_catch directive, then the RTEMS
|
||||
interrupt handler will begin execution. The RTEMS interrupt
|
||||
handler saves all registers which are not preserved according to
|
||||
the calling conventions and invokes the application's ISR.
|
||||
@end itemize
|
||||
|
||||
A nested interrupt is processed similarly by these
|
||||
CPU models with the exception that only a single ISF is placed
|
||||
on the interrupt stack and the current stack need not be
|
||||
switched.
|
||||
|
||||
The FVO word in the Interrupt Stack Frame is examined
|
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by RTEMS to determine when an outer most interrupt is being
|
||||
exited. Since the FVO is used by RTEMS for this purpose, the
|
||||
user application code MUST NOT modify this field.
|
||||
|
||||
The following shows the Interrupt Stack Frame for
|
||||
XXX CPU models with separate interrupt stacks:
|
||||
|
||||
@ifset use-ascii
|
||||
@example
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||||
@group
|
||||
+----------------------+
|
||||
| Status Register | 0x0
|
||||
+----------------------+
|
||||
| Program Counter High | 0x2
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||||
+----------------------+
|
||||
| Program Counter Low | 0x4
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||||
+----------------------+
|
||||
| Format/Vector Offset | 0x6
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||||
+----------------------+
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||||
@end group
|
||||
@end example
|
||||
@end ifset
|
||||
|
||||
@ifset use-tex
|
||||
@sp 1
|
||||
@tex
|
||||
\centerline{\vbox{\offinterlineskip\halign{
|
||||
\strut\vrule#&
|
||||
\hbox to 2.00in{\enskip\hfil#\hfil}&
|
||||
\vrule#&
|
||||
\hbox to 0.50in{\enskip\hfil#\hfil}
|
||||
\cr
|
||||
\multispan{3}\hrulefill\cr
|
||||
& Status Register && 0x0\cr
|
||||
\multispan{3}\hrulefill\cr
|
||||
& Program Counter High && 0x2\cr
|
||||
\multispan{3}\hrulefill\cr
|
||||
& Program Counter Low && 0x4\cr
|
||||
\multispan{3}\hrulefill\cr
|
||||
& Format/Vector Offset && 0x6\cr
|
||||
\multispan{3}\hrulefill\cr
|
||||
}}\hfil}
|
||||
@end tex
|
||||
@end ifset
|
||||
|
||||
@ifset use-html
|
||||
@html
|
||||
<CENTER>
|
||||
<TABLE COLS=2 WIDTH="40%" BORDER=2>
|
||||
<TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD>
|
||||
<TD ALIGN=center>0x0</TD></TR>
|
||||
<TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD>
|
||||
<TD ALIGN=center>0x2</TD></TR>
|
||||
<TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD>
|
||||
<TD ALIGN=center>0x4</TD></TR>
|
||||
<TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD>
|
||||
<TD ALIGN=center>0x6</TD></TR>
|
||||
</TABLE>
|
||||
</CENTER>
|
||||
@end html
|
||||
@end ifset
|
||||
|
||||
@subsection Interrupt Levels
|
||||
|
||||
Eight levels (0-7) of interrupt priorities are
|
||||
supported by XXX family members with level seven (7) being
|
||||
the highest priority. Level zero (0) indicates that interrupts
|
||||
are fully enabled. Interrupt requests for interrupts with
|
||||
priorities less than or equal to the current interrupt mask
|
||||
level are ignored.
|
||||
|
||||
Although RTEMS supports 256 interrupt levels, the
|
||||
XXX family only supports eight. RTEMS interrupt levels 0
|
||||
through 7 directly correspond to XXX interrupt levels. All
|
||||
other RTEMS interrupt levels are undefined and their behavior is
|
||||
unpredictable.
|
||||
|
||||
@subsection Disabling of Interrupts by RTEMS
|
||||
|
||||
During the execution of directive calls, critical
|
||||
sections of code may be executed. When these sections are
|
||||
encountered, RTEMS disables interrupts to level seven (7) before
|
||||
the execution of this section and restores them to the previous
|
||||
level upon completion of the section. RTEMS has been optimized
|
||||
to insure that interrupts are disabled for less than
|
||||
RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
|
||||
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with
|
||||
zero wait states. These numbers will vary based the
|
||||
number of wait states and processor speed present on the target board.
|
||||
[NOTE: The maximum period with interrupts disabled is hand calculated. This
|
||||
calculation was last performed for Release
|
||||
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
|
||||
|
||||
Non-maskable interrupts (NMI) cannot be disabled, and
|
||||
ISRs which execute at this level MUST NEVER issue RTEMS system
|
||||
calls. If a directive is invoked, unpredictable results may
|
||||
occur due to the inability of RTEMS to protect its critical
|
||||
sections. However, ISRs that make no system calls may safely
|
||||
execute as non-maskable interrupts.
|
||||
|
||||
@subsection Interrupt Stack
|
||||
|
||||
RTEMS allocates the interrupt stack from the
|
||||
Workspace Area. The amount of memory allocated for the
|
||||
interrupt stack is determined by the interrupt_stack_size field
|
||||
in the CPU Configuration Table. During the initialization
|
||||
process, RTEMS will install its interrupt stack.
|
||||
|
||||
The XXX port of RTEMS supports a software managed
|
||||
dedicated interrupt stack on those CPU models which do not
|
||||
support a separate interrupt stack in hardware.
|
||||
|
||||
|
||||
@c
|
||||
@c COPYRIGHT (c) 1988-2002.
|
||||
@c On-Line Applications Research Corporation (OAR).
|
||||
@c All rights reserved.
|
||||
@c
|
||||
@c $Id$
|
||||
@c
|
||||
|
||||
@section Default Fatal Error Processing
|
||||
|
||||
|
||||
Upon detection of a fatal error by either the
|
||||
application or RTEMS the fatal error manager is invoked. The
|
||||
fatal error manager will invoke the user-supplied fatal error
|
||||
handlers. If no user-supplied handlers are configured, the
|
||||
RTEMS provided default fatal error handler is invoked. If the
|
||||
user-supplied fatal error handlers return to the executive the
|
||||
default fatal error handler is then invoked. This chapter
|
||||
describes the precise operations of the default fatal error
|
||||
handler.
|
||||
|
||||
@subsection Default Fatal Error Handler Operations
|
||||
|
||||
The default fatal error handler which is invoked by
|
||||
the @code{rtems_fatal_error_occurred} directive when there is
|
||||
no user handler configured or the user handler returns control to
|
||||
RTEMS. The default fatal error handler disables processor interrupts,
|
||||
places the error code in @b{XXX}, and executes a @code{XXX}
|
||||
instruction to simulate a halt processor instruction.
|
||||
|
||||
@c
|
||||
@c COPYRIGHT (c) 1988-2002.
|
||||
@c On-Line Applications Research Corporation (OAR).
|
||||
@c All rights reserved.
|
||||
@c
|
||||
@c $Id$
|
||||
@c
|
||||
|
||||
@section Board Support Packages
|
||||
|
||||
|
||||
An RTEMS Board Support Package (BSP) must be designed
|
||||
to support a particular processor and target board combination.
|
||||
This chapter presents a discussion of XXX specific BSP
|
||||
issues. For more information on developing a BSP, refer to the
|
||||
chapter titled Board Support Packages in the RTEMS
|
||||
Applications User's Guide.
|
||||
|
||||
@subsection System Reset
|
||||
|
||||
An RTEMS based application is initiated or
|
||||
re-initiated when the XXX processor is reset. When the
|
||||
XXX is reset, the processor performs the following actions:
|
||||
|
||||
@itemize @bullet
|
||||
@item The tracing bits of the status register are cleared to
|
||||
disable tracing.
|
||||
|
||||
@item The supervisor interrupt state is entered by setting the
|
||||
supervisor (S) bit and clearing the master/interrupt (M) bit of
|
||||
the status register.
|
||||
|
||||
@item The interrupt mask of the status register is set to
|
||||
level 7 to effectively disable all maskable interrupts.
|
||||
|
||||
@item The vector base register (VBR) is set to zero.
|
||||
|
||||
@item The cache control register (CACR) is set to zero to
|
||||
disable and freeze the processor cache.
|
||||
|
||||
@item The interrupt stack pointer (ISP) is set to the value
|
||||
stored at vector 0 (bytes 0-3) of the exception vector table
|
||||
(EVT).
|
||||
|
||||
@item The program counter (PC) is set to the value stored at
|
||||
vector 1 (bytes 4-7) of the EVT.
|
||||
|
||||
@item The processor begins execution at the address stored in
|
||||
the PC.
|
||||
@end itemize
|
||||
|
||||
@subsection Processor Initialization
|
||||
|
||||
The address of the application's initialization code
|
||||
should be stored in the first vector of the EVT which will allow
|
||||
the immediate vectoring to the application code. If the
|
||||
application requires that the VBR be some value besides zero,
|
||||
then it should be set to the required value at this point. All
|
||||
tasks share the same XXX's VBR value. Because interrupts
|
||||
are enabled automatically by RTEMS as part of the initialize
|
||||
executive directive, the VBR MUST be set before this directive
|
||||
is invoked to insure correct interrupt vectoring. If processor
|
||||
caching is to be utilized, then it should be enabled during the
|
||||
reset application initialization code.
|
||||
|
||||
In addition to the requirements described in the
|
||||
Board Support Packages chapter of the Applications User's
|
||||
Manual for the reset code which is executed before the call to
|
||||
initialize executive, the XXX version has the following
|
||||
specific requirements:
|
||||
|
||||
@itemize @bullet
|
||||
@item Must leave the S bit of the status register set so that
|
||||
the XXX remains in the supervisor state.
|
||||
|
||||
@item Must set the M bit of the status register to remove the
|
||||
XXX from the interrupt state.
|
||||
|
||||
@item Must set the master stack pointer (MSP) such that a
|
||||
minimum stack size of MINIMUM_STACK_SIZE bytes is provided for
|
||||
the initialize executive directive.
|
||||
|
||||
@item Must initialize the XXX's vector table.
|
||||
@end itemize
|
||||
|
||||
Note that the BSP is not responsible for allocating
|
||||
or installing the interrupt stack. RTEMS does this
|
||||
automatically as part of initialization. If the BSP does not
|
||||
install an interrupt stack and -- for whatever reason -- an
|
||||
interrupt occurs before initialize_executive is invoked, then
|
||||
the results are unpredictable.
|
||||
|
||||
@c
|
||||
@c COPYRIGHT (c) 1988-2002.
|
||||
@c On-Line Applications Research Corporation (OAR).
|
||||
@c All rights reserved.
|
||||
@c
|
||||
@c $Id$
|
||||
@c
|
||||
|
||||
@section Processor Dependent Information Table
|
||||
|
||||
|
||||
Any highly processor dependent information required
|
||||
to describe a processor to RTEMS is provided in the CPU
|
||||
Dependent Information Table. This table is not required for all
|
||||
processors supported by RTEMS. This chapter describes the
|
||||
contents, if any, for a particular processor type.
|
||||
|
||||
@subsection CPU Dependent Information Table
|
||||
|
||||
The XXX version of the RTEMS CPU Dependent
|
||||
Information Table contains the information required to interface
|
||||
a Board Support Package and RTEMS on the XXX. This
|
||||
information is provided to allow RTEMS to interoperate
|
||||
effectively with the BSP. The C structure definition is given
|
||||
here:
|
||||
|
||||
@example
|
||||
@group
|
||||
typedef struct @{
|
||||
void (*pretasking_hook)( void );
|
||||
void (*predriver_hook)( void );
|
||||
void (*postdriver_hook)( void );
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 idle_task_stack_size;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
/* XXX CPU family dependent stuff */
|
||||
@} rtems_cpu_table;
|
||||
@end group
|
||||
@end example
|
||||
|
||||
@table @code
|
||||
@item pretasking_hook
|
||||
is the address of the user provided routine which is invoked
|
||||
once RTEMS APIs are initialized. This routine will be invoked
|
||||
before any system tasks are created. Interrupts are disabled.
|
||||
This field may be NULL to indicate that the hook is not utilized.
|
||||
|
||||
@item predriver_hook
|
||||
is the address of the user provided
|
||||
routine that is invoked immediately before the
|
||||
the device drivers and MPCI are initialized. RTEMS
|
||||
initialization is complete but interrupts and tasking are disabled.
|
||||
This field may be NULL to indicate that the hook is not utilized.
|
||||
|
||||
@item postdriver_hook
|
||||
is the address of the user provided
|
||||
routine that is invoked immediately after the
|
||||
the device drivers and MPCI are initialized. RTEMS
|
||||
initialization is complete but interrupts and tasking are disabled.
|
||||
This field may be NULL to indicate that the hook is not utilized.
|
||||
|
||||
@item idle_task
|
||||
is the address of the optional user
|
||||
provided routine which is used as the system's IDLE task. If
|
||||
this field is not NULL, then the RTEMS default IDLE task is not
|
||||
used. This field may be NULL to indicate that the default IDLE
|
||||
is to be used.
|
||||
|
||||
@item do_zero_of_workspace
|
||||
indicates whether RTEMS should
|
||||
zero the Workspace as part of its initialization. If set to
|
||||
TRUE, the Workspace is zeroed. Otherwise, it is not.
|
||||
|
||||
@item idle_task_stack_size
|
||||
is the size of the RTEMS idle task stack in bytes.
|
||||
If this number is less than MINIMUM_STACK_SIZE, then the
|
||||
idle task's stack will be MINIMUM_STACK_SIZE in byte.
|
||||
|
||||
@item interrupt_stack_size
|
||||
is the size of the RTEMS
|
||||
allocated interrupt stack in bytes. This value must be at least
|
||||
as large as MINIMUM_STACK_SIZE.
|
||||
|
||||
@item extra_mpci_receive_server_stack
|
||||
is the extra stack space allocated for the RTEMS MPCI receive server task
|
||||
in bytes. The MPCI receive server may invoke nearly all directives and
|
||||
may require extra stack space on some targets.
|
||||
|
||||
@item stack_allocate_hook
|
||||
is the address of the optional user provided routine which allocates
|
||||
memory for task stacks. If this hook is not NULL, then a stack_free_hook
|
||||
must be provided as well.
|
||||
|
||||
@item stack_free_hook
|
||||
is the address of the optional user provided routine which frees
|
||||
memory for task stacks. If this hook is not NULL, then a stack_allocate_hook
|
||||
must be provided as well.
|
||||
|
||||
@item XXX
|
||||
is where the CPU family dependent stuff goes.
|
||||
|
||||
@end table
|
||||
Reference in New Issue
Block a user