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Converted to use shared

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exception and interrupt code.
This commit is contained in:
Thomas Doerfler
2008-09-03 15:39:03 +00:00
parent 9ac98838d6
commit 82bd8d9d66
15 changed files with 685 additions and 863 deletions
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2
c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c
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@@ -19,7 +19,7 @@
#include <rtems.h> #include <rtems.h>
#include <rtems/error.h> #include <rtems/error.h>
#include <bsp.h> #include <bsp.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include "include/ppctypes.h" /* uint32, et. al. */ #include "include/ppctypes.h" /* uint32, et. al. */
#include "dma_image.h" #include "dma_image.h"

4
c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c
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@@ -39,7 +39,7 @@ __declspec(section ".text") extern const uint32 taskTableBytes;
__declspec(section ".text") extern const uint32 taskTableTasks; __declspec(section ".text") extern const uint32 taskTableTasks;
__declspec(section ".text") extern const uint32 offsetEntry; __declspec(section ".text") extern const uint32 offsetEntry;
#else #else
extern const uint32 taskTable; extern const uint32 taskTable [];
extern const uint32 taskTableBytes; extern const uint32 taskTableBytes;
extern const uint32 taskTableTasks; extern const uint32 taskTableTasks;
extern const uint32 offsetEntry; extern const uint32 offsetEntry;
@@ -71,7 +71,7 @@ void TasksLoadImage(sdma_regs *sdma)
SCTDT_T *tt; SCTDT_T *tt;
/* copy task table from source to destination */ /* copy task table from source to destination */
memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), &taskTable, taskTableBytes); memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), taskTable, taskTableBytes);
/* adjust addresses in task table */ /* adjust addresses in task table */
for (i=0; i < (uint32) taskTableTasks; i++) { for (i=0; i < (uint32) taskTableTasks; i++) {
tt = (SCTDT_T *)(((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal) + (uint32) offsetEntry + (i * sizeof (SCTDT_T))); tt = (SCTDT_T *)(((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal) + (uint32) offsetEntry + (i * sizeof (SCTDT_T)));

105
c/src/lib/libbsp/powerpc/gen5200/clock/clock.c
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@@ -103,7 +103,7 @@
#include <bsp.h> #include <bsp.h>
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include <rtems.h> #include <rtems.h>
#include <rtems/clockdrv.h> #include <rtems/clockdrv.h>
@@ -114,6 +114,8 @@
#define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0) #define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0)
extern uint32_t bsp_clicks_per_usec;
/* this lets us do nanoseconds since last tick */ /* this lets us do nanoseconds since last tick */
uint64_t Clock_last_TBR; uint64_t Clock_last_TBR;
volatile uint32_t counter_value; volatile uint32_t counter_value;
@@ -122,7 +124,7 @@ volatile int ClockInitialized = 0;
/* /*
* ISR Handlers * ISR Handlers
*/ */
void mpc5200_gpt_clock_isr(rtems_irq_hdl_param handle) void mpc5200_gpt_clock_isr(rtems_vector_number vector, void *handle)
{ {
uint32_t status; uint32_t status;
struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)handle; struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)handle;
@@ -218,45 +220,32 @@ uint32_t mpc5200_check_gpt_status(uint32_t gpt_no)
return ((gpt->emsel) & (GPT_EMSEL_CE | GPT_EMSEL_INTEN)); return ((gpt->emsel) & (GPT_EMSEL_CE | GPT_EMSEL_INTEN));
} }
void clockOn(const rtems_irq_connect_data* irq) void clockOn()
{ {
uint32_t gpt_no; uint32_t gpt_no;
extern uint32_t bsp_clicks_per_usec;
gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name); gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
counter_value = rtems_configuration_get_microseconds_per_tick() * counter_value = rtems_configuration_get_microseconds_per_tick() *
bsp_clicks_per_usec; bsp_clicks_per_usec;
mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no); mpc5200_set_gpt_count(counter_value, gpt_no);
mpc5200_enable_gpt_int((uint32_t)gpt_no); mpc5200_enable_gpt_int(gpt_no);
ClockInitialized = 1; ClockInitialized = 1;
} }
void clockOff(const rtems_irq_connect_data* irq) void clockOff()
{ {
uint32_t gpt_no; uint32_t gpt_no;
gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name); gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
mpc5200_disable_gpt_int((uint32_t)gpt_no); mpc5200_disable_gpt_int(gpt_no);
ClockInitialized = 0; ClockInitialized = 0;
} }
int clockIsOn(const rtems_irq_connect_data* irq)
{
uint32_t gpt_no;
gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
if (mpc5200_check_gpt_status(gpt_no) && ClockInitialized)
return ClockInitialized;
return 0;
}
int BSP_get_clock_irq_level(void) int BSP_get_clock_irq_level(void)
{ {
/* /*
@@ -266,56 +255,51 @@ int BSP_get_clock_irq_level(void)
return BSP_PERIODIC_TIMER; return BSP_PERIODIC_TIMER;
} }
int BSP_disconnect_clock_handler (unsigned gpt_no)
int BSP_disconnect_clock_handler (void)
{ {
rtems_irq_connect_data clockIrqData; rtems_status_code sc = RTEMS_SUCCESSFUL;
clockIrqData.name = BSP_PERIODIC_TIMER;
if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) { return 0;
printk("Unable to stop system clock\n");
rtems_fatal_error_occurred(1);
} }
return BSP_remove_rtems_irq_handler (&clockIrqData); clockOff( BSP_PERIODIC_TIMER);
sc = rtems_interrupt_handler_remove(
BSP_PERIODIC_TIMER,
mpc5200_gpt_clock_isr,
&mpc5200.gpt [gpt_no]
);
if (sc != RTEMS_SUCCESSFUL) {
return 0;
}
return 1;
} }
int BSP_connect_clock_handler (unsigned gpt_no)
int BSP_connect_clock_handler (uint32_t gpt_no)
{ {
rtems_irq_hdl hdl = 0; rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_irq_connect_data clockIrqData;
/* if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
* Reinit structure
*/
clockIrqData.name = BSP_PERIODIC_TIMER;
if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
printk("Unable to get system clock handler\n");
rtems_fatal_error_occurred(1);
}
if (!BSP_remove_rtems_irq_handler (&clockIrqData)) {
printk("Unable to remove current system clock handler\n");
rtems_fatal_error_occurred(1);
}
if ((gpt_no >= GPT0) || (gpt_no <= GPT7)) {
hdl = (rtems_irq_hdl_param )&mpc5200.gpt[gpt_no];
} else {
printk("Unable to set system clock handler\n"); printk("Unable to set system clock handler\n");
rtems_fatal_error_occurred(1); rtems_fatal_error_occurred(1);
} }
clockIrqData.hdl = mpc5200_gpt_clock_isr; sc = rtems_interrupt_handler_install(
clockIrqData.handle = (rtems_irq_hdl_param) hdl; BSP_PERIODIC_TIMER,
clockIrqData.on = clockOn; "Clock",
clockIrqData.off = clockOff; RTEMS_INTERRUPT_UNIQUE,
clockIrqData.isOn = clockIsOn; mpc5200_gpt_clock_isr,
&mpc5200.gpt [gpt_no]
);
if (sc != RTEMS_SUCCESSFUL) {
return 0;
}
return BSP_install_rtems_irq_handler (&clockIrqData); clockOn();
return 1;
} }
#define CLOCK_VECTOR 0 #define CLOCK_VECTOR 0
@@ -342,7 +326,6 @@ int BSP_connect_clock_handler (uint32_t gpt_no)
/* This driver does this in clockOn called at connection time */ /* This driver does this in clockOn called at connection time */
#define Clock_driver_support_initialize_hardware() \ #define Clock_driver_support_initialize_hardware() \
do { \ do { \
extern uint32_t bsp_clicks_per_usec; \
counter_value = rtems_configuration_get_microseconds_per_tick() * \ counter_value = rtems_configuration_get_microseconds_per_tick() * \
bsp_clicks_per_usec; \ bsp_clicks_per_usec; \
mpc5200_init_gpt(GPT); \ mpc5200_init_gpt(GPT); \
@@ -354,7 +337,7 @@ int BSP_connect_clock_handler (uint32_t gpt_no)
#define Clock_driver_support_shutdown_hardware() \ #define Clock_driver_support_shutdown_hardware() \
do { \ do { \
(void) BSP_disconnect_clock_handler (); \ (void) BSP_disconnect_clock_handler (GPT); \
} while (0) } while (0)
#include "../../../shared/clockdrv_shell.c" #include "../../../shared/clockdrv_shell.c"

2
c/src/lib/libbsp/powerpc/gen5200/console/console.c
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@@ -98,7 +98,7 @@
#include <rtems.h> #include <rtems.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include <bsp.h> #include <bsp.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include <rtems/libio.h> #include <rtems/libio.h>

2
c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c
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@@ -34,7 +34,7 @@
*/ */
#include "mpc5200mbus.h" #include "mpc5200mbus.h"
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/i2c.h" #include "../include/i2c.h"
/* Events of I2C machine */ /* Events of I2C machine */

2
c/src/lib/libbsp/powerpc/gen5200/ide/idecfg.c
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@@ -18,7 +18,7 @@
\*===============================================================*/ \*===============================================================*/
#include <rtems.h> #include <rtems.h>
#include <bsp.h> #include <bsp.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include "./pcmcia_ide.h" #include "./pcmcia_ide.h"

2
c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c
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@@ -78,7 +78,7 @@
#include <rtems.h> #include <rtems.h>
#include <rtems/error.h> #include <rtems/error.h>
#include <bsp.h> #include <bsp.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include "./pcmcia_ide.h" #include "./pcmcia_ide.h"

67
c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
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@@ -23,6 +23,44 @@
#ifndef __GEN5200_BSP_h #ifndef __GEN5200_BSP_h
#define __GEN5200_BSP_h #define __GEN5200_BSP_h
#include <libcpu/powerpc-utility.h>
/*
* Some symbols defined in the linker command file.
*/
LINKER_SYMBOL(bsp_ram_start);
LINKER_SYMBOL(bsp_ram_end);
LINKER_SYMBOL(bsp_ram_size);
LINKER_SYMBOL(bsp_rom_start);
LINKER_SYMBOL(bsp_rom_end);
LINKER_SYMBOL(bsp_rom_size);
LINKER_SYMBOL(bsp_dpram_start);
LINKER_SYMBOL(bsp_dpram_end);
LINKER_SYMBOL(bsp_dpram_size);
LINKER_SYMBOL(bsp_section_text_start);
LINKER_SYMBOL(bsp_section_text_end);
LINKER_SYMBOL(bsp_section_text_size);
LINKER_SYMBOL(bsp_section_data_start);
LINKER_SYMBOL(bsp_section_data_end);
LINKER_SYMBOL(bsp_section_data_size);
LINKER_SYMBOL(bsp_section_bss_start);
LINKER_SYMBOL(bsp_section_bss_end);
LINKER_SYMBOL(bsp_section_bss_size);
LINKER_SYMBOL(bsp_interrupt_stack_start);
LINKER_SYMBOL(bsp_interrupt_stack_end);
LINKER_SYMBOL(bsp_interrupt_stack_size);
LINKER_SYMBOL(bsp_work_area_start);
LINKER_SYMBOL(MBAR);
/* /*
* distinguish board characteristics * distinguish board characteristics
*/ */
@@ -56,27 +94,6 @@
#define GPIOPCR_INITVAL 0x91050444 #define GPIOPCR_INITVAL 0x91050444
/* we have PSC1/2/3 */ /* we have PSC1/2/3 */
#define GEN5200_UART_AVAIL_MASK 0x07 #define GEN5200_UART_AVAIL_MASK 0x07
/*
* address range definitions
*/
/* ROM definitions (2 MB) */
#define ROM_START 0xFFE00000
#define ROM_SIZE 0x00200000
#define ROM_END (ROM_START+ROM_SIZE-1)
#define BOOT_START ROM_START
#define BOOT_END ROM_END
/* SDRAM definitions (256 MB) */
#define RAM_START 0x00000000
#define RAM_SIZE 0x10000000
#define RAM_END (RAM_START+RAM_SIZE-1)
/* DPRAM definitions (64 KB) */
#define DPRAM_START 0xFF000000
#define DPRAM_END 0xFF0003FF
/* internal memory map definitions (64 KB) */
#define MBAR 0xF0000000
/* we need the low level initialization in start.S*/ /* we need the low level initialization in start.S*/
#define NEED_LOW_LEVEL_INIT #define NEED_LOW_LEVEL_INIT
@@ -84,10 +101,6 @@
#define HAS_NVRAM_93CXX #define HAS_NVRAM_93CXX
#elif defined (PM520) #elif defined (PM520)
/*
* MicroSys PM520 internal memory map definitions
*/
#define MBAR 0xF0000000
#define HAS_UBOOT #define HAS_UBOOT
#elif defined (icecube) #elif defined (icecube)
@@ -107,8 +120,6 @@
/* we only have PSC1 */ /* we only have PSC1 */
#define GEN5200_UART_AVAIL_MASK 0x01 #define GEN5200_UART_AVAIL_MASK 0x01
#define MBAR 0xF0000000
/* We want to prompt for a reset and then reset the board */ /* We want to prompt for a reset and then reset the board */
#define BSP_PRESS_KEY_FOR_RESET 1 #define BSP_PRESS_KEY_FOR_RESET 1
#define BSP_RESET_BOARD_AT_EXIT 1 #define BSP_RESET_BOARD_AT_EXIT 1
@@ -269,6 +280,8 @@ void BSP_IRQ_Benchmarking_Report(void);
); );
#endif #endif
void cpu_init(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

996
c/src/lib/libbsp/powerpc/gen5200/irq/irq.c
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File diff suppressed because it is too large Load Diff

2
c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c
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@@ -65,7 +65,7 @@
#include <netinet/in.h> #include <netinet/in.h>
#include <netinet/if_ether.h> #include <netinet/if_ether.h>
#include <bsp.h> #include <bsp.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include <net/if_var.h> #include <net/if_var.h>
#include <errno.h> #include <errno.h>

4
c/src/lib/libbsp/powerpc/gen5200/slicetimer/slicetimer.c
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@@ -99,13 +99,13 @@
#include <bsp.h> #include <bsp.h>
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include <rtems.h> #include <rtems.h>
#include <rtems/clockdrv.h> #include <rtems/clockdrv.h>
#include <rtems/libio.h> #include <rtems/libio.h>
#include "../irq/irq.h" #include <bsp/irq.h>
#include "../include/mpc5200.h" #include "../include/mpc5200.h"
#include "../slicetimer/slicetimer.h" #include "../slicetimer/slicetimer.h"
#include <stdio.h> #include <stdio.h>

127
c/src/lib/libbsp/powerpc/gen5200/start/start.S
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@@ -90,56 +90,10 @@
/* */ /* */
/***********************************************************************/ /***********************************************************************/
#include <rtems/asm.h>
#include <rtems/powerpc/cache.h> #include <rtems/powerpc/cache.h>
#include <rtems/powerpc/registers.h>
#include "../include/mpc5200.h"
#include "../include/bsp.h"
/* Macro definitions to load a register with a 32-bit address. #include <bsp.h>
Both functions identically. Sometimes one mnemonic is more #include <bsp/mpc5200.h>
appropriate than the other.
reg -> register to load
value -> value to be loaded
LA reg,value ("Load Address")
LWI reg,value ("Load Word Immediate") */
.macro LA reg, value
lis \reg , \value@h
ori \reg , \reg, \value@l
sync
.endm
.macro LWI reg, value
lis \reg , (\value)@h
ori \reg , \reg, (\value)@l
sync
.endm
/* Macro definitions to test, set or clear a single
bit or bit pattern in a given 32bit GPR.
reg1 -> register content to be tested
reg2 -> 2nd register only needed for computation
mask -> any bit pattern */
.macro TSTBITS reg1, reg2, mask /* Match is indicated by EQ=0 (CR) */
LWI \reg2, \mask /* Unmatch is indicated by EQ=1 (CR) */
and \reg1, \reg1, \reg2
cmplw \reg1, \reg2
sync
.endm
.macro SETBITS reg1, reg2, mask
LWI \reg2, \mask
or \reg1, \reg1, \reg2
sync
.endm
.macro CLRBITS reg1, reg2, mask
LWI \reg2, \mask
andc \reg1, \reg1, \reg2
sync
.endm
/* Some register offsets of MPC5x00 memory map registers */ /* Some register offsets of MPC5x00 memory map registers */
.set CS0STR, 0x04 .set CS0STR, 0x04
@@ -200,15 +154,7 @@
.set CSCONTROL_VAL, 0x91000000 .set CSCONTROL_VAL, 0x91000000
.set CFG_VAL, 0x00000100 .set CFG_VAL, 0x00000100
.extern _bss_start
.extern _bss_size
.extern _data_start
.extern _data_size
.extern _text_start
.extern _text_size
/*.extern _s_got*/
.extern boot_card .extern boot_card
.extern MBAR
.section ".entry" .section ".entry"
PUBLIC_VAR (start) PUBLIC_VAR (start)
@@ -262,7 +208,7 @@ start:
#if defined(NEED_LOW_LEVEL_INIT) #if defined(NEED_LOW_LEVEL_INIT)
/* detect RAM/ROM startup (common for RAM/ROM startup) */ /* detect RAM/ROM startup (common for RAM/ROM startup) */
LWI r20, ROM_START /* set the relocation offset */ LWI r20, bsp_rom_start /* set the relocation offset */
LWI r30, CFG_VAL /* get CFG register content */ LWI r30, CFG_VAL /* get CFG register content */
@@ -295,12 +241,11 @@ start:
/* FIXME: map BOOT ROM into final location with CS0 registers */ /* FIXME: map BOOT ROM into final location with CS0 registers */
LWI r30, ROM_START LWI r30, bsp_rom_start
rlwinm r30, r30,17,15,31 rlwinm r30, r30,17,15,31
stw r30, CS0STR(r31) /* Set CS0STR */ stw r30, CS0STR(r31) /* Set CS0STR */
lis r30, ROM_END@h LWI r30, bsp_rom_end
ori r30, r30, ROM_END@l
rlwinm r30, r30,17,15,31 rlwinm r30, r30,17,15,31
stw r30, CS0STP(r31) /* Set CS0STP */ stw r30, CS0STP(r31) /* Set CS0STP */
@@ -311,9 +256,9 @@ start:
isync isync
/* jump to same code in final BOOT ROM location */ /* jump to same code in final BOOT ROM location */
LWI r30, reloc_in_CS0 LWI r30, reloc_in_CS0
LWI r29, RAM_START LWI r29, bsp_ram_start
sub r30,r30,r29 sub r30,r30,r29
LWI r29, ROM_START LWI r29, bsp_rom_start
add r30,r30,r29 add r30,r30,r29
mtctr r30 mtctr r30
bctr bctr
@@ -325,12 +270,13 @@ reloc_in_CS0:
stw r30, ADREN(r31) /* disable BOOT mapping */ stw r30, ADREN(r31) /* disable BOOT mapping */
/* init SDRAM */ /* init SDRAM */
LWI r30, RAM_START LWI r30, bsp_ram_start
ori r30,r30,0x1a /* size code: bank is 128MByte */ ori r30, r30, 0x1a /* size code: bank is 128MByte */
stw r30,SDRAMCS0(r31) /* Set SDRAMCS0 */ stw r30, SDRAMCS0(r31) /* Set SDRAMCS0 */
LWI r30,(RAM_SIZE)>>1 LWI r30, bsp_ram_size
ori r30,r30,0x1a /* size code: bank is 128MByte */ srawi r30, r30, 1
ori r30, r30, 0x1a /* size code: bank is 128MByte */
stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */ stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
bl SDRAM_init /* Initialize SDRAM controller */ bl SDRAM_init /* Initialize SDRAM controller */
@@ -348,32 +294,32 @@ reloc_in_CS0:
LWI r30, 0x0000001e LWI r30, 0x0000001e
stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */ stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
/* copy .text section from ROM to RAM location (unique for ROM startup) */ /* copy .text section from ROM to RAM location (unique for ROM startup) */
LA r30, _text_start /* get start address of text section in RAM */ LA r30, bsp_section_text_start /* get start address of text section in RAM */
add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */ add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
LA r29, _text_start /* get start address of text section in RAM */ LA r29, bsp_section_text_start /* get start address of text section in RAM */
LA r28, _text_size /* get size of RAM image */ LA r28, bsp_section_text_size /* get size of RAM image */
bl copy_image /* copy text section from ROM to RAM location */ bl copy_image /* copy text section from ROM to RAM location */
/* copy .data section from ROM to RAM location (unique for ROM startup) */ /* copy .data section from ROM to RAM location (unique for ROM startup) */
LA r30, _data_start /* get start address of data section in RAM */ LA r30, bsp_section_data_start /* get start address of data section in RAM */
add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */ add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
LA r29, _data_start /* get start address of data section in RAM */ LA r29, bsp_section_data_start /* get start address of data section in RAM */
LA r28, _data_size /* get size of RAM image */ LA r28, bsp_section_data_size /* get size of RAM image */
bl copy_image /* copy initialized data section from ROM to RAM location */ bl copy_image /* copy initialized data section from ROM to RAM location */
@@ -425,43 +371,46 @@ remap_rom:
skip_ROM_start: skip_ROM_start:
/* configure external DPRAM CS1 */ /* configure external DPRAM CS1 */
LWI r30,0xFFFFFB10 LWI r30, 0xFFFFFB10
stw r30,CS1CONF(r31) stw r30, CS1CONF(r31)
/* map external DPRAM (CS1) */ /* map external DPRAM (CS1) */
LWI r30,(DPRAM_START>>16) LWI r30, bsp_dpram_start
stw r30,CS1STR(r31) srawi r30, r30, 16
stw r30, CS1STR(r31)
LWI r30,((DPRAM_END)>>16) LWI r30, bsp_dpram_end
stw r30,CS1STP(r31) srawi r30, r30, 16
stw r30, CS1STP(r31)
lwz r30, ADREN(r31) /* get content of ADREN */ lwz r30, ADREN(r31) /* get content of ADREN */
LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */ LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
or r30,r30,r29 or r30, r30,r29
stw r30,ADREN(r31) /* enable CS1 */ stw r30, ADREN(r31) /* enable CS1 */
/* clear entire on chip SRAM (unique for ROM startup) */ /* clear entire on chip SRAM (unique for ROM startup) */
lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */ lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
ori r30,r30,(MBAR+ONCHIP_SRAM_OFFSET)@l ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */ LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
bl clr_mem /* Clear onchip SRAM */ bl clr_mem /* Clear onchip SRAM */
#endif /* defined(BRS5L) */ #endif /* defined(BRS5L) */
/* clear .bss section (unique for ROM startup) */ /* clear .bss section (unique for ROM startup) */
LWI r30, _bss_start /* get start address of bss section */ LWI r30, bsp_section_bss_start /* get start address of bss section */
LWI r29, _bss_size /* get size of bss section */ LWI r29, bsp_section_bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */ bl clr_mem /* Clear the bss section */
/* set stack pointer (common for RAM/ROM startup) */ /* set stack pointer (common for RAM/ROM startup) */
LA r1, _text_start LA r1, bsp_section_text_start
addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */ addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
bl __eabi /* Set up EABI and SYSV environment */
/* enable dynamic power management(common for RAM/ROM startup) */ /* enable dynamic power management(common for RAM/ROM startup) */
bl PPC_HID0_rd /* Get the content of HID0 */ bl PPC_HID0_rd /* Get the content of HID0 */
@@ -622,7 +571,7 @@ FID_DCache:
bne FID_DCache_exit /* If data cache is switched of, skip further actions */ bne FID_DCache_exit /* If data cache is switched of, skip further actions */
li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
LWI r28, _text_start /* Load base address (begin of RAM) */ LWI r28, bsp_section_text_start /* Load base address (begin of RAM) */
FID_DCache_loop_1: FID_DCache_loop_1:
lwz r27, 0(r28) /* Load data at address */ lwz r27, 0(r28) /* Load data at address */
@@ -633,7 +582,7 @@ FID_DCache_loop_1:
bne FID_DCache_loop_1 /* Loop until cache size is reached */ bne FID_DCache_loop_1 /* Loop until cache size is reached */
li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */ li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
LWI r28, _text_start /* Reload base address (begin of RAM) */ LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
xor r27, r27, r27 xor r27, r27, r27
FID_DCache_loop_2: FID_DCache_loop_2:
@@ -697,7 +646,7 @@ FPU_init:
mtmsr r30 /* enable FPU and FPU exceptions */ mtmsr r30 /* enable FPU and FPU exceptions */
#if 0 #if 0
LA r29, RAM_START LA r29, bsp_ram_start
stw r29, 0x0(r29) stw r29, 0x0(r29)
#endif #endif

3
c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c
View File

@@ -14,7 +14,8 @@
#include <rtems.h> #include <rtems.h>
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include <bsp.h> #include <bsp.h>
#include <mpc5200.h> #include <bsp/mpc5200.h>
#include <bsp/bootcard.h>
extern int mpc5200_uart_pollRead(int minor); extern int mpc5200_uart_pollRead(int minor);

123
c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
View File

@@ -96,42 +96,31 @@
#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c). #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
#include <bsp.h> #include <string.h>
#include <rtems/libio.h> #include <rtems/libio.h>
#include <rtems/libcsupport.h> #include <rtems/libcsupport.h>
#include <rtems/powerpc/powerpc.h>
#include <rtems/score/thread.h> #include <rtems/score/thread.h>
#include <rtems/bspIo.h> #include <libcpu/powerpc-utility.h>
#include <libcpu/cpuIdent.h> #include <libcpu/raw_exception.h>
#include <libcpu/spr.h>
#include "../irq/irq.h"
#include <string.h> #include <bsp.h>
#include <bsp/bootcard.h>
#include <bsp/ppc_exc_bspsupp.h>
#include <bsp/irq.h>
#if defined(HAS_UBOOT) #if defined(HAS_UBOOT)
bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */ bd_t *uboot_bdinfo_ptr = (bd_t *)1; /* will be overwritten from startup code */
bd_t uboot_bdinfo_copy; /* will be overwritten with copy of bdinfo */ bd_t uboot_bdinfo_copy; /* will be overwritten with copy of bdinfo */
#endif #endif
SPR_RW(SPRG1)
extern unsigned long intrStackPtr;
/* /*
* Driver configuration parameters * Driver configuration parameters
*/ */
uint32_t bsp_clicks_per_usec; uint32_t bsp_clicks_per_usec;
/*
* Use the shared implementations of the following routines.
* Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
*/
void bsp_libc_init( void *, uint32_t, int );
extern void initialize_exceptions(void);
extern void cpu_init(void);
void BSP_panic(char *s) void BSP_panic(char *s)
{ {
printk("%s PANIC %s\n",_RTEMS_version, s); printk("%s PANIC %s\n",_RTEMS_version, s);
@@ -144,48 +133,23 @@ void _BSP_Fatal_error(unsigned int v)
__asm__ __volatile ("sc"); __asm__ __volatile ("sc");
} }
/* void bsp_get_work_area(
* Function: bsp_pretasking_hook void **work_area_start,
* Created: 95/03/10 size_t *work_area_size,
* void **heap_start,
* Description: size_t *heap_size)
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
void
bsp_pretasking_hook(void)
{ {
/* #ifdef HAS_UBOOT
* These are assigned addresses in the linkcmds file for the BSP. This char *ram_end = (char *) uboot_bdinfo_ptr->bi_memstart +
* approach is better than having these defined as manifest constants and uboot_bdinfo_ptr->bi_memsize;
* compiled into the kernel, but it is still not ideal when dealing with #else /* HAS_UBOOT */
* multiprocessor configuration in which each board as a different memory char *ram_end = bsp_ram_end;
* map. A better place for defining these symbols might be the makefiles. #endif /* HAS_UBOOT */
* Consideration should also be given to developing an approach in which
* the kernel and the application can be linked and burned into ROM
* independently of each other.
*/
#if defined(HAS_UBOOT) *work_area_start = bsp_work_area_start;
extern unsigned char _HeapStart; *work_area_size = ram_end - bsp_work_area_start;
*heap_start = BSP_BOOTCARD_HEAP_USES_WORK_AREA;
bsp_libc_init( &_HeapStart, *heap_size = BSP_BOOTCARD_HEAP_SIZE_DEFAULT;
uboot_bdinfo_ptr->bi_memstart
+ uboot_bdinfo_ptr->bi_memsize
- (uint32_t)&_HeapStart
, 0 );
#else
extern unsigned char _HeapStart;
extern unsigned char _HeapEnd;
bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
#endif
} }
void bsp_predriver_hook(void) void bsp_predriver_hook(void)
@@ -219,10 +183,8 @@ void bsp_predriver_hook(void)
void bsp_start(void) void bsp_start(void)
{ {
extern void *_WorkspaceBase;
ppc_cpu_id_t myCpu; ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision; ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/* /*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
@@ -246,22 +208,8 @@ void bsp_start(void)
cpu_init(); cpu_init();
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
bsp_clicks_per_usec = (IPB_CLOCK/1000000); bsp_clicks_per_usec = (IPB_CLOCK/1000000);
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/* /*
* Enable instruction and data caches. Do not force writethrough mode. * Enable instruction and data caches. Do not force writethrough mode.
*/ */
@@ -272,21 +220,18 @@ void bsp_start(void)
rtems_cache_enable_data(); rtems_cache_enable_data();
#endif #endif
/* /* Initialize exception handler */
* Need to "allocate" the memory for the RTEMS Workspace and ppc_exc_cache_wb_check = 0;
* tell the RTEMS configuration where it is. This memory is ppc_exc_initialize(
* not malloc'ed. It is just "pulled from the air". PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
*/ (uint32_t) bsp_interrupt_stack_start,
Configuration.work_space_start = (void *)&_WorkspaceBase; (uint32_t) bsp_interrupt_stack_size
#ifdef SHOW_MORE_INIT_SETTINGS );
printk( "workspace=%p\n", Configuration.work_space_start );
printk( "workspace size=%d\n", Configuration.work_space_size );
#endif
/* /* Initalize interrupt support */
* Initalize RTEMS IRQ system if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
*/ BSP_panic( "Cannot intitialize interrupt support\n");
BSP_rtems_irq_mng_init(0); }
/* /*
* If the BSP was built with IRQ benchmarking enabled, * If the BSP was built with IRQ benchmarking enabled,

107
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
View File

@@ -117,30 +117,73 @@ void cpu_init_bsp(void)
{ {
BAT dbat; BAT dbat;
calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW); calc_dbat_regvals(
&dbat,
(uint32_t) bsp_ram_start,
(uint32_t) bsp_ram_size,
true,
false,
false,
false,
BPP_RW
);
SET_DBAT(0,dbat.batu,dbat.batl); SET_DBAT(0,dbat.batu,dbat.batl);
calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX); calc_dbat_regvals(
&dbat,
(uint32_t) bsp_rom_start,
(uint32_t) bsp_rom_size,
true,
false,
false,
false,
BPP_RX
);
SET_DBAT(1,dbat.batu,dbat.batl); SET_DBAT(1,dbat.batu,dbat.batl);
calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW); calc_dbat_regvals(
&dbat,
(uint32_t) MBAR,
128 * 1024,
false,
true,
false,
true,
BPP_RW
);
SET_DBAT(2,dbat.batu,dbat.batl); SET_DBAT(2,dbat.batu,dbat.batl);
calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW); calc_dbat_regvals(
&dbat,
(uint32_t) bsp_dpram_start,
128 * 1024,
false,
true,
false,
true,
BPP_RW
);
SET_DBAT(3,dbat.batu,dbat.batl); SET_DBAT(3,dbat.batu,dbat.batl);
} }
#elif defined (HAS_UBOOT) #elif defined (HAS_UBOOT)
void cpu_init_bsp(void) void cpu_init_bsp(void)
{ {
BAT dbat; BAT dbat;
uint32_t start = 0;
/* /*
* Program BAT0 for RAM * Program BAT0 for RAM
*/ */
calc_dbat_regvals(&dbat, calc_dbat_regvals(
uboot_bdinfo_ptr->bi_memstart, &dbat,
uboot_bdinfo_ptr->bi_memsize, uboot_bdinfo_ptr->bi_memstart,
1,0,0,0,BPP_RW); uboot_bdinfo_ptr->bi_memsize,
true,
false,
false,
false,
BPP_RW
);
SET_DBAT(0,dbat.batu,dbat.batl); SET_DBAT(0,dbat.batu,dbat.batl);
/* /*
@@ -150,33 +193,53 @@ void cpu_init_bsp(void)
* U-Boot that lies about the starting address of Flash. This check * U-Boot that lies about the starting address of Flash. This check
* corrects that. * corrects that.
*/ */
if ( (uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize) < if ((uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize)
uboot_bdinfo_ptr->bi_flashstart ) { < uboot_bdinfo_ptr->bi_flashstart) {
uint32_t start = 0 - uboot_bdinfo_ptr->bi_flashsize; start = 0 - uboot_bdinfo_ptr->bi_flashsize;
calc_dbat_regvals(&dbat,
start, uboot_bdinfo_ptr->bi_flashsize, 1,0,0,0,BPP_RX);
} else { } else {
calc_dbat_regvals(&dbat, start = uboot_bdinfo_ptr->bi_flashstart;
uboot_bdinfo_ptr->bi_flashstart,
uboot_bdinfo_ptr->bi_flashsize,
1,0,0,0,BPP_RX);
} }
calc_dbat_regvals(
&dbat,
start,
uboot_bdinfo_ptr->bi_flashsize,
true,
false,
false,
false,
BPP_RX
);
SET_DBAT(1,dbat.batu,dbat.batl); SET_DBAT(1,dbat.batu,dbat.batl);
/* /*
* Program BAT2 for the MBAR * Program BAT2 for the MBAR
*/ */
calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW); calc_dbat_regvals(
&dbat,
(uint32_t) MBAR,
128 * 1024,
false,
true,
false,
true,
BPP_RW
);
SET_DBAT(2,dbat.batu,dbat.batl); SET_DBAT(2,dbat.batu,dbat.batl);
/* /*
* If there is SRAM, program BAT3 for that memory * If there is SRAM, program BAT3 for that memory
*/ */
if (uboot_bdinfo_ptr->bi_sramsize != 0) { if (uboot_bdinfo_ptr->bi_sramsize != 0) {
calc_dbat_regvals(&dbat, calc_dbat_regvals(
uboot_bdinfo_ptr->bi_sramstart, &dbat,
uboot_bdinfo_ptr->bi_sramsize, uboot_bdinfo_ptr->bi_sramstart,
0,1,1,1,BPP_RW); uboot_bdinfo_ptr->bi_sramsize,
false,
true,
true,
true,
BPP_RW
);
SET_DBAT(3,dbat.batu,dbat.batl); SET_DBAT(3,dbat.batu,dbat.batl);
} }
} }