forked from Imagelibrary/rtems
2009-05-08 Kate Feng <feng1@bnl.gov>
PR1395/bsps * Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007. * network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver. * pci/pci_interface.c: + Enabled PCI "Read", "Read Line", and "Read Multiple" + Agressive Prefetch to improve the performance of the PCI based applications (e.g. 1GHz NIC). * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value register to monitor the cause of the level sensitive interrupts. This unique solution solves various bugs in the 1GHz network drivers Fixed bugs in compute_pic_masks_from_prio() * pci/pci.c : Updated it to be consistent with the original pci.c * written by Eric Valette. There is no change in its function. * irq/irq_init.c : set defaultIrq->next_handler to be 0 * for BSP_SHARED_HANDLER_SUPPORT.
This commit is contained in:
Joel Sherrill
492
c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c
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492
c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c
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@@ -0,0 +1,492 @@
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/* BSP_irq.c
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*
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* This file contains the implementation of the function described in irq.h
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*
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* Copyright (C) 1998, 1999 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Acknowledgement May 2004, to Till Straumann <strauman@slac.stanford.edu>
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* for some inputs.
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*
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* Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>,
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* NSLS, Brookhaven National Laboratory. All rights reserved.
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*
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* 1) Used GT_GPP_Value register instead of the GT_GPP_Interrupt_Cause
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* register to monitor the cause of the level sensitive interrupts.
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* (Copyright : NDA item)
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* 2) The implementation of picPrioTable[] is an original work by the
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* author to optimize the software IRQ priority scheduling because
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* Discovery controller does not provide H/W IRQ priority schedule.
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* It ensures the fastest/faster interrupt service to the
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* highest/higher priority IRQ, if pendig.
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* 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
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*
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*/
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#include <stdio.h>
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#include <rtems/system.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/apiext.h>
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#include <libcpu/raw_exception.h>
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#include <rtems/rtems/intr.h>
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#include <libcpu/io.h>
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#include <libcpu/byteorder.h>
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#include <bsp/vectors.h>
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#include <rtems/bspIo.h> /* for printk */
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#include "bsp/gtreg.h"
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#define HI_INT_CAUSE 0x40000000
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#define MAX_IRQ_LOOP 20
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/* #define DEBUG_IRQ*/
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/*
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* pointer to the mask representing the additionnal irq vectors
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* that must be disabled when a particular entry is activated.
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* They will be dynamically computed from the table given
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* in BSP_rtems_irq_mngt_set();
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* CAUTION : this table is accessed directly by interrupt routine
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* prologue.
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*/
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static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];
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/*
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* location used to store initial tables used for interrupt
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* management.BSP copy of the configuration
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*/
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static rtems_irq_global_settings BSP_config;
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static rtems_irq_connect_data* rtems_hdl_tbl;
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/*
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* default handler connected on each irq after bsp initialization
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* (locally cached copy)
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*/
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void (*default_rtems_hdl)(rtems_irq_hdl_param) = (void(*)(rtems_irq_hdl_param)) -1;
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static volatile unsigned *BSP_irqMask_reg[3];
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static volatile unsigned *BSP_irqCause_reg[3];
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static volatile unsigned BSP_irqMask_cache[3]={0,0,0};
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static int picPrioTblPtr=0;
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static unsigned int GPPIrqInTbl=0;
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static unsigned long long MainIrqInTbl=0;
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/*
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* The software developers are forbidden to setup picPrioTable[],
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* as it is a powerful engine for the BSP to find the pending
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* highest priority IRQ at run time. It ensures the fastest/faster
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* interrupt service to the highest/higher priority IRQ, if pendig.
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*
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* The picPrioTable[96] is updated dynamically at run time
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* based on the priority levels set at BSPirqPrioTable[96],
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* while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic()
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* commands are invoked.
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*
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* The picPrioTable[96] lists the enabled CPU main and GPP external interrupt
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* numbers [0 (lowest)- 95 (highest)] starting from the highest priority
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* one to the lowest priority one. The highest priority interrupt is
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* located at picPrioTable[0], and the lowest priority interrupt is located
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* at picPrioTable[picPrioTblPtr-1].
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*
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*
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*/
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#define DynamicIsrTable
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#ifdef DynamicIsrTable
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/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
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static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1 };
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#else
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static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={
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80, 84, 76, 77, 32, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1 };
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#endif
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/*
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* Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
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*/
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static inline int is_pic_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* Check if IRQ is a Porcessor IRQ
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*/
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static inline int is_processor_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
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);
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}
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/*
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* ------------------------ RTEMS Irq helper functions ----------------
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*/
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/*
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* Caution : this function assumes the variable "BSP_config"
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* is already set and that the tables it contains are still valid
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* and accessible.
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*/
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static void compute_pic_masks_from_prio(void)
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{
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int i,j, k, isGppMain;
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unsigned long long irq_prio_mask=0;
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/*
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* Always mask at least current interrupt to prevent re-entrance
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*/
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for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) {
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switch(i) {
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case BSP_MAIN_GPP7_0_IRQ:
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case BSP_MAIN_GPP15_8_IRQ:
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case BSP_MAIN_GPP23_16_IRQ:
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case BSP_MAIN_GPP31_24_IRQ:
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for (k=0; k< 3; k++)
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BSP_irq_prio_mask_tbl[k][i]=0;
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irq_prio_mask =0;
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isGppMain =1;
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break;
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default :
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isGppMain =0;
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irq_prio_mask = (unsigned long long) (1LLU << i);
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break;
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}
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if ( isGppMain) continue;
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for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
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/*
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* Mask interrupts at PIC level that have a lower priority
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* or <Till Straumann> a equal priority.
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*/
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if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
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irq_prio_mask |= (unsigned long long)(1LLU << j);
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}
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BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
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BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
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#if 0
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printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
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BSP_irq_prio_mask_tbl[0][i]);
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#endif
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BSP_irq_prio_mask_tbl[2][i] = 1<<i;
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/* Compute for the GPP priority interrupt mask */
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for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {
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if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
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BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET);
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}
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#if 0
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printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]);
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#endif
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}
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}
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static void UpdateMainIrqTbl(int irqNum)
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{
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int i=0, j, shifted=0;
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switch (irqNum) {
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case BSP_MAIN_GPP7_0_IRQ:
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case BSP_MAIN_GPP15_8_IRQ:
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case BSP_MAIN_GPP23_16_IRQ:
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case BSP_MAIN_GPP31_24_IRQ:
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return; /* Do nothing, let GPP take care of it */
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break;
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}
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#ifdef SHOW_MORE_INIT_SETTINGS
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unsigned long val2, val1;
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#endif
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/* If entry not in table*/
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if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
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(!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) ||
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((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
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(!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
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{
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|
while ( picPrioTable[i]!=-1) {
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if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) {
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/* all other lower priority entries shifted right */
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for (j=picPrioTblPtr;j>i; j--) {
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picPrioTable[j]=picPrioTable[j-1];
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}
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picPrioTable[i]=irqNum;
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shifted=1;
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break;
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|
}
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|
i++;
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|
}
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if (!shifted) picPrioTable[picPrioTblPtr] =irqNum;
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|
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if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
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GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
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|
else
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|
MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
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picPrioTblPtr++;
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|
}
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#ifdef SHOW_MORE_INIT_SETTINGS
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|
val2 = (MainIrqInTbl>>32) & 0xffffffff;
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val1 = MainIrqInTbl&0xffffffff;
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|
printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1);
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BSP_printPicIsrTbl();
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|
#endif
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|
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|
}
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|
|
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|
|
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|
static void CleanMainIrqTbl(int irqNum)
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|
{
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|
int i, j;
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|
|
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|
switch (irqNum) {
|
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|
case BSP_MAIN_GPP7_0_IRQ:
|
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|
case BSP_MAIN_GPP15_8_IRQ:
|
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|
case BSP_MAIN_GPP23_16_IRQ:
|
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|
case BSP_MAIN_GPP31_24_IRQ:
|
||||||
|
return; /* Do nothing, let GPP take care of it */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&
|
||||||
|
((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) ||
|
||||||
|
((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&
|
||||||
|
(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
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||||||
|
{ /* If entry in table*/
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||||||
|
for (i=0; i<64; i++) {
|
||||||
|
if (picPrioTable[i]==irqNum) {/*remove it from the entry */
|
||||||
|
/* all other lower priority entries shifted left */
|
||||||
|
for (j=i;j<picPrioTblPtr; j++) {
|
||||||
|
picPrioTable[j]=picPrioTable[j+1];
|
||||||
|
}
|
||||||
|
if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
|
||||||
|
GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
|
||||||
|
else
|
||||||
|
MainIrqInTbl &= ~(1LLU << irqNum);
|
||||||
|
picPrioTblPtr--;
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||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
|
||||||
|
{
|
||||||
|
unsigned bitNum, regNum;
|
||||||
|
unsigned int level;
|
||||||
|
|
||||||
|
if ( !is_pic_irq(irqNum) )
|
||||||
|
return;
|
||||||
|
|
||||||
|
bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
|
||||||
|
regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
|
||||||
|
|
||||||
|
rtems_interrupt_disable(level);
|
||||||
|
|
||||||
|
#ifdef DynamicIsrTable
|
||||||
|
UpdateMainIrqTbl((int) irqNum);
|
||||||
|
#endif
|
||||||
|
BSP_irqMask_cache[regNum] |= (1 << bitNum);
|
||||||
|
|
||||||
|
out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
|
||||||
|
while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
|
||||||
|
|
||||||
|
rtems_interrupt_enable(level);
|
||||||
|
}
|
||||||
|
|
||||||
|
void BSP_enable_pic_irq(const rtems_irq_number irqNum)
|
||||||
|
{
|
||||||
|
BSP_enable_irq_at_pic(irqNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
int BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
|
||||||
|
{
|
||||||
|
int rval;
|
||||||
|
unsigned bitNum, regNum;
|
||||||
|
unsigned int level;
|
||||||
|
|
||||||
|
if ( ! is_pic_irq(irqNum) )
|
||||||
|
return -1;
|
||||||
|
|
||||||
|
bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
|
||||||
|
regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
|
||||||
|
|
||||||
|
rtems_interrupt_disable(level);
|
||||||
|
|
||||||
|
#ifdef DynamicIsrTable
|
||||||
|
CleanMainIrqTbl((int) irqNum);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
rval = BSP_irqMask_cache[regNum] & (1<<bitNum);
|
||||||
|
|
||||||
|
BSP_irqMask_cache[regNum] &= ~(1 << bitNum);
|
||||||
|
|
||||||
|
out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
|
||||||
|
while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
|
||||||
|
|
||||||
|
rtems_interrupt_enable(level);
|
||||||
|
|
||||||
|
return rval ? 1 : 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void BSP_disable_pic_irq(const rtems_irq_number irqNum)
|
||||||
|
{
|
||||||
|
(void)BSP_disable_irq_at_pic(irqNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Use shared/irq : 2008 */
|
||||||
|
int BSP_setup_the_pic(rtems_irq_global_settings* config)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
BSP_config = *config;
|
||||||
|
default_rtems_hdl = config->defaultEntry.hdl;
|
||||||
|
rtems_hdl_tbl = config->irqHdlTbl;
|
||||||
|
|
||||||
|
/* Get ready for discovery BSP */
|
||||||
|
BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO);
|
||||||
|
BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI);
|
||||||
|
BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO);
|
||||||
|
BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI);
|
||||||
|
BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask);
|
||||||
|
BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value);
|
||||||
|
|
||||||
|
/* Page 401, Table 598:
|
||||||
|
* Comm Unit Arbiter Control register :
|
||||||
|
* bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
|
||||||
|
* MOTload default is set as level sensitive(1). Set it agin to make sure.
|
||||||
|
*/
|
||||||
|
out_le32(GT_CommUnitArb_Ctrl, (in_le32(GT_CommUnitArb_Ctrl)| (1<<10)));
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[0]),
|
||||||
|
in_le32(BSP_irqCause_reg[0]));
|
||||||
|
printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[1]),
|
||||||
|
in_le32(BSP_irqCause_reg[1]));
|
||||||
|
printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[2]),
|
||||||
|
in_le32(BSP_irqCause_reg[2]));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Initialize the interrupt related registers */
|
||||||
|
for (i=0; i<3; i++) {
|
||||||
|
out_le32(BSP_irqCause_reg[i], 0);
|
||||||
|
out_le32(BSP_irqMask_reg[i], 0);
|
||||||
|
}
|
||||||
|
in_le32(BSP_irqMask_reg[2]);
|
||||||
|
compute_pic_masks_from_prio();
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[0]),
|
||||||
|
in_le32(BSP_irqCause_reg[0]));
|
||||||
|
printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[1]),
|
||||||
|
in_le32(BSP_irqCause_reg[1]));
|
||||||
|
printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",
|
||||||
|
in_le32(BSP_irqMask_reg[2]),
|
||||||
|
in_le32(BSP_irqCause_reg[2]));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
|
||||||
|
if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) {
|
||||||
|
BSP_enable_irq_at_pic(i);
|
||||||
|
BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]);
|
||||||
|
BSP_disable_irq_at_pic(i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++)
|
||||||
|
BSP_enable_irq_at_pic(i);
|
||||||
|
|
||||||
|
return(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High level IRQ handler called from shared_raw_irq_code_entry
|
||||||
|
*/
|
||||||
|
int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
|
||||||
|
{
|
||||||
|
unsigned long irqCause[3]={0, 0,0};
|
||||||
|
unsigned oldMask[3]={0,0,0};
|
||||||
|
int loop=0, wloop=0, i=0, j;
|
||||||
|
int irq=0, group=0;
|
||||||
|
|
||||||
|
if (excNum == ASM_DEC_VECTOR) {
|
||||||
|
bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
|
||||||
|
for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);
|
||||||
|
|
||||||
|
while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP))
|
||||||
|
{
|
||||||
|
if (irqCause[group= irq/32] & ( 1<<(irq % 32))) {
|
||||||
|
for (j=0; j<3; j++)
|
||||||
|
BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
|
||||||
|
|
||||||
|
out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
|
||||||
|
out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
|
||||||
|
out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
|
||||||
|
in_le32(BSP_irqMask_reg[2]);
|
||||||
|
|
||||||
|
bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
|
||||||
|
|
||||||
|
for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
|
||||||
|
|
||||||
|
out_le32(BSP_irqMask_reg[0], oldMask[0]);
|
||||||
|
out_le32(BSP_irqMask_reg[1], oldMask[1]);
|
||||||
|
out_le32(BSP_irqMask_reg[2], oldMask[2]);
|
||||||
|
in_le32(BSP_irqMask_reg[2]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Only print part of the entries for now */
|
||||||
|
void BSP_printPicIsrTbl()
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
printf("picPrioTable[12]={ {irq# : ");
|
||||||
|
for (i=0; i<12; i++)
|
||||||
|
printf("%d,", picPrioTable[i]);
|
||||||
|
printf("}\n");
|
||||||
|
|
||||||
|
printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user