diff --git a/bsps/bfin/TLL6527M/README.md b/bsps/bfin/TLL6527M/README.md deleted file mode 100644 index e21059f0ff..0000000000 --- a/bsps/bfin/TLL6527M/README.md +++ /dev/null @@ -1,102 +0,0 @@ -TLL6527M -======== - -``` -BSP NAME: TLL6527M -BOARD: TLL6527M -CPU FAMILY: Blackfin -CPU: Blackfin 527 -MODE: 32 bit mode - -DEBUG MONITOR: -SIMULATOR: -``` - -PERIPHERALS ------------ - -``` -TIMERS: internal - RESOLUTION: 1 milisecond -SERIAL PORTS: 2 internal UART (polled/interrupt/dma) -REAL-TIME CLOCK: internal -DMA: internal -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: internal -TIMER DRIVER: internal -I2C: -SPI: -PPI: -SPORT: -``` - -STDIO ------ -``` -PORT: Console port 1 -ELECTRICAL: RS-232 -BAUD: 9600 -BITS PER CHARACTER: 8 -PARITY: None -STOP BITS: 1 -``` - -NOTES ------ -The TLL56527M board contains analog devices blackfin 527 processor. In addition -to the peripherals provided by bf527 the board has a temprature sensor, -accelerometer and power module connected via I2C. It also has LCD interface, -Card reader interface. - -The analog device bf52X family of processors are different from the bf53x range -of processors. This port supports the additional features that are not -supported by the blackfin 53X family of processors. - -The TLL6527M does not use the interrupt module used by the bfin 53x since it has -an additional system interrupt controller isr registers for additional lines. -On the 53X these line are multiplexed. -The centralized interrupt handler is implemented to use lookup tables for -jumping to the user ISR. For more details look at files implemented under -libcpu/bfin/bf52x/interrupt/* - -This port supports only the uart peripheral. The uart is supported via -polling, DMA, interrupt. The uart file is generic and is common between the -ports. Under bsp configure.ac files -* change the CONSOLE_BAUDRATE or to choose among different baudrate. -* Set UART_USE_DMA for UART to use DMA based transfers. In DMA based transfer - chunk of buffer is transmitted at once and then an interrupt is generated. -* Set CONSOLE_USE_INTERRUPTS to use interrupt based transfers. After every - character is transmitted an interrupt is generated. -* If CONSOLE_USE_INTERRUPTS, UART_USE_DMA are both not set then the port uses - polling to transmit data over uart. This call is blocking. - -TLL6527 specific file are mentioned below. -c/src/lib/libcpu/bfin/bf52x/* -c/src/lib/libbsp/bfin/TLL6527M/* - - -The port was compiled using ---------------------------- - 1. bfin-rtems4.11-gcc (GCC) 4.5.2 20101216 - (RTEMS gcc-4.5.2-3.el5/newlib-1.19.0-1.el5) - 2. automake (GNU automake) 1.11.1 - 3. autoconf (GNU Autoconf) 2.68 - - -The port was configured using the flags ---------------------------------------- ---target=bfin-rtems4.11 --enable-rtemsbsp=TLL6527M --enable-tests=samples ---disable-posix --disable-itron - - -ISSUES ------- -Could not place code in l1code (SRAM) because it was not being loaded by the -gnu loaded. diff --git a/bsps/bfin/TLL6527M/config/TLL6527M.cfg b/bsps/bfin/TLL6527M/config/TLL6527M.cfg deleted file mode 100644 index 8226543b89..0000000000 --- a/bsps/bfin/TLL6527M/config/TLL6527M.cfg +++ /dev/null @@ -1,19 +0,0 @@ -# -# Config file for Blackfin TLL6527M -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=bfin - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -# -CPU_CFLAGS =-mcpu=bf527 - -# optimize flag: typically -O2 -# gcc-4.2.0 segfaults on -OX > -O0 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/bfin/TLL6527M/console/console.c b/bsps/bfin/TLL6527M/console/console.c deleted file mode 100644 index b7de975220..0000000000 --- a/bsps/bfin/TLL6527M/console/console.c +++ /dev/null @@ -1,181 +0,0 @@ -/** - *@file - * - *@brief - * - This file implements uart console for TLL6527M. TLL6527M has BF527 with - * second uart (uart-1) connected to the console. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#include -#include -#include -#include -#include - -#include -#include - -/*************************************************** -LOCAL DEFINES - ***************************************************/ - - -/*************************************************** -STATIC GLOBALS - ***************************************************/ -/** - * Declaration of UART - */ -static bfin_uart_channel_t channels[] = { - {"/dev/console", - UART1_BASE_ADDRESS, - DMA10_BASE_ADDRESS, - DMA11_BASE_ADDRESS, - CONSOLE_USE_INTERRUPTS, - UART_USE_DMA, - CONSOLE_BAUDRATE, - NULL, - 0, - 0} -}; - -/** - * Over all configuration - */ -static bfin_uart_config_t config = { - SCLK, - sizeof(channels) / sizeof(channels[0]), - channels -}; - - -#if CONSOLE_USE_INTERRUPTS -/** - * The Rx and Tx isr will get the same argument - * The isr will have to find if it was the rx that caused the interrupt or - * the tx - */ -static bfin_isr_t bfinUARTISRs[] = { -#if UART_USE_DMA - /* For First uart */ - {IRQ_DMA10_UART1_RX, bfinUart_rxDmaIsr, (void *)&channels[0], 0}, - {IRQ_DMA11_UART1_TX, bfinUart_txDmaIsr, (void *)&channels[0], 0}, - /* For second uart */ -#else - /* For First uart */ - {IRQ_DMA10_UART1_RX, bfinUart_rxIsr, &channels[0], 0}, - {IRQ_DMA11_UART1_TX, bfinUart_txIsr, &channels[0], 0}, - /* For second uart */ -#endif -}; -#endif - - -static void TLL6527_BSP_output_char(char c) { - - bfin_uart_poll_write(0, c); -} - -static int TLL6527_BSP_poll_char(void) { - - return bfin_uart_poll_read(0); -} - -BSP_output_char_function_type BSP_output_char = TLL6527_BSP_output_char; -BSP_polling_getchar_function_type BSP_poll_char = TLL6527_BSP_poll_char; - - - -rtems_device_driver console_close(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_close(arg); -} - -rtems_device_driver console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_read(arg); -} - -rtems_device_driver console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_write(arg); -} - -rtems_device_driver console_control(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_ioctl(arg); -} - - - -/* - * Open entry point - */ -rtems_device_driver console_open(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return bfin_uart_open(major, minor, arg); -} - - - -/** - * - * This routine initializes the console IO driver. - * - * Parameters - * @param major major number - * @param minor minor number - * - * Output parameters: NONE - * - * @return void - */ -rtems_device_driver console_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - rtems_status_code status = RTEMS_NOT_DEFINED; -#if CONSOLE_USE_INTERRUPTS - int i = 0; -#endif - - status = bfin_uart_initialize(major, &config); - if (status != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(status); - } - -#if CONSOLE_USE_INTERRUPTS - for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) { - bfin_interrupt_register(&bfinUARTISRs[i]); -#if INTERRUPT_USE_TABLE -#else - bfin_interrupt_enable(&bfinUARTISRs[i], 1); -#endif - } -#endif - - return RTEMS_SUCCESSFUL; -} diff --git a/bsps/bfin/TLL6527M/include/bsp.h b/bsps/bfin/TLL6527M/include/bsp.h deleted file mode 100644 index daf1ebe333..0000000000 --- a/bsps/bfin/TLL6527M/include/bsp.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsBfinTLL6527M - * - * @brief Global BSP definitions. - * - * This include file contains all board IO definitions for TLL6527M. - */ - -/* - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - */ - -#ifndef LIBBSP_BFIN_TLL6527M_BSP_H -#define LIBBSP_BFIN_TLL6527M_BSP_H - -/** - * @defgroup RTEMSBSPsBfinTLL6527M TLL6527M - * - * @ingroup RTEMSBSPsBfin - * - * @brief TLL6527M Board Support Package. - * - * @{ - */ - -#ifndef ASM - -#include -#include - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * PLL and clock setup values: - */ - -/* - * PLL configuration for TLL6527M - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - */ - -/** - * @name PLL Configuration - * @{ - */ - -#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ -#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ -#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ - -/** @} */ - -/** - * @name Clock setup values - * @{ - */ - -#define CLKIN (25000000) ///< @brief Input clock to the PLL */ -#define CCLK (600000000) ///< @brief CORE CLOCK */ -#define SCLK (100000000) ///< @brief SYSTEM CLOCK */ - -/** @} */ - -/** - * @name UART setup values - * @{ - */ - -#define BAUDRATE 57600 ///< @brief Console Baudrate */ -#define WORD_5BITS 0x00 ///< @brief 5 bits word */ -#define WORD_6BITS 0x01 ///< @brief 6 bits word */ -#define WORD_7BITS 0x02 ///< @brief 7 bits word */ -#define WORD_8BITS 0x03 ///< @brief 8 bits word */ -#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ -#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ -#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ - -/** @} */ - -/** - * @brief Install an interrupt handler - * - * This method installs an interrupt handle. - * - * @param[in] handler is the isr routine - * @param[in] vector is the vector number - * @param[in] type indicates whether RTEMS or RAW intr - * - * @return returns old vector - */ -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Prototype for methods in .S files that are referenced from C. - */ -void bfin_null_isr(void); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/** @} */ - -#endif diff --git a/bsps/bfin/TLL6527M/include/bsp/irq.h b/bsps/bfin/TLL6527M/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/bfin/TLL6527M/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/bfin/TLL6527M/include/cplb.h b/bsps/bfin/TLL6527M/include/cplb.h deleted file mode 100644 index e5625771a3..0000000000 --- a/bsps/bfin/TLL6527M/include/cplb.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * @ingroup tll6527m_cplb - * @brief CPLB configurations. - */ - -/* cplb.h - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _CPLB_H -#define _CPLB_H - -/** - * @defgroup tll6527m_cplb CPLB Configuration - * @ingroup RTEMSBSPsBfinTLL6527M - * @brief CPLB Configuration - * @{ - */ - -/* CPLB configurations */ -#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT -#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL -#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY - -#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID -#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID - -#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL - -#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT -#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB - -/** @} */ - -#endif /* _CPLB_H */ diff --git a/bsps/bfin/TLL6527M/include/tm27.h b/bsps/bfin/TLL6527M/include/tm27.h deleted file mode 100644 index f192790a0f..0000000000 --- a/bsps/bfin/TLL6527M/include/tm27.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * @file - * @ingroup tll6527m_tm27 - * @brief Interrupt mechanisms for tm27 test. - */ - -/* - * tm27.h - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup tll6527m_tm27 TM27 Test Support - * @ingroup RTEMSBSPsBfinTLL6527M - * @brief Interrupt Mechanisms for TM27 - * @{ - */ - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define TM27_USE_VECTOR_HANDLER - -#define Install_tm27_vector(handler) \ -{ \ - set_vector( handler, 0x06, 1 ); \ -} - -#define Cause_tm27_intr() asm volatile("raise 0x06;" : :); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/** @} */ - -#endif diff --git a/bsps/bfin/TLL6527M/start/bspstart.c b/bsps/bfin/TLL6527M/start/bspstart.c deleted file mode 100644 index 4c8302a7ba..0000000000 --- a/bsps/bfin/TLL6527M/start/bspstart.c +++ /dev/null @@ -1,152 +0,0 @@ -/* bspstart.c for TLL6527M - * - * This routine does the bulk of the system initialization. - */ - -/* - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - */ - -#include -#include -#include -#include -#include -#include - -const unsigned int dcplbs_table[16][2] = { - { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, - { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */ - { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */ - { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, - - { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */ - { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2 */ - { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */ - { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */ - - { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - - { 0xffffffff, 0xffffffff }/* end of section - termination */ -}; - - -const unsigned int _icplbs_table[16][2] = { - { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, - /* L1 Code */ - { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */ - { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, - - { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */ - { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */ - { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */ - { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */ - - { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - - { 0xffffffff, 0xffffffff }/* end of section - termination */ -}; - -/* - * Init_PLL - * - * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL. - */ -static void Init_PLL (void) -{ - unsigned short msel = 0; - unsigned short ssel = 0; - - msel = (unsigned short)( (float)CCLK/(float)CLKIN ); - ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK); - - asm("cli r0;"); - - *((uint32_t*)SIC_IWR) = 0x1; - - /* Configure PLL registers */ - *((uint16_t*)PLL_DIV) = ssel; - msel = msel<<9; - *((uint16_t*)PLL_CTL) = msel; - - /* Commands to set PLL values */ - asm("idle;"); - asm("sti r0;"); -} - -/* - * Init_EBIU - * - * Configure extern memory - */ -static void Init_EBIU (void) -{ - /* Check if SDRAM is already enabled */ - if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){ - asm("ssync;"); - /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */ - *(uint16_t *)EBIU_SDRRC = 0x3F6; /* SHould have been 0x306*/ - *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M | - EBIU_SDBCTL_EBE; - *(uint32_t *)EBIU_SDGCTL = 0x8491998d; - asm("ssync;"); - } else { - /* SDRAm is already programmed */ - } -} - -/* - * Init_Flags - * - * Enable LEDs port - */ -static void Init_Flags(void) -{ - *((uint16_t*)PORTH_FER) = 0x0; - *((uint16_t*)PORTH_MUX) = 0x0; - *((uint16_t*)PORTHIO_DIR) = 0x1<<15; - *((uint16_t*)PORTHIO_SET) = 0x1<<15; -} - -RTEMS_SYSINIT_ITEM( - bfin_interrupt_init, - RTEMS_SYSINIT_BSP_PRE_DRIVERS, - RTEMS_SYSINIT_ORDER_MIDDLE -); - -void bsp_start( void ) -{ - int i; - - /* BSP Hardware Initialization*/ - Init_RTC(); /* Blackfin Real Time Clock initialization */ - Init_PLL(); /* PLL initialization */ - Init_EBIU(); /* EBIU initialization */ - Init_Flags(); /* GPIO initialization */ - - /* - * Allocate the memory for the RTEMS Work Space. This can come from - * a variety of places: hard coded address, malloc'ed from outside - * RTEMS world (e.g. simulator or primitive memory manager), or (as - * typically done by stock BSPs) by subtracting the required amount - * of work space from the last physical address on the CPU board. - */ - for (i=5;i<16;i++) { - set_vector((rtems_isr_entry)bfin_null_isr, i, 1); - } - -} diff --git a/bsps/bfin/TLL6527M/start/interrupt.c b/bsps/bfin/TLL6527M/start/interrupt.c deleted file mode 100644 index aa3f2c61ca..0000000000 --- a/bsps/bfin/TLL6527M/start/interrupt.c +++ /dev/null @@ -1,642 +0,0 @@ -/** - *@file - * - *@brief - * - This file implements interrupt dispatcher. Most of the code is taken from - * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR - * registers some portion is written twice. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#include -#include - -#include -#include -#include -#include -#include - -#define SIC_IAR_COUNT_SET0 4 -#define SIC_IAR_BASE_ADDRESS_0 0xFFC00150 - -/** - * There are two implementations for the interrupt handler. - * 1. INTERRUPT_USE_TABLE: uses tables for finding the right ISR. - * 2. Uses link list to find the user ISR. - * - * - * 1. INTERRUPT_USE_TABLE - * Space requirement: - * - Array to hold CEC masks size: CEC_INTERRUPT_COUNT(9)*(2*int).9*2*4= 72B - * - Array to hold isr function pointers IRQ_MAX(56)*sizeof(bfin_isr_t)= 896B - * - Array for bit twidlling 32 bytes. - * - Global Mask 8 bytes. - * - Total = 1008 Bytes Aprox - * - * Time requirements - * The worst case time is about the same for jumping to the user ISR. With a - * variance of one conditional statement. - * - * 2. Using link list. - * Space requirement: - * - Array to hold CEC mask CEC_INTERRUPT_COUNT(9)*(sizeof(vectors)). - * 9*3*4= 108B - * - Array to hold isr IRQ_MAX(56)*sizeof(bfin_isr_t) The structure has - * additional pointers 56*7*4=1568B - * - Global Mask 8 bytes. - * Total = 1684. - * Time requirements - * In the worst case all the lines can be on one CEC line to 56 entries have - * to be traversed to find the right user ISR. - * But this implementation has benefit of being flexible, Providing - * additional user assigned priority. and may consume less space - * if all devices are not supported. - */ - -/** - * TODO: To place the dispatcher routine code in L1. - */ - -#if INTERRUPT_USE_TABLE - - -/****************************************************************************** - * Static variables - *****************************************************************************/ -/** - * @var sic_isr0_mask - * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device - * the relevant SIC_ISRx bit is not cleared unless the interrupt - * service routine clears the mechanism that generated interrupt - */ -static uint32_t sic_isr0_mask = 0; - -/** - * @var sic_isr0_mask - * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device - * the relevant SIC_ISRx bit is not cleared unless the interrupt - * service routine clears the mechanism that generated interrupt - */ -static uint32_t sic_isr1_mask = 0; - - -/** - * @var sic_isr - * @brief An array of sic register mask for each of the 16 core interrupt lines - */ -static struct { - uint32_t mask0; - uint32_t mask1; -} vectors[CEC_INTERRUPT_COUNT]; - -/** - * @var ivt - * @brief Contains a table of ISR and arguments. The ISR jumps directly to - * these ISR. - */ -static bfin_isr_t ivt[IRQ_MAX]; - -/** - * http://graphics.stanford.edu/~seander/bithacks.html for more details - */ -static const char clz_table[32] = -{ - 0, 31, 9, 30, 3, 8, 18, 29, 2, 5, 7, 14, 12, 17, - 22, 28, 1, 10, 4, 19, 6, 15, 13, 23, 11, 20, 16, - 24, 21, 25, 26, 27 -}; - -/** - * finds the first bit set from the left. look at - * http://graphics.stanford.edu/~seander/bithacks.html for more details - * @param n - * @return - */ -static unsigned long clz(unsigned long n) -{ - unsigned long c = 0x7dcd629; /* magic constant... */ - - n |= (n >> 1); - n |= (n >> 2); - n |= (n >> 4); - n |= (n >> 8); - n |= (n >> 16); - if (n == 0) return 32; - n = c + (c * n); - return 31 - clz_table[n >> 27]; /* For little endian */ -} - - - -/** - * Centralized Interrupt dispatcher routine. This routine dispatches interrupts - * to the user ISR. The priority is according to the blackfin SIC. - * The first level of priority is handled in the hardware at the core event - * controller. The second level of interrupt is handled according to the line - * number that goes in to the SIC. - * * SIC_0 has higher priority than SIC 1. - * * Inside the SIC the priority is assigned according to the line number. - * Lower the line number higher the priority. - * - * In order to change the interrupt priority we may - * 1. change the SIC IAR registers or - * 2. Assign priority and extract it inside this function and call the ISR - * according tot the priority. - * - * @param vector IVG number. - * @return - */ -static rtems_isr interruptHandler(rtems_vector_number vector) { - uint32_t mask = 0; - int id = 0; - /** - * Enable for debugging - * - * static volatile uint32_t spurious_sic0 = 0; - * static volatile uint32_t spurious_source = 0; - * static volatile uint32_t spurious_sic1 = 0; - */ - - /** - * Extract the vector number relative to the SIC start line - */ - vector -= CEC_INTERRUPT_BASE_VECTOR; - - /** - * Check for bounds - */ - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - - /** - * Extract information and execute ISR from SIC 0 - */ - mask = *(uint32_t volatile *) SIC_ISR & - *(uint32_t volatile *) SIC_IMASK & vectors[vector].mask0; - id = clz(mask); - if ( SIC_ISR0_MAX > id ) { - /** Parameter check */ - if( NULL != ivt[id].pFunc) { - /** Call the relevant function with argument */ - ivt[id].pFunc( ivt[id].pArg ); - } else { - /** - * spurious interrupt we should not be getting this - * spurious_sic0++; - * spurious_source = id; - */ - } - } else { - /** - * we look at SIC 1 - */ - } - - - /** - * Extract information and execute ISR from SIC 1 - */ - mask = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & - *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) & - vectors[vector].mask1; - id = clz(mask)+SIC_ISR0_MAX; - if ( IRQ_MAX > id ) { - /** Parameter Check */ - if( NULL != ivt[id].pFunc ) { - /** Call the relevant function with argument */ - ivt[id].pFunc( ivt[id].pArg ); - } else { - /** - * spurious interrupt we should not be getting this - * - * spurious_sic1++; - * spurious_source = id; - */ - } - } else { - /** - * we continue - */ - } - - } -} - - - -/** - * This routine registers a new ISR. It will write a new entry to the IVT table - * @param isr contains a callback function and source - * @return rtems status code - */ -rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) { - rtems_interrupt_level isrLevel; - int id = 0; - int position = 0; - - /** - * Sanity Check - */ - if ( NULL == isr ){ - return RTEMS_UNSATISFIED; - } - - /** - * Sanity check. The register function should at least provide callback func - */ - if ( NULL == isr->pFunc ) { - return RTEMS_UNSATISFIED; - } - - id = isr->source; - - /** - * Parameter Check. We already have a function registered here. First - * unregister and then a new function can be allocated. - */ - if ( NULL != ivt[id].pFunc ) { - return RTEMS_UNSATISFIED; - } - - rtems_interrupt_disable(isrLevel); - /** - * Assign the new function pointer to the ISR Dispatcher - * */ - ivt[id].pFunc = isr->pFunc; - ivt[id].pArg = isr->pArg; - - - /** find out which isr mask has to be set to enable the interrupt */ - if ( SIC_ISR0_MAX > id ) { - sic_isr0_mask |= 0x1<source; - - rtems_interrupt_disable(isrLevel); - /** - * Assign the new function pointer to the ISR Dispatcher - * */ - ivt[id].pFunc = NULL; - ivt[id].pArg = NULL; - - - /** find out which isr mask has to be set to enable the interrupt */ - if ( SIC_ISR0_MAX > id ) { - sic_isr0_mask &= ~(0x1< i ) { - r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); - } else { - r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 + - ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH)); - } - - for (j = 0; j < 8; j++) { - vector = r & 0x0f; - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - /* install our local handler */ - if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){ - set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); - } - if ( SIC_ISR0_MAX > source ) { - vectors[vector].mask0 |= (1 << source); - } else { - vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX)); - } - } - r >>= 4; - source++; - } - } -} - - - - - -#else - -static struct { - uint32_t mask0; - uint32_t mask1; - bfin_isr_t *head; -} vectors[CEC_INTERRUPT_COUNT]; - -static uint32_t globalMask0; -static uint32_t globalMask1; - -static rtems_isr interruptHandler(rtems_vector_number vector) { - bfin_isr_t *isr = NULL; - uint32_t sourceMask0 = 0; - uint32_t sourceMask1 = 0; - rtems_interrupt_level isrLevel; - - rtems_interrupt_disable(isrLevel); - vector -= CEC_INTERRUPT_BASE_VECTOR; - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - isr = vectors[vector].head; - sourceMask0 = *(uint32_t volatile *) SIC_ISR & - *(uint32_t volatile *) SIC_IMASK; - sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & - *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH); - while (isr) { - if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) { - isr->isr(isr->_arg); - sourceMask0 = *(uint32_t volatile *) SIC_ISR & - *(uint32_t volatile *) SIC_IMASK; - sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) & - *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH); - } - isr = isr->next; - } - } - rtems_interrupt_enable(isrLevel); -} - -/** - * Initializes the interrupt module - */ -void bfin_interrupt_init(void) { - int source; - int vector; - uint32_t r; - int i; - int j; - - globalMask0 = ~(uint32_t) 0; - globalMask1 = ~(uint32_t) 0; - *(uint32_t volatile *) SIC_IMASK = 0; - *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0; - - memset(vectors, 0, sizeof(vectors)); - /* build mask0 showing what SIC sources drive each CEC vector */ - source = 0; - - /** - * The bf52x has 8 IAR registers but they do not have a constant pitch. - * - */ - for (i = 0; i < SIC_IAR_COUNT; i++) { - if ( SIC_IAR_COUNT_SET0 > i ) { - r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); - } else { - r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 + - ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH)); - } - for (j = 0; j < 8; j++) { - vector = r & 0x0f; - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - /* install our local handler */ - if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){ - set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); - } - if ( SIC_ISR0_MAX > source ) { - vectors[vector].mask0 |= (1 << source); - } else { - vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX)); - } - } - r >>= 4; - source++; - } - } -} - -/* modify SIC_IMASK based on ISR list for a particular CEC vector */ -static void setMask(uint32_t vector) { - bfin_isr_t *isr = NULL; - uint32_t mask = 0; - uint32_t r = 0; - - mask = 0; - isr = vectors[vector].head; - while (isr) { - mask |= isr->mask0; - isr = isr->next; - } - r = *(uint32_t volatile *) SIC_IMASK; - r &= ~vectors[vector].mask0; - r |= mask; - r &= globalMask0; - *(uint32_t volatile *) SIC_IMASK = r; - - - mask = 0; - isr = vectors[vector].head; - while (isr) { - mask |= isr->mask1; - isr = isr->next; - } - r = *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH); - r &= ~vectors[vector].mask1; - r |= mask; - r &= globalMask1; - *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH) = r; -} - -/* add an ISR to the list for whichever vector it belongs to */ -rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) { - bfin_isr_t *walk; - rtems_interrupt_level isrLevel; - - /* find the appropriate vector */ - for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++) - if ( (vectors[isr->vector].mask0 & (1 << isr->source) ) || \ - (vectors[isr->vector].mask1 & (1 << (isr->source - SIC_ISR0_MAX)) )) - break; - if (isr->vector < CEC_INTERRUPT_COUNT) { - isr->next = NULL; - isr->mask0 = 0; - isr->mask1 = 0; - rtems_interrupt_disable(isrLevel); - /* find the current end of the list */ - walk = vectors[isr->vector].head; - while (walk && walk->next) - walk = walk->next; - /* append new isr to list */ - if (walk) - walk->next = isr; - else - vectors[isr->vector].head = isr; - rtems_interrupt_enable(isrLevel); - } else - /* we failed, but make vector a legal value so other calls into - this module with this isr descriptor won't do anything bad */ - isr->vector = 0; - return RTEMS_SUCCESSFUL; -} - -rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) { - bfin_isr_t *walk, *prev; - rtems_interrupt_level isrLevel; - - rtems_interrupt_disable(isrLevel); - walk = vectors[isr->vector].head; - prev = NULL; - /* find this isr in our list */ - while (walk && walk != isr) { - prev = walk; - walk = walk->next; - } - if (walk) { - /* if found, remove it */ - if (prev) - prev->next = walk->next; - else - vectors[isr->vector].head = walk->next; - /* fix up SIC_IMASK if necessary */ - setMask(isr->vector); - } - rtems_interrupt_enable(isrLevel); - return RTEMS_SUCCESSFUL; -} - -void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) { - rtems_interrupt_level isrLevel; - - rtems_interrupt_disable(isrLevel); - if ( SIC_ISR0_MAX > isr->source ) { - isr->mask0 = enable ? (1 << isr->source) : 0; - *(uint32_t volatile *) SIC_IMASK |= isr->mask0; - } else { - isr->mask1 = enable ? (1 << (isr->source - SIC_ISR0_MAX)) : 0; - *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= isr->mask1; - } - - //setMask(isr->vector); - rtems_interrupt_enable(isrLevel); -} - -void bfin_interrupt_enable_all(int source, bool enable) { - rtems_interrupt_level isrLevel; - int vector; - bfin_isr_t *walk; - - for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) - if ( (vectors[vector].mask0 & (1 << source) ) || \ - (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) )) - break; - if (vector < CEC_INTERRUPT_COUNT) { - rtems_interrupt_disable(isrLevel); - walk = vectors[vector].head; - while (walk) { - walk->mask0 = enable ? (1 << source) : 0; - walk = walk->next; - } - - walk = vectors[vector].head; - while (walk) { - walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0; - walk = walk->next; - } - setMask(vector); - rtems_interrupt_enable(isrLevel); - } -} - -void bfin_interrupt_enable_global(int source, bool enable) { - int vector; - rtems_interrupt_level isrLevel; - - for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) - if ( (vectors[vector].mask0 & (1 << source) ) || \ - (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) )) - break; - if (vector < CEC_INTERRUPT_COUNT) { - rtems_interrupt_disable(isrLevel); - if ( SIC_ISR0_MAX > source ) { - if (enable) - globalMask0 |= 1 << source; - else - globalMask0 &= ~(1 << source); - }else { - if (enable) - globalMask1 |= 1 << (source - SIC_ISR0_MAX); - else - globalMask1 &= ~(1 << (source - SIC_ISR0_MAX)); - } - setMask(vector); - rtems_interrupt_enable(isrLevel); - } -} - -#endif diff --git a/bsps/bfin/TLL6527M/start/linkcmds b/bsps/bfin/TLL6527M/start/linkcmds deleted file mode 100644 index 6e005ee271..0000000000 --- a/bsps/bfin/TLL6527M/start/linkcmds +++ /dev/null @@ -1,184 +0,0 @@ -OUTPUT_FORMAT("elf32-bfin", "elf32-bfin", - "elf32-bfin") - -OUTPUT_ARCH(bfin) -ENTRY(__start) -STARTUP(start.o) - -/* - * Declare some sizes. - */ -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0; -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x04000000; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000; - -MEMORY -{ - sdram(rwx) : ORIGIN = 0x00000100, LENGTH = 0x04000000 - - l1dataA(rwx) : ORIGIN = 0xff800000, LENGTH = 0x00004000 - l1dataAC(rwx) : ORIGIN = 0xff804000, LENGTH = 0x00004000 - l1dataB(rwx) : ORIGIN = 0xff900000, LENGTH = 0x00004000 - l1dataBC(rwx) : ORIGIN = 0xff904000, LENGTH = 0x00004000 - - l1code(rwx) : ORIGIN = 0xffa00000, LENGTH = 0x0000C000 - l1codeC(rwx) : ORIGIN = 0xffa10000, LENGTH = 0x00004000 - scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000 -} - -SECTIONS -{ - - .init : - { - *(.l1code) - KEEP (*(.init)) - } > sdram /*=0*/ - - .text : - { - CREATE_OBJECT_SYMBOLS - *(.text) - *(.rodata*) - *(.gnu.linkonce.r*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysctl_*); - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - _etext = .; - - ___CTOR_LIST__ = .; - LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - ___CTOR_END__ = .; - ___DTOR_LIST__ = .; - LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - ___DTOR_END__ = .; - } > sdram - - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > sdram - - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > sdram - - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .fini : - { - KEEP (*(.fini)) - } > sdram /*=0*/ - - .data : - { - *(.data) - KEEP (*(SORT(.rtemsrwset.*))) - *(.jcr) - *(.gnu.linkonce.d*) - CONSTRUCTORS - _edata = .; - } > sdram - - .eh_frame : { *(.eh_frame) } > sdram - .data1 : { *(.data1) } > sdram - .eh_frame : { *(.eh_frame) } > sdram - .gcc_except_table : { *(.gcc_except_table*) } > sdram - - .rodata : - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - } > sdram - - - .bss : - { - _bss_start = .; - _clear_start = .; - *(.bss) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (64); - _clear_end = .; - _end = .; - __end = .; - } > sdram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > sdram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - _WorkAreaBase = .; - } > sdram - -/* Debugging stuff follows */ - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} - -__HeapSize = _HeapSize; -__edata = _edata; -__etext = _etext; - diff --git a/bsps/bfin/bf537Stamp/README.md b/bsps/bfin/bf537Stamp/README.md deleted file mode 100644 index dd72cf5154..0000000000 --- a/bsps/bfin/bf537Stamp/README.md +++ /dev/null @@ -1,43 +0,0 @@ -bf537Stamp -========== -``` -BSP NAME: bf537Stamp -BOARD: ADZS-BF537-STAMP -CPU FAMILY: Blackfin -CPU: Blackfin 537 -MODE: 32 bit mode - -DEBUG MONITOR: ICEBear -SIMULATOR: Skyeye -``` - -PERIPHERALS ------------ -``` -TIMERS: internal - RESOLUTION: 1 milisecond -SERIAL PORTS: internal UART (polled/interrupt) -REAL-TIME CLOCK: internal -DMA: internal -VIDEO: none -SCSI: none -NETWORKING: internal -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: internal -TIMER DRIVER: internal -``` - -STDIO ------ -``` -PORT: Console port 0 -ELECTRICAL: RS-232 -BAUD: 57600 -BITS PER CHARACTER: 8 -PARITY: None -STOP BITS: 1 -``` diff --git a/bsps/bfin/bf537Stamp/config/bf537Stamp.cfg b/bsps/bfin/bf537Stamp/config/bf537Stamp.cfg deleted file mode 100644 index e27a7d31a1..0000000000 --- a/bsps/bfin/bf537Stamp/config/bf537Stamp.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# Config file for Blackfin bf537Stamp -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=bfin - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = - -# optimize flag: typically -O2 -# gcc-4.2.0 segfaults on -OX > -O0 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/bfin/bf537Stamp/console/console.c b/bsps/bfin/bf537Stamp/console/console.c deleted file mode 100644 index e9fe24cda1..0000000000 --- a/bsps/bfin/bf537Stamp/console/console.c +++ /dev/null @@ -1,141 +0,0 @@ -/* Console driver for bf537Stamp - */ - -/* - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* -#undef CONSOLE_USE_INTERRUPTS -#define CONSOLE_USE_INTERRUPTS 1 -*/ - -static bfin_uart_channel_t channels[] = { - {"/dev/console", - UART0_BASE_ADDRESS, - 0, - 0, - CONSOLE_USE_INTERRUPTS, - 0, - #ifdef CONSOLE_FORCE_BAUD - CONSOLE_FORCE_BAUD, - #else - 0, - #endif - NULL, - 0, - 0} - -#if (!BFIN_ON_SKYEYE) -, - {"/dev/tty1", - UART1_BASE_ADDRESS, - CONSOLE_USE_INTERRUPTS, - 0, - NULL, - 0} -#endif -}; - -static bfin_uart_config_t config = { - SCLK, - sizeof(channels) / sizeof(channels[0]), - channels -}; - -#if CONSOLE_USE_INTERRUPTS -static bfin_isr_t bfinUARTISRs[] = { - {SIC_DMA8_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL}, - {SIC_DMA10_UART1_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL}, - {SIC_DMA9_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL}, - {SIC_DMA11_UART1_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL} -}; -#endif - - -static void bf537Stamp_BSP_output_char(char c) { - - bfin_uart_poll_write(0, c); -} - -static int bf537Stamp_BSP_poll_char(void) { - - return bfin_uart_poll_read(0); -} - -BSP_output_char_function_type BSP_output_char = bf537Stamp_BSP_output_char; -BSP_polling_getchar_function_type BSP_poll_char = bf537Stamp_BSP_poll_char; - -rtems_device_driver console_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - rtems_status_code status; -#if CONSOLE_USE_INTERRUPTS - int i; -#endif - - status = bfin_uart_initialize(major, &config); -#if CONSOLE_USE_INTERRUPTS - for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) { - bfin_interrupt_register(&bfinUARTISRs[i]); - bfin_interrupt_enable(&bfinUARTISRs[i], TRUE); - } -#endif - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver console_open(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return bfin_uart_open(major, minor, arg); -} - -rtems_device_driver console_close(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_close(arg); -} - -rtems_device_driver console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_read(arg); -} - -rtems_device_driver console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_write(arg); -} - -rtems_device_driver console_control(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_ioctl(arg); -} - diff --git a/bsps/bfin/bf537Stamp/include/bsp.h b/bsps/bfin/bf537Stamp/include/bsp.h deleted file mode 100644 index 5b55ecf325..0000000000 --- a/bsps/bfin/bf537Stamp/include/bsp.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsBfinBF537Stamp - * - * @brief Global BSP definitions. - */ - -/* bsp.h - * - * This include file contains all board IO definitions for bf537Stamp. - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef LIBBSP_BFIN_BF537STAMP_BSP_H -#define LIBBSP_BFIN_BF537STAMP_BSP_H - -/** - * @defgroup RTEMSBSPsBfinBF537Stamp BF537-STAMP - * - * @ingroup RTEMSBSPsBfin - * - * @brief BF537-STAMP Board Support Package. - * - * @{ - */ - -#ifndef ASM - -#include -#include - -#include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* configure data cache to use 16K of each SRAM bank when enabled */ -#define BSP_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT) - - -/* - * PLL and clock setup values: - */ - -/* - * PLL configuration for bf533Stamp - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - */ - -#define PLL_CSEL 0x0000 /* CCLK = VCO */ -#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */ -#define PLL_DF 0x0001 /* CLKIN = XTL/2 */ - -#define CCLK 500000000 /* CORE CLOCK */ -#define SCLK 100000000 /* SYSTEM CLOCK */ - -#define CONSOLE_FORCE_BAUD 57600 - -/* - * Blackfin environment memory map - */ -#define L1_DATA_SRAM_A 0xff800000L - -#define FIFOLENGTH 0x100 - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define rtems_bsp_delay( microseconds ) \ - { \ - } - -/* Constants */ - -#define RAM_START 0 -#define RAM_END 0x4000000 - -/* functions */ - -/* - * Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLED(uint8_t value); - -/* - * Helper Function to use the EzKits LEDS - */ -uint8_t getLEDs(void); -void setLEDs(uint8_t value); -uint8_t getButtons(void); - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Network driver configuration - */ -struct rtems_bsdnet_ifconfig; -extern int bf537Stamp_network_driver_attach(struct rtems_bsdnet_ifconfig *, int); - -#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth1" -#define RTEMS_BSP_NETWORK_DRIVER_ATTACH bf537Stamp_network_driver_attach - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/* @} */ - -#endif diff --git a/bsps/bfin/bf537Stamp/include/bsp/irq.h b/bsps/bfin/bf537Stamp/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/bfin/bf537Stamp/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/bfin/bf537Stamp/include/tm27.h b/bsps/bfin/bf537Stamp/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/bsps/bfin/bf537Stamp/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/bfin/bf537Stamp/start/bspstart.c b/bsps/bfin/bf537Stamp/start/bspstart.c deleted file mode 100644 index ffc2d950c7..0000000000 --- a/bsps/bfin/bf537Stamp/start/bspstart.c +++ /dev/null @@ -1,229 +0,0 @@ -/* bspstart.c for bf537Stamp - * - * This routine does the bulk of the system initialisation. - */ - -/* - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static bfin_mmu_config_t mmuRegions = { - /* instruction */ - { - {(void *) 0x00000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x00400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x00800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x00c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x01000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x01400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x01800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x01c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x02000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x02400000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x02800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x02c00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x03000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0x20000000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_CACHEABLE}, - {(void *) 0xff800000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE}, - {(void *) 0xffc00000, ICPLB_DATA_PAGE_SIZE_4MB | INSTR_NOCACHE} - }, - /* data */ - { - {(void *) 0x00000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x00400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x00800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x00c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x01000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x01400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x01800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x01c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x02000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x02400000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x02800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x02c00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x03000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0x20000000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_WRITEBACK}, - {(void *) 0xff800000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE}, - {(void *) 0xffc00000, DCPLB_DATA_PAGE_SIZE_4MB | DATA_NOCACHE} - } -}; - -static void initPLL(void); -static void initEBIU(void); -static void initGPIO(void); - -RTEMS_SYSINIT_ITEM( - bfin_interrupt_init, - RTEMS_SYSINIT_BSP_PRE_DRIVERS, - RTEMS_SYSINIT_ORDER_MIDDLE -); - -void bsp_start(void) -{ - /* BSP Hardware Initialization*/ - - *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_PORT_PREF0; - *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_PORT_PREF1; - bfin_mmu_init(&mmuRegions); - rtems_cache_enable_instruction(); - rtems_cache_enable_data(); - - Init_RTC(); /* Blackfin Real Time Clock initialization */ - - initPLL(); /* PLL initialization */ - initEBIU(); /* EBIU initialization */ - initGPIO(); /* GPIO initialization */ -} - - /* - * initPLL - * - * Routine to initialize the PLL. The BF537 Stamp uses a 27 Mhz XTAL. BISON - * See "../bf537Stamp/include/bsp.h" for more information. - */ - -static void initPLL(void) { - -#ifdef BISON - unsigned int n; - - /* Configure PLL registers */ - *((uint16_t*)PLL_LOCKCNT) = 0x1000; - *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL; - *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF; - - /* Commands to set PLL values */ - __asm__ ("cli r0;"); - __asm__ ("idle;"); - __asm__ ("sti r0;"); - - /* Delay for PLL stabilization */ - for (n=0; n<200; n++) {} -#endif - -} - - /* - * initEBIU - * - * Configure extern memory - */ - -static void initEBIU(void) { - - /* by default the processor has priority over dma channels for access to - external memory. this has been seen to result in dma unerruns on - ethernet transmit; it seems likely it could cause dma overruns on - ethernet receive as well. setting the following bit gives the dma - channels priority over the cpu, fixing that problem. unfortunately - we don't have finer grain control than that; all dma channels now - have priority over the cpu. */ - *(uint16_t volatile *) EBIU_AMGCTL |= EBIU_AMGCTL_CDPRIO; - -#ifdef BISON - /* Configure FLASH */ - *((uint32_t*)EBIU_AMBCTL0) = 0x7bb07bb0L; - *((uint32_t*)EBIU_AMBCTL1) = 0x7bb07bb0L; - *((uint16_t*)EBIU_AMGCTL) = 0x000f; - - /* Configure SDRAM - *((uint32_t*)EBIU_SDGCTL) = 0x0091998d; - *((uint16_t*)EBIU_SDBCTL) = 0x0013; - *((uint16_t*)EBIU_SDRRC) = 0x0817; - */ -#endif -} - - /* - * initGPIO - * - * Enable LEDs port - */ -static void initGPIO(void) { -#if (!BFIN_ON_SKYEYE) - *(uint16_t volatile *) PORT_MUX = 0; - - /* port f bits 0, 1: uart0 tx, rx */ - /* bits 2 - 5: buttons */ - /* bits 6 - 11: leds */ - *(uint16_t volatile *) PORTF_FER = 0x0003; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x003c; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0fc0; - - *(uint16_t volatile *) PORTG_FER = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTGIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000; - - /* port h bits 0 - 15: ethernet */ - *(uint16_t volatile *) PORTH_FER = 0xffff; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_INEN_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_POLAR_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_EDGE_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_BOTH_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKA_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_MASKB_OFFSET) = 0x0000; - *(uint16_t volatile *) (PORTHIO_BASE_ADDRESS + PORTIO_DIR_OFFSET) = 0x0000; -#endif -} - -/* - * Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLEDs(uint8_t value) { - - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_CLEAR_OFFSET) = - (uint16_t) (~value & 0x3f) << 6; - *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_SET_OFFSET) = - (uint16_t) (value & 0x3f) << 6; -} - -/* - * Helper Function to use the EzKits LEDS - */ -uint8_t getLEDs(void) { - uint16_t r; - - r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET); - return (uint8_t) ((r >> 6) & 0x3f); -} - -uint8_t getButtons(void) { - uint16_t r; - - r = *(uint16_t volatile *) (PORTFIO_BASE_ADDRESS + PORTIO_OFFSET); - - return (uint8_t) ((r >> 2) & 0x0f); -} - - diff --git a/bsps/bfin/bf537Stamp/start/linkcmds b/bsps/bfin/bf537Stamp/start/linkcmds deleted file mode 100644 index 32899e19fa..0000000000 --- a/bsps/bfin/bf537Stamp/start/linkcmds +++ /dev/null @@ -1,192 +0,0 @@ -OUTPUT_FORMAT("elf32-bfin", "elf32-bfin", - "elf32-bfin") - -OUTPUT_ARCH(bfin) -ENTRY(__start) -STARTUP(start.o) - -/* - * Declare some sizes. - */ -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0; -/* bf537stamp has 64MB ram, but dynamic mmu tables have not yet been - implemented. there are not enough static entries to support 64MB - along with banks for io and flash, so waste some RAM at the end - to free up mmu entries. */ -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x03400000; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - sdram(rwx) : ORIGIN = 0x00001000, LENGTH = 0x03fff000 -/* - l1code(rwx) : ORIGIN = 0xffa08000, LENGTH = 0x00008000 - l1data(rwx) : ORIGIN = 0xff804000, LENGTH = 0x00004000 -*/ -} - -SECTIONS -{ - -/* - .l1code : - { -*/ - /*jump.o (.text)*/ -/* - } > l1code -*/ - - .init : - { - *(.start) - KEEP (*(.init)) - } > sdram /*=0*/ - - .text : - { - CREATE_OBJECT_SYMBOLS - *(.text) - *(.rodata*) - *(.gnu.linkonce.r*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysctl_*); - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - _etext = .; - - ___CTOR_LIST__ = .; - LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - ___CTOR_END__ = .; - ___DTOR_LIST__ = .; - LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - ___DTOR_END__ = .; - } > sdram - - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > sdram - - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > sdram - - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .fini : - { - KEEP (*(.fini)) - } > sdram /*=0*/ - - .data : - { - *(.data) - KEEP (*(SORT(.rtemsrwset.*))) - *(.jcr) - *(.gnu.linkonce.d*) - CONSTRUCTORS - _edata = .; - } > sdram - - .eh_frame : { *(.eh_frame) } > sdram - .data1 : { *(.data1) } > sdram - .eh_frame : { *(.eh_frame) } > sdram - .gcc_except_table : { *(.gcc_except_table*) } > sdram - - .rodata : - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - } > sdram - - - .bss : - { - _bss_start = .; - _clear_start = .; - *(.bss) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (64); - _clear_end = .; - _end = .; - __end = .; - } > sdram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > sdram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - _WorkAreaBase = .; - } > sdram - -/* Debugging stuff follows */ - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} - -__RamBase = _RamBase; -__RamSize = _RamSize; -__edata = _edata; -__etext = _etext; diff --git a/bsps/bfin/bf537Stamp/start/start.S b/bsps/bfin/bf537Stamp/start/start.S deleted file mode 100644 index cc6c7c62fb..0000000000 --- a/bsps/bfin/bf537Stamp/start/start.S +++ /dev/null @@ -1,115 +0,0 @@ -#include -#include -#include -#include -#include - -#ifndef LO -#define LO(con32) ((con32) & 0xFFFF) -#endif -#ifndef HI -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#endif - - .section .start - .align 4 - - .global __start -__start: - cli r0; - - /* setup an initial stack */ - sp.h = __ISR_Stack_area_end; - sp.l = __ISR_Stack_area_end; - - /* disable timer interrupts */ - p0.h = HI(TCNTL); - p0.l = LO(TCNTL); - r0 = 0; - [p0] = r0; - - /* disable all interrupts routed through sic */ - p0.h = HI(SIC_IMASK); - p0.l = LO(SIC_IMASK); - [p0] = r0; - - /* clear any pending interrupts */ - p0.h = HI(CEC_ILAT); - p0.l = LO(CEC_ILAT); - r0 = 0xffff (z); - [p0] = r0; - - /* disable all dma channels */ - p0.h = HI(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET); - p0.l = LO(DMA0_BASE_ADDRESS + DMA_CONFIG_OFFSET); - p1 = DMA_PITCH; - p2 = DMA_CHANNELS; - r0 = ~DMA_CONFIG_DMAEN; - lsetup(loop1,loop2) lc0 = p2; -loop1: r1 = w[p0]; - r1 = r0 & r1; -loop2: w[p0 ++ p1] = r1.l; - - /* this is so we can stay in supervisor mode and still be able to - accept interrupts later. */ - p0.h = start; - p0.l = start; - p1.h = HI(CEC_EVT15); - p1.l = LO(CEC_EVT15); - - [p1] = p0; - - r0 = 0x8000 (z); - sti r0; - - raise 15; - - p0.h = wait; - p0.l = wait; - - reti = p0; - rti; - - /* wait for event 15 */ -wait: - jump wait; - -start: - [--sp] = reti; /* allow us to process interrupts later */ - - /* mask interrupts for now */ - cli r0; - - p0.h = _bss_start; - p0.l = _bss_start; - p1.h = _end; - p1.l = _end; - r0 = p0; - r1 = p1; - r1 = r1 - r0; - p1 = r1; - r0 = 0; - - /* Set _bss_start until _end to zero */ - lsetup(loop3,loop4) lc0 = p1; -loop3: b[p0] = r0; -loop4: p0 +=1; - - l0 = 0; - l1 = 0; - l2 = 0; - l3 = 0; - sp += -12; - /* r0 == const char *cmdline (currently null) */ - p0.h = _boot_card; - p0.l = _boot_card; - call (p0); - sp += 12; - - .global _bsp_reset -_bsp_reset: - HLT - p0.h = _exit; - p0.l = _exit; - jump (p0); - diff --git a/bsps/bfin/eZKit533/README.md b/bsps/bfin/eZKit533/README.md deleted file mode 100644 index 741b447367..0000000000 --- a/bsps/bfin/eZKit533/README.md +++ /dev/null @@ -1,43 +0,0 @@ -eZKit533 -======== -``` -BSP NAME: eZKit533 -BOARD: ADSP-BF533 EzKit Lite -CPU FAMILY: Blackfin -CPU: Blackfin 533 -MODE: 32 bit mode - -DEBUG MONITOR: ICEBear -SIMULATOR: Skyeye -``` - -PERIPHERALS ------------ -``` -TIMERS: internal - RESOLUTION: 1 milisecond -SERIAL PORTS: internal UART (polled/interrupt) -REAL-TIME CLOCK: internal -DMA: internal -VIDEO: none -SCSI: none -NETWORKING: none -``` - -DRIVER INFORMATION ------------------- -``` -CLOCK DRIVER: internal -TIMER DRIVER: internal -``` - -STDIO ------ -``` -PORT: Console port 0 -ELECTRICAL: RS-232 -BAUD: 57600 -BITS PER CHARACTER: 8 -PARITY: None -STOP BITS: 1 -``` diff --git a/bsps/bfin/eZKit533/config/eZKit533.cfg b/bsps/bfin/eZKit533/config/eZKit533.cfg deleted file mode 100644 index 834039d985..0000000000 --- a/bsps/bfin/eZKit533/config/eZKit533.cfg +++ /dev/null @@ -1,18 +0,0 @@ -# -# Config file for Blackfin eZKit533 -# - -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU=bfin - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -# -CPU_CFLAGS = - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -g -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections - -LDFLAGS = -Wl,--gc-sections diff --git a/bsps/bfin/eZKit533/console/console-io.c b/bsps/bfin/eZKit533/console/console-io.c deleted file mode 100644 index 5bafb3a094..0000000000 --- a/bsps/bfin/eZKit533/console/console-io.c +++ /dev/null @@ -1,126 +0,0 @@ -/* console-io.c - * - * This file contains the hardware specific portions of the TTY driver - * for the serial ports for ezkit533. - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include -#include -#include - -#include -#include -#include - -static bfin_uart_channel_t channels[] = { - {"/dev/console", - UART0_BASE_ADDRESS, - 0, - 0, - CONSOLE_USE_INTERRUPTS, - 0, -#ifdef CONSOLE_FORCE_BAUD - CONSOLE_FORCE_BAUD, -#else - 0, -#endif - NULL, - 0, - 0} -}; - -static bfin_uart_config_t config = { - SCLK, - sizeof(channels) / sizeof(channels[0]), - channels -}; - -#if CONSOLE_USE_INTERRUPTS -static bfin_isr_t bfinUARTISRs[] = { - {SIC_DMA6_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL}, - {SIC_DMA7_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL}, -}; -#endif - - -static void eZKit533_BSP_output_char(char c) { - - bfin_uart_poll_write(0, c); -} - -static int eZKit533_BSP_poll_char(void) { - - return bfin_uart_poll_read(0); -} - -BSP_output_char_function_type BSP_output_char = eZKit533_BSP_output_char; -BSP_polling_getchar_function_type BSP_poll_char = eZKit533_BSP_poll_char; - -rtems_device_driver console_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - rtems_status_code status; -#if CONSOLE_USE_INTERRUPTS - int i; -#endif - - status = bfin_uart_initialize(major, &config); -#if CONSOLE_USE_INTERRUPTS - for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) { - bfin_interrupt_register(&bfinUARTISRs[i]); - bfin_interrupt_enable(&bfinUARTISRs[i], TRUE); - } -#endif - - if (status != RTEMS_SUCCESSFUL) - rtems_fatal_error_occurred(status); - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver console_open(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return bfin_uart_open(major, minor, arg); -} - -rtems_device_driver console_close(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_close(arg); -} - -rtems_device_driver console_read(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_read(arg); -} - -rtems_device_driver console_write(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_write(arg); -} - -rtems_device_driver console_control(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) { - - return rtems_termios_ioctl(arg); -} - diff --git a/bsps/bfin/eZKit533/include/bsp.h b/bsps/bfin/eZKit533/include/bsp.h deleted file mode 100644 index 27498b1442..0000000000 --- a/bsps/bfin/eZKit533/include/bsp.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsBfinEZKit533 - * - * @brief Global BSP definitions. - * - * This include file contains all board IO definitions for TLL6527M. - */ - -/* bsp.h - * - * This include file contains all board IO definitions for eZKit533. - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef LIBBSP_BFIN_EZKIT533_BSP_H -#define LIBBSP_BFIN_EZKIT533_BSP_H - -#ifndef ASM - -#include - -#include -#include - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup RTEMSBSPsBfinEZKit533 BF533 EZ-KIT - * - * @ingroup RTEMSBSPsBfin - * - * @brief BF533 EZ-KIT Board Support Package. - * - * @{ - */ - -/** - * @name PLL and clock setup values: - * @brief PLL configuration for ezkit533 - * - * XTL = 27 MHz - * CLKIN = 13 MHz - * VCO = 391 MHz - * CCLK = 391 MHz - * SCLK = 130 MHz - * - * @{ - * - */ - -#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ -#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ -#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ - -#define CCLK 391000000 ///< @brief CORE CLOCK */ -#define SCLK 130000000 ///< @brief SYSTEM CLOCK */ - -/** @} */ - -/** - * @name UART setup values - * @{ - */ - -#define BAUDRATE 57600 ///< @brief Console Baudrate */ -#define WORD_5BITS 0x00 ///< @brief 5 bits word */ -#define WORD_6BITS 0x01 ///< @brief 6 bits word */ -#define WORD_7BITS 0x02 ///< @brief 7 bits word */ -#define WORD_8BITS 0x03 ///< @brief 8 bits word */ -#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ -#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ -#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ - -/** @} */ - -/** - * @name Ezkit flash ports - * @{ - */ - -#define FlashA_PortB_Dir 0x20270007L -#define FlashA_PortB_Data 0x20270005L - -/** @} */ - -/** - * @brief Blackfin environment memory map - */ -#define L1_DATA_SRAM_A 0xff800000L - -#define FIFOLENGTH 0x100 - -/** - * @name Constants - * @{ - */ - -#define RAM_START 0 -#define RAM_END 0x100000 - -/** @} */ - -/** - * @name functions - * @{ - */ - -/** - * @brief Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLED (uint8_t value); - -/** - * @brief Helper Function to use the EzKits LEDS - */ -uint8_t getLED (void); - -/** - * @brief Install an interrupt handler - * - * This method installs an interrupt handle. - * - * @param[in] handler is the isr routine - * @param[in] vector is the vector number - * @param[in] type indicates whether RTEMS or RAW intr - * - * @return returns old vector - */ -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Internal BSP methods that are used across file boundaries - */ -void Init_RTC(void); - -/* - * Prototype for methods in .S files that are referenced from C. - */ -void bfin_null_isr(void); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -/** @} */ - -#endif diff --git a/bsps/bfin/eZKit533/include/bsp/irq.h b/bsps/bfin/eZKit533/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/bfin/eZKit533/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/bfin/eZKit533/include/cplb.h b/bsps/bfin/eZKit533/include/cplb.h deleted file mode 100644 index 1a5906a8d1..0000000000 --- a/bsps/bfin/eZKit533/include/cplb.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file - * @ingroup ezkit533_cplb - * @brief CPLB configurations. - */ - -/* cplb.h - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef _CPLB_H -#define _CPLB_H - -/** - * @defgroup ezkit533_cplb CPLB Configuration - * @ingroup RTEMSBSPsBfinEZKit533 - * @brief CPLB Configuration - * @{ - */ - -/* CPLB configurations */ -#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT -#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL -#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY - -#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT -#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR - -#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID -#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID - -#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID -#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL - -#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT -#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB - -/** @} */ - -#endif /* _CPLB_H */ diff --git a/bsps/bfin/eZKit533/include/tm27.h b/bsps/bfin/eZKit533/include/tm27.h deleted file mode 100644 index 3871908e62..0000000000 --- a/bsps/bfin/eZKit533/include/tm27.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * @ingroup ezkit533_tm27 - * @brief Interrupt mechanisms for the tm27 test. - */ - -/* - * tm27.h - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/** - * @defgroup ezkit533_tm27 TM27 Test Support - * @ingroup RTEMSBSPsBfinEZKit533 - * @brief Interrupt Mechanisms for TM27 - * @{ - */ - -/* - * Define the interrupt mechanism for Time Test 27 - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define TM27_USE_VECTOR_HANDLER - -#define Install_tm27_vector(handler) \ -{ \ - set_vector( handler, 0x06, 1 ); \ -} - -#define Cause_tm27_intr() __asm__ volatile("raise 0x06;" : :); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -/** @} */ - -#endif diff --git a/bsps/bfin/eZKit533/start/bspstart.c b/bsps/bfin/eZKit533/start/bspstart.c deleted file mode 100644 index 3579dd7766..0000000000 --- a/bsps/bfin/eZKit533/start/bspstart.c +++ /dev/null @@ -1,156 +0,0 @@ -/* bspstart.c for eZKit533 - * - * This routine does the bulk of the system initialisation. - */ - -/* - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include -#include - -const unsigned int dcplbs_table[16][2] = { - { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, - { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */ - { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */ - { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, - { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 3 */ - { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 2 (Secnd) */ - { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 1 (Prim B) */ - { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 (Prim A) */ - - { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) }, - { 0xffffffff, 0xffffffff } /* end of section - termination */ - -}; - - -const unsigned int _icplbs_table[16][2] = { - { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, /* L1 Code */ - { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */ - { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, - { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 3 */ - { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 2 (Secnd) */ - { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 1 (Prim B) */ - { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 0 (Prim A) */ - - { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) }, - { 0xffffffff, 0xffffffff } /* end of section - termination */ - -}; - -/* - * Init_PLL - * - * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL. - * See "../eZKit533/include/bsp.h" for more information. - */ -static void Init_PLL (void) -{ - unsigned int n; - - /* Configure PLL registers */ - *((uint16_t*)PLL_LOCKCNT) = 0x1000; - *((uint16_t*)PLL_DIV) = PLL_CSEL|PLL_SSEL; - *((uint16_t*)PLL_CTL) = PLL_MSEL|PLL_DF; - - /* Commands to set PLL values */ - __asm__ ("cli r0;"); - __asm__ ("idle;"); - __asm__ ("sti r0;"); - - /* Delay for PLL stabilization */ - for (n=0; n<200; n++) {} -} - -/* - * Init_EBIU - * - * Configure extern memory - */ -static void Init_EBIU (void) -{ - /* Configure FLASH */ - *((uint32_t*)EBIU_AMBCTL0) = 0x7bb07bb0L; - *((uint32_t*)EBIU_AMBCTL1) = 0x7bb07bb0L; - *((uint16_t*)EBIU_AMGCTL) = 0x000f; - - /* Configure SDRAM - *((uint32_t*)EBIU_SDGCTL) = 0x0091998d; - *((uint16_t*)EBIU_SDBCTL) = 0x0013; - *((uint16_t*)EBIU_SDRRC) = 0x0817; - */ -} - -/* - * Init_Flags - * - * Enable LEDs port - */ -static void Init_Flags(void) -{ - *((uint16_t*)FIO_INEN) = 0x0100; - *((uint16_t*)FIO_DIR) = 0x0000; - *((uint16_t*)FIO_EDGE) = 0x0100; - *((uint16_t*)FIO_MASKA_D) = 0x0100; - - *((uint8_t*)FlashA_PortB_Dir) = 0x3f; - *((uint8_t*)FlashA_PortB_Data) = 0x00; -} - -RTEMS_SYSINIT_ITEM( - bfin_interrupt_init, - RTEMS_SYSINIT_BSP_PRE_DRIVERS, - RTEMS_SYSINIT_ORDER_MIDDLE -); - -void bsp_start( void ) -{ - /* BSP Hardware Initialization*/ - Init_RTC(); /* Blackfin Real Time Clock initialization */ - Init_PLL(); /* PLL initialization */ - Init_EBIU(); /* EBIU initialization */ - Init_Flags(); /* GPIO initialization */ - - int i=0; - for (i=5;i<16;i++) { - set_vector((rtems_isr_entry)bfin_null_isr, i, 1); - } -} - -/* - * Helper Function to use the EzKits LEDS. - * Can be used by the Application. - */ -void setLED (uint8_t value) -{ - *((uint8_t*)FlashA_PortB_Data) = value; -} - -/* - * Helper Function to use the EzKits LEDS - */ -uint8_t getLED (void) -{ - return *((uint8_t*)FlashA_PortB_Data); -} diff --git a/bsps/bfin/eZKit533/start/linkcmds b/bsps/bfin/eZKit533/start/linkcmds deleted file mode 100644 index c7c02a98da..0000000000 --- a/bsps/bfin/eZKit533/start/linkcmds +++ /dev/null @@ -1,180 +0,0 @@ -OUTPUT_FORMAT("elf32-bfin", "elf32-bfin", - "elf32-bfin") - -OUTPUT_ARCH(bfin) -ENTRY(__start) -STARTUP(start.o) - -/* - * Declare some sizes. - */ -_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0; -_RamSize = DEFINED(_RamSize) ? _RamSize : 0x01000000; -_RamEnd = _RamBase + _RamSize; -_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; - -MEMORY -{ - sdram(rwx) : ORIGIN = 0x00001000, LENGTH = 0x01000000 - l1code(rwx) : ORIGIN = 0xffa08000, LENGTH = 0x00008000 - l1data(rwx) : ORIGIN = 0xff804000, LENGTH = 0x00004000 -} - -SECTIONS -{ - - .l1code : - { - /*jump.o (.text)*/ - } > l1code - - .init : - { - KEEP (*(.init)) - } > sdram /*=0*/ - - .text : - { - CREATE_OBJECT_SYMBOLS - *(.text) - *(.rodata*) - *(.gnu.linkonce.r*) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - ___start_set_sysctl_set = .; - *(set_sysctl_*); - ___stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - _etext = .; - - ___CTOR_LIST__ = .; - LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - ___CTOR_END__ = .; - ___DTOR_LIST__ = .; - LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - ___DTOR_END__ = .; - } > sdram - - .tdata : { - __TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - __TLS_Data_end = .; - } > sdram - - .tbss : { - __TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - __TLS_BSS_end = .; - } > sdram - - __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; - __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; - __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; - __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; - __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; - __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .fini : - { - KEEP (*(.fini)) - } > sdram /*=0*/ - - .data : - { - *(.data) - KEEP (*(SORT(.rtemsrwset.*))) - *(.jcr) - *(.gnu.linkonce.d*) - CONSTRUCTORS - _edata = .; - } > sdram - - .eh_frame : { *(.eh_frame) } > sdram - .data1 : { *(.data1) } > sdram - .eh_frame : { *(.eh_frame) } > sdram - .gcc_except_table : { *(.gcc_except_table*) } > sdram - - .rodata : - { - *(.rodata) - *(.rodata.*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - } > sdram - - - .bss : - { - _bss_start = .; - _clear_start = .; - *(.bss) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (64); - _clear_end = .; - _end = .; - __end = .; - } > sdram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } > sdram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - _WorkAreaBase = .; - } > sdram - -/* Debugging stuff follows */ - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* These must appear regardless of . */ - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } -} - -__HeapSize = _HeapSize; -__edata = _edata; -__etext = _etext; diff --git a/bsps/bfin/include/bf52x.h b/bsps/bfin/include/bf52x.h deleted file mode 100644 index 11d0ef15a3..0000000000 --- a/bsps/bfin/include/bf52x.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - *@file - * - *@brief - * - This file provides the register address for the 52X model. The file is - * based on the 533 implementation with some addition to support 52X range of - * processors. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#ifndef _BF52X_H_ -#define _BF52X_H_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define UART1_BASE_ADDRESS 0xffc02000 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 3 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER_ENABLE 0xffc00640 -#define TIMER_DISABLE 0xffc00644 -#define TIMER_STATUS 0xffc00648 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 8 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define DMA8_BASE_ADDRESS 0xffc00e00 -#define DMA9_BASE_ADDRESS 0xffc00e40 -#define DMA10_BASE_ADDRESS 0xffc00e80 -#define DMA11_BASE_ADDRESS 0xffc00ec0 -#define MDMA_BASE_ADDRESS 0xffc00e00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00e00 -#define MDMA0S_BASE_ADDRESS 0xffc00e40 -#define MDMA1D_BASE_ADDRESS 0xffc00e80 -#define MDMA1S_BASE_ADDRESS 0xffc00ec0 -#define PPI_BASE_ADDRESS 0xffc01000 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 8 - -#endif /* _BF52X_H_ */ - diff --git a/bsps/bfin/include/bsp/interrupt.h b/bsps/bfin/include/bsp/interrupt.h deleted file mode 100644 index 2822899918..0000000000 --- a/bsps/bfin/include/bsp/interrupt.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - *@file - * - *@brief - * - This file implements interrupt dispatcher. The init code is taken from - * the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR - * registers some portion is written twice. - * - * Target: TLL6527v1-0 - * Compiler: - * - * COPYRIGHT (c) 2010 by ECE Northeastern University. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license - * - * @author Rohan Kangralkar, ECE, Northeastern University - * (kangralkar.r@husky.neu.edu) - * - * LastChange: - */ - -#ifndef _BFIN_INTERRUPT_H_ -#define _BFIN_INTERRUPT_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** The type of interrupts handled by the SIC - */ -typedef enum { - IRQ_PLL_WAKEUP_INTERRUPT, /* 0 */ - IRQ_DMA_ERROR_0, /* 1 */ - IRQ_DMAR0_BLOCK_INTERRUPT, /* 2 */ - IRQ_DMAR1_BLOCK_INTERRUPT, /* 3 */ - IRQ_DMAR0_OVERFLOW_ERROR, /* 4 */ - IRQ_DMAR1_OVERFLOW_ERROR, /* 5 */ - IRQ_PPI_STATUS, /* 6 */ - IRQ_MAC_STATUS, /* 7 */ - IRQ_SPORT0_STATUS, /* 8 */ - IRQ_SPORT1_STATUS, /* 9 */ - IRQ_RESERVED_10, /* 10 */ - IRQ_RESERVED_11, /* 11 */ - IRQ_UART0_STATUS, /* 12 */ - IRQ_UART1_STATUS, /* 13 */ - IRQ_REAL_TIME_CLOCK, /* 14 */ - IRQ_DMA0_PPI_NFC, /* 15 */ - IRQ_DMA3_SPORT0_RX, /* 16 */ - IRQ_DMA4_SPORT0_TX, /* 17 */ - IRQ_DMA5_SPORT1_RX, /* 18 */ - IRQ_DMA6_SPORT1_TX, /* 19 */ - IRQ_TWI_INTERRUPT, /* 20 */ - IRQ_DMA7_SPI, /* 21 */ - IRQ_DMA8_UART0_RX, /* 22 */ - IRQ_DMA9_UART0_TX, /* 23 */ - IRQ_DMA10_UART1_RX, /* 24 */ - IRQ_DMA11_UART1_TX, /* 25 */ - IRQ_OTP, /* 26 */ - IRQ_GP_COUNTER, /* 27 */ - IRQ_DMA1_MAC_RX_HOSTDP, /* 28 */ - IRQ_PORT_H_INTERRUPT_A, /* 29 */ - IRQ_DMA2_MAC_TX_NFC, /* 30 */ - IRQ_PORT_H_INTERRUPT_B, /* 31 */ - SIC_ISR0_MAX, /* 32 ***/ - IRQ_TIMER0 = SIC_ISR0_MAX, /* 32 */ - IRQ_TIMER1, /* 33 */ - IRQ_TIMER2, /* 34 */ - IRQ_TIMER3, /* 35 */ - IRQ_TIMER4, /* 36 */ - IRQ_TIMER5, /* 37 */ - IRQ_TIMER6, /* 38 */ - IRQ_TIMER7, /* 39 */ - IRQ_PORT_G_INTERRUPT_A, /* 40 */ - IRQ_PORT_G_INTERRUPT_B, /* 41 */ - IRQ_MDMA0_STREAM_0_INTERRUPT, /* 42 */ - IRQ_MDMA1_STREAM_0_INTERRUPT, /* 43 */ - IRQ_SOFTWARE_WATCHDOG_INTERRUPT, /* 44 */ - IRQ_PORT_F_INTERRUPT_A, /* 45 */ - IRQ_PORT_F_INTERRUPT_B, /* 46 */ - IRQ_SPI_STATUS, /* 47 */ - IRQ_NFC_STATUS, /* 48 */ - IRQ_HOSTDP_STATUS, /* 49 */ - IRQ_HOREAD_DONE_INTERRUPT, /* 50 */ - IRQ_RESERVED_19, /* 51 */ - IRQ_USB_INT0_INTERRUPT, /* 52 */ - IRQ_USB_INT1_INTERRUPT, /* 53 */ - IRQ_USB_INT2_INTERRUPT, /* 54 */ - IRQ_USB_DMAINT, /* 55 */ - IRQ_MAX, /* 56 */ -} e_isr_t; - - - - -/* source is the source to the SIC (the bit number in SIC_ISR). isr is - the function that will be called when the interrupt is active. */ -typedef struct bfin_isr_s { -#if INTERRUPT_USE_TABLE - e_isr_t source; - void (*pFunc)(void *arg); - void *pArg; - int priority; /** not used */ -#else - int source; - void (*isr)(void *arg); - void *_arg; - /* the following are for internal use only */ - uint32_t mask0; - uint32_t mask1; - uint32_t vector; - struct bfin_isr_s *next; -#endif -} bfin_isr_t; - -/** - * This routine registers a new ISR. It will write a new entry to the IVT table - * @param isr contains a callback function and source - * @return rtems status code - */ -rtems_status_code bfin_interrupt_register(bfin_isr_t *isr); - -/** - * This function unregisters a registered interrupt handler. - * @param isr - */ -rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr); - -/** - * blackfin interrupt initialization routine. It initializes the bfin ISR - * dispatcher. It will also create SIC CEC map which will be used for - * identifying the ISR. - */ -void bfin_interrupt_init(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* _BFIN_INTERRUPT_H_ */ - diff --git a/bsps/bfin/include/libcpu/bf533.h b/bsps/bfin/include/libcpu/bf533.h deleted file mode 100644 index 78cfaa0125..0000000000 --- a/bsps/bfin/include/libcpu/bf533.h +++ /dev/null @@ -1,135 +0,0 @@ -/* Blackfin BF533 Definitions - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _bf533_h_ -#define _bf533_h_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 3 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER_ENABLE 0xffc00640 -#define TIMER_DISABLE 0xffc00644 -#define TIMER_STATUS 0xffc00648 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 8 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define MDMA_BASE_ADDRESS 0xffc00e00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00e00 -#define MDMA0S_BASE_ADDRESS 0xffc00e40 -#define MDMA1D_BASE_ADDRESS 0xffc00e80 -#define MDMA1S_BASE_ADDRESS 0xffc00ec0 -#define PPI_BASE_ADDRESS 0xffc01000 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 3 - -#define SIC_PLL_WAKEUP_VECTOR 0 -#define SIC_DMA_ERROR_VECTOR 1 -#define SIC_PPI_ERROR_VECTOR 2 -#define SIC_SPORT0_ERROR_VECTOR 3 -#define SIC_SPORT1_ERROR_VECTOR 4 -#define SIC_SPI_ERROR_VECTOR 5 -#define SIC_UART0_ERROR_VECTOR 6 -#define SIC_RTC_VECTOR 7 -#define SIC_DMA0_PPI_VECTOR 8 -#define SIC_DMA1_SPORT0_RX_VECTOR 9 -#define SIC_DMA2_SPORT0_TX_VECTOR 10 -#define SIC_DMA3_SPORT1_RX_VECTOR 11 -#define SIC_DMA4_SPORT1_TX_VECTOR 12 -#define SIC_DMA5_SPI_VECTOR 13 -#define SIC_DMA6_UART0_RX_VECTOR 14 -#define SIC_DMA7_UART0_TX_VECTOR 15 -#define SIC_TIMER0_VECTOR 16 -#define SIC_TIMER1_VECTOR 17 -#define SIC_TIMER2_VECTOR 18 -#define SIC_MDMA0_VECTOR 21 -#define SIC_MDMA1_VECTOR 22 -#define SIC_WATCHDOG_VECTOR 23 - -#endif /* _bf533_h_ */ diff --git a/bsps/bfin/include/libcpu/bf537.h b/bsps/bfin/include/libcpu/bf537.h deleted file mode 100644 index 8ed235205f..0000000000 --- a/bsps/bfin/include/libcpu/bf537.h +++ /dev/null @@ -1,225 +0,0 @@ -/* Blackfin BF537 Definitions - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _bf537_h_ -#define _bf537_h_ - -/* register (or register block) addresses */ - -#define SIC_BASE_ADDRESS 0xffc00100 -#define WDOG_BASE_ADDRESS 0xffc00200 -#define RTC_BASE_ADDRESS 0xffc00300 -#define UART0_BASE_ADDRESS 0xffc00400 -#define SPI_BASE_ADDRESS 0xffc00500 -#define TIMER_BASE_ADDRESS 0xffc00600 -#define TIMER_CHANNELS 8 -#define TIMER_PITCH 0x10 -#define TIMER0_BASE_ADDRESS 0xffc00600 -#define TIMER1_BASE_ADDRESS 0xffc00610 -#define TIMER2_BASE_ADDRESS 0xffc00620 -#define TIMER3_BASE_ADDRESS 0xffc00630 -#define TIMER4_BASE_ADDRESS 0xffc00640 -#define TIMER5_BASE_ADDRESS 0xffc00650 -#define TIMER6_BASE_ADDRESS 0xffc00660 -#define TIMER7_BASE_ADDRESS 0xffc00670 -#define TIMER_ENABLE 0xffc00680 -#define TIMER_DISABLE 0xffc00684 -#define TIMER_STATUS 0xffc00688 -#define PORTFIO_BASE_ADDRESS 0xffc00700 -#define SPORT0_BASE_ADDRESS 0xffc00800 -#define SPORT1_BASE_ADDRESS 0xffc00900 -#define EBIU_BASE_ADDRESS 0xffc00a00 -#define DMA_TC_PER 0xffc00b0c -#define DMA_TC_CNT 0xffc00b10 -#define DMA_BASE_ADDRESS 0xffc00c00 -#define DMA_CHANNELS 12 -#define DMA_PITCH 0x40 -#define DMA0_BASE_ADDRESS 0xffc00c00 -#define DMA1_BASE_ADDRESS 0xffc00c40 -#define DMA2_BASE_ADDRESS 0xffc00c80 -#define DMA3_BASE_ADDRESS 0xffc00cc0 -#define DMA4_BASE_ADDRESS 0xffc00d00 -#define DMA5_BASE_ADDRESS 0xffc00d40 -#define DMA6_BASE_ADDRESS 0xffc00d80 -#define DMA7_BASE_ADDRESS 0xffc00dc0 -#define DMA8_BASE_ADDRESS 0xffc00e00 -#define DMA9_BASE_ADDRESS 0xffc00e40 -#define DMA10_BASE_ADDRESS 0xffc00e80 -#define DMA11_BASE_ADDRESS 0xffc00ec0 -#define MDMA_BASE_ADDRESS 0xffc00f00 -#define MDMA_CHANNELS 2 -#define MDMA_D_S 0x40 -#define MDMA_PITCH 0x80 -#define MDMA0D_BASE_ADDRESS 0xffc00f00 -#define MDMA0S_BASE_ADDRESS 0xffc00f40 -#define MDMA1D_BASE_ADDRESS 0xffc00f80 -#define MDMA1S_BASE_ADDRESS 0xffc00fc0 -#define PPI_BASE_ADDRESS 0xffc01000 -#define TWI_BASE_ADDRESS 0xffc01400 -#define PORTGIO_BASE_ADDRESS 0xffc01500 -#define PORTHIO_BASE_ADDRESS 0xffc01700 -#define UART1_BASE_ADDRESS 0xffc02000 -#define CAN_BASE_ADDRESS 0xffc02a00 -#define CAN_AM_BASE_ADDRESS 0xffc02b00 -#define CAN_MB_BASE_ADDRESS 0xffc02c00 -#define EMAC_BASE_ADDRESS 0xffc03000 -#define PORTF_FER 0xffc03200 -#define PORTG_FER 0xffc03204 -#define PORTH_FER 0xffc03208 -#define PORT_MUX 0xffc0320c -#define HMDMA0_BASE_ADDRESS 0xffc03300 -#define HMDMA1_BASE_ADDRESS 0xffc03340 - - -/* register fields */ - -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800 -#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700 -#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0 -#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4 -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f -#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0 - -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800 -#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700 -#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0 -#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4 -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f -#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0 - -#define TIMER_ENABLE_TIMEN7 0x0080 -#define TIMER_ENABLE_TIMEN6 0x0040 -#define TIMER_ENABLE_TIMEN5 0x0020 -#define TIMER_ENABLE_TIMEN4 0x0010 -#define TIMER_ENABLE_TIMEN3 0x0008 -#define TIMER_ENABLE_TIMEN2 0x0004 -#define TIMER_ENABLE_TIMEN1 0x0002 -#define TIMER_ENABLE_TIMEN0 0x0001 - -#define TIMER_DISABLE_TIMDIS7 0x0080 -#define TIMER_DISABLE_TIMDIS6 0x0040 -#define TIMER_DISABLE_TIMDIS5 0x0020 -#define TIMER_DISABLE_TIMDIS4 0x0010 -#define TIMER_DISABLE_TIMDIS3 0x0008 -#define TIMER_DISABLE_TIMDIS2 0x0004 -#define TIMER_DISABLE_TIMDIS1 0x0002 -#define TIMER_DISABLE_TIMDIS0 0x0001 - -#define TIMER_STATUS_TRUN7 0x80000000 -#define TIMER_STATUS_TRUN6 0x40000000 -#define TIMER_STATUS_TRUN5 0x20000000 -#define TIMER_STATUS_TRUN4 0x10000000 -#define TIMER_STATUS_TOVF_ERR7 0x00800000 -#define TIMER_STATUS_TOVF_ERR6 0x00400000 -#define TIMER_STATUS_TOVF_ERR5 0x00200000 -#define TIMER_STATUS_TOVF_ERR4 0x00100000 -#define TIMER_STATUS_TIMIL7 0x00080000 -#define TIMER_STATUS_TIMIL6 0x00040000 -#define TIMER_STATUS_TIMIL5 0x00020000 -#define TIMER_STATUS_TIMIL4 0x00010000 -#define TIMER_STATUS_TRUN3 0x00008000 -#define TIMER_STATUS_TRUN2 0x00004000 -#define TIMER_STATUS_TRUN1 0x00002000 -#define TIMER_STATUS_TRUN0 0x00001000 -#define TIMER_STATUS_TOVF_ERR3 0x00000080 -#define TIMER_STATUS_TOVF_ERR2 0x00000040 -#define TIMER_STATUS_TOVF_ERR1 0x00000020 -#define TIMER_STATUS_TOVF_ERR0 0x00000010 -#define TIMER_STATUS_TIMIL3 0x00000008 -#define TIMER_STATUS_TIMIL2 0x00000004 -#define TIMER_STATUS_TIMIL1 0x00000002 -#define TIMER_STATUS_TIMIL0 0x00000001 - -#define PORT_MUX_PGTE 0x0800 -#define PORT_MUX_PGRE 0x0400 -#define PORT_MUX_PGSE 0x0200 -#define PORT_MUX_PFFE 0x0100 -#define PORT_MUX_PFS4E 0x0080 -#define PORT_MUX_PFS5E 0x0040 -#define PORT_MUX_PFS6E 0x0020 -#define PORT_MUX_PFTE 0x0010 -#define PORT_MUX_PFDE 0x0008 -#define PORT_MUX_PJCE_MASK 0x0006 -#define PORT_MUX_PJCE_DR0SEC_DTOSEC 0x0000 -#define PORT_MUX_PJCE_CANRX_CANTX 0x0002 -#define PORT_MUX_PJCE_SPISSEL7 0x0004 -#define PORT_MUX_PJSE 0x0001 - - -/* Core Event Controller vectors */ - -#define CEC_EMULATION_VECTOR 0 -#define CEC_RESET_VECTOR 1 -#define CEC_NMI_VECTOR 2 -#define CEC_EXCEPTIONS_VECTOR 3 -#define CEC_HARDWARE_ERROR_VECTOR 5 -#define CEC_CORE_TIMER_VECTOR 6 -#define CEC_INTERRUPT_BASE_VECTOR 7 -#define CEC_INTERRUPT_COUNT 9 - - -/* System Interrupt Controller vectors */ - -#define SIC_IAR_COUNT 4 - -#define SIC_PLL_WAKEUP_VECTOR 0 -#define SIC_DMA_ERROR_VECTOR 1 -#define SIC_DMAR0_BLOCK_DONE_VECTOR 1 -#define SIC_DMAR1_BLOCK_DONE_VECTOR 1 -#define SIC_DMAR0_OVERFLOW_VECTOR 1 -#define SIC_DMAR1_OVERFLOW_VECTOR 1 -#define SIC_CAN_ERROR_VECTOR 2 -#define SIC_MAC_ERROR_VECTOR 2 -#define SIC_SPORT0_ERROR_VECTOR 2 -#define SIC_SPORT1_ERROR_VECTOR 2 -#define SIC_PPI_ERROR_VECTOR 2 -#define SIC_SPI_ERROR_VECTOR 2 -#define SIC_UART0_ERROR_VECTOR 2 -#define SIC_UART1_ERROR_VECTOR 2 -#define SIC_RTC_VECTOR 3 -#define SIC_DMA0_PPI_VECTOR 4 -#define SIC_DMA3_SPORT0_RX_VECTOR 5 -#define SIC_DMA4_SPORT0_TX_VECTOR 6 -#define SIC_DMA5_SPORT1_RX_VECTOR 7 -#define SIC_DMA5_SPORT1_TX_VECTOR 8 -#define SIC_TWI_VECTOR 9 -#define SIC_DMA7_SPI_VECTOR 10 -#define SIC_DMA8_UART0_RX_VECTOR 11 -#define SIC_DMA9_UART0_TX_VECTOR 12 -#define SIC_DMA10_UART1_RX_VECTOR 13 -#define SIC_DMA11_UART1_TX_VECTOR 14 -#define SIC_CAN_RX_VECTOR 15 -#define SIC_CAN_TX_VECTOR 16 -#define SIC_DMA1_MAC_RX_VECTOR 17 -#define SIC_PORTH_IRQ_A_VECTOR 17 -#define SIC_DMA2_MAC_TX_VECTOR 18 -#define SIC_PORTH_IRQ_B_VECTOR 18 -#define SIC_TIMER0_VECTOR 19 -#define SIC_TIMER1_VECTOR 20 -#define SIC_TIMER2_VECTOR 21 -#define SIC_TIMER3_VECTOR 22 -#define SIC_TIMER4_VECTOR 23 -#define SIC_TIMER5_VECTOR 24 -#define SIC_TIMER6_VECTOR 25 -#define SIC_TIMER7_VECTOR 26 -#define SIC_PORTF_IRQ_A_VECTOR 27 -#define SIC_PORTG_IRQ_A_VECTOR 27 -#define SIC_PORTG_IRQ_B_VECTOR 28 -#define SIC_MDMA0_VECTOR 29 -#define SIC_MDMA1_VECTOR 30 -#define SIC_WATCHDOG_VECTOR 31 -#define SIC_PORTF_IRQ_B_VECTOR 31 - - -#endif /* _bf537_h_ */ diff --git a/bsps/bfin/include/libcpu/cecRegs.h b/bsps/bfin/include/libcpu/cecRegs.h deleted file mode 100644 index 89564c6f70..0000000000 --- a/bsps/bfin/include/libcpu/cecRegs.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Blackfin Core Event Controller Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _cecRegs_h_ -#define _cecRegs_h_ - -/* register addresses */ -#define CEC_EVT_BASE 0xffe02000 -#define CEC_EVT_COUNT 16 -#define CEC_EVT_PITCH 0x04 -#define CEC_EVT0 0xffe02000 -#define CEC_EVT1 0xffe02004 -#define CEC_EVT2 0xffe02008 -#define CEC_EVT3 0xffe0200c -#define CEC_EVT4 0xffe02010 -#define CEC_EVT5 0xffe02014 -#define CEC_EVT6 0xffe02018 -#define CEC_EVT7 0xffe0201c -#define CEC_EVT8 0xffe02020 -#define CEC_EVT9 0xffe02024 -#define CEC_EVT10 0xffe02028 -#define CEC_EVT11 0xffe0202c -#define CEC_EVT12 0xffe02030 -#define CEC_EVT13 0xffe02034 -#define CEC_EVT14 0xffe02038 -#define CEC_EVT15 0xffe0203c -#define CEC_IMASK 0xffe02104 -#define CEC_IPEND 0xffe02108 -#define CEC_ILAT 0xffe0210c -#define CEC_IPRIO 0xffe02110 - - -/* register fields */ - -#define CEC_IPRIO_IPRIO_MARK_MASK 0x0000000f -#define CEC_IPRIO_IPRIO_MARK_SHIFT 0 - - -#endif /* _cecRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/coreTimerRegs.h b/bsps/bfin/include/libcpu/coreTimerRegs.h deleted file mode 100644 index c5b257783c..0000000000 --- a/bsps/bfin/include/libcpu/coreTimerRegs.h +++ /dev/null @@ -1,29 +0,0 @@ -/* Blackfin Core Timer Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _coreTimerRegs_h_ -#define _coreTimerRegs_h_ - -/* register addresses */ - -#define TCNTL 0xffe03000 -#define TPERIOD 0xffe03004 -#define TSCALE 0xffe03008 -#define TCOUNT 0xffe0300c - - -/* register fields */ - -#define TCNTL_TINT 0x00000008 -#define TCNTL_TAUTORLD 0x00000004 -#define TCNTL_TMREN 0x00000002 -#define TCNTL_TMPWR 0x00000001 - -#endif /* _coreTimerRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/dmaRegs.h b/bsps/bfin/include/libcpu/dmaRegs.h deleted file mode 100644 index 7c895b7cab..0000000000 --- a/bsps/bfin/include/libcpu/dmaRegs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* Blackfin DMA Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _dmaRegs_h_ -#define _dmaRegs_h_ - - -/* register addresses */ - -#define DMA_NEXT_DESC_PTR_OFFSET 0x0000 -#define DMA_START_ADDR_OFFSET 0x0004 -#define DMA_CONFIG_OFFSET 0x0008 -#define DMA_X_COUNT_OFFSET 0x0010 -#define DMA_X_MODIFY_OFFSET 0x0014 -#define DMA_Y_COUNT_OFFSET 0x0018 -#define DMA_Y_MODIFY_OFFSET 0x001c -#define DMA_CURR_DESC_PTR_OFFSET 0x0020 -#define DMA_CURR_ADDR_OFFSET 0x0024 -#define DMA_IRQ_STATUS_OFFSET 0x0028 -#define DMA_PERIPHERAL_MAP_OFFSET 0x002c -#define DMA_CURR_X_COUNT_OFFSET 0x0030 -#define DMA_CURR_Y_COUNT_OFFSET 0x0038 - -#define HMDMA_CONTROL_OFFSET 0x0000 -#define HMDMA_ECINIT_OFFSET 0x0004 -#define HMDMA_BCINIT_OFFSET 0x0008 -#define HMDMA_ECURGENT_OFFSET 0x000c -#define HMDMA_ECOVERFLOW_OFFSET 0x0010 -#define HMDMA_ECOUNT_OFFSET 0x0014 -#define HMDMA_BCOUNT_OFFSET 0x0018 - - -/* register fields */ - -#define DMA_CONFIG_FLOW_MASK 0x7000 -#define DMA_CONFIG_FLOW_STOP 0x0000 -#define DMA_CONFIG_FLOW_AUTOBUFFER 0x1000 -#define DMA_CONFIG_FLOW_DESC_ARRAY 0x4000 -#define DMA_CONFIG_FLOW_DESC_SMALL 0x6000 -#define DMA_CONFIG_FLOW_DESC_LARGE 0x7000 -#define DMA_CONFIG_NDSIZE_MASK 0x0f00 -#define DMA_CONFIG_NDSIZE_SHIFT 8 -#define DMA_CONFIG_DI_EN 0x0080 -#define DMA_CONFIG_DI_SEL 0x0040 -#define DMA_CONFIG_SYNC 0x0020 -#define DMA_CONFIG_DMA2D 0x0010 -#define DMA_CONFIG_WDSIZE_MASK 0x000c -#define DMA_CONFIG_WDSIZE_8 0x0000 -#define DMA_CONFIG_WDSIZE_16 0x0004 -#define DMA_CONFIG_WDSIZE_32 0x0008 -#define DMA_CONFIG_WNR 0x0002 -#define DMA_CONFIG_DMAEN 0x0001 - -#define DMA_IRQ_STATUS_DMA_RUN 0x0008 -#define DMA_IRQ_STATUS_DFETCH 0x0004 -#define DMA_IRQ_STATUS_DMA_ERR 0x0002 -#define DMA_IRQ_STATUS_DMA_DONE 0x0001 - -#define DMA_PERIPHERAL_MAP_PMAP_MASK 0xf000 -#define DMA_PERIPHERAL_MAP_PMAP_PPI 0x0000 -#define DMA_PERIPHERAL_MAP_PMAP_ETHRX 0x1000 -#define DMA_PERIPHERAL_MAP_PMAP_ETHTX 0x2000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT0RX 0x3000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT0TX 0x4000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT1RX 0x5000 -#define DMA_PERIPHERAL_MAP_PMAP_SPORT1TX 0x6000 -#define DMA_PERIPHERAL_MAP_PMAP_SPI 0x7000 -#define DMA_PERIPHERAL_MAP_PMAP_UART0RX 0x8000 -#define DMA_PERIPHERAL_MAP_PMAP_UART0TX 0x9000 -#define DMA_PERIPHERAL_MAP_PMAP_UART1RX 0xa000 -#define DMA_PERIPHERAL_MAP_PMAP_UART1TX 0xb000 -#define DMA_PERIPHERAL_MAP_CTYPE 0x0040 - -#define HMDMA_CONTROL_BDI 0x8000 -#define HMDMA_CONTROL_OI 0x4000 -#define HMDMA_CONTROL_PS 0x2000 -#define HMDMA_CONTROL_RBC 0x1000 -#define HMDMA_CONTROL_DRQ_MASK 0x0300 -#define HMDMA_CONTROL_DRQ_NONE 0x0000 -#define HMDMA_CONTROL_DRQ_SINGLE 0x0100 -#define HMDMA_CONTROL_DRQ_MULTIPLE 0x0200 -#define HMDMA_CONTROL_DRQ_URGENT_MULTIPLE 0x0300 -#define HMDMA_CONTROL_MBDI 0x0040 -#define HMDMA_CONTROL_BDIE 0x0020 -#define HMDMA_CONTROL_OIE 0x0010 -#define HMDMA_CONTROL_UTE 0x0008 -#define HMDMA_CONTROL_REP 0x0002 -#define HMDMA_CONTROL_HMDMAEN 0x0001 - -#endif /* _dmaRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ebiuRegs.h b/bsps/bfin/include/libcpu/ebiuRegs.h deleted file mode 100644 index 1a07ff6985..0000000000 --- a/bsps/bfin/include/libcpu/ebiuRegs.h +++ /dev/null @@ -1,133 +0,0 @@ -/* Blackfin External Peripheral Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ebiuRegs_h_ -#define _ebiuRegs_h_ - -/* register addresses */ - -#define EBIU_AMGCTL (EBIU_BASE_ADDRESS + 0x0000) -#define EBIU_AMBCTL0 (EBIU_BASE_ADDRESS + 0x0004) -#define EBIU_AMBCTL1 (EBIU_BASE_ADDRESS + 0x0008) -#define EBIU_SDGCTL (EBIU_BASE_ADDRESS + 0x0010) -#define EBIU_SDBCTL (EBIU_BASE_ADDRESS + 0x0014) -#define EBIU_SDRRC (EBIU_BASE_ADDRESS + 0x0018) -#define EBIU_SDSTAT (EBIU_BASE_ADDRESS + 0x001c) - -/* register fields */ - -#define EBIU_AMGCTL_CDPRIO 0x0100 -#define EBIU_AMGCTL_AMBEN_MASK 0x000e -#define EBIU_AMGCTL_AMBEN_SHIFT 1 -#define EBIU_AMGCTL_AMCKEN 0x0001 - -#define EBIU_AMBCTL0_B1WAT_MASK 0xf0000000 -#define EBIU_AMBCTL0_B1WAT_SHIFT 28 -#define EBIU_AMBCTL0_B1RAT_MASK 0x0f000000 -#define EBIU_AMBCTL0_B1RAT_SHIFT 24 -#define EBIU_AMBCTL0_B1HT_MASK 0x00c00000 -#define EBIU_AMBCTL0_B1HT_SHIFT 22 -#define EBIU_AMBCTL0_B1ST_MASK 0x00300000 -#define EBIU_AMBCTL0_B1ST_SHIFT 20 -#define EBIU_AMBCTL0_B1TT_MASK 0x000c0000 -#define EBIU_AMBCTL0_B1TT_SHIFT 18 -#define EBIU_AMBCTL0_B1RDYPOL 0x00020000 -#define EBIU_AMBCTL0_B1RDYEN 0x00010000 -#define EBIU_AMBCTL0_B0WAT_MASK 0x0000f000 -#define EBIU_AMBCTL0_B0WAT_SHIFT 12 -#define EBIU_AMBCTL0_B0RAT_MASK 0x00000f00 -#define EBIU_AMBCTL0_B0RAT_SHIFT 8 -#define EBIU_AMBCTL0_B0HT_MASK 0x000000c0 -#define EBIU_AMBCTL0_B0HT_SHIFT 6 -#define EBIU_AMBCTL0_B0ST_MASK 0x00000030 -#define EBIU_AMBCTL0_B0ST_SHIFT 4 -#define EBIU_AMBCTL0_B0TT_MASK 0x0000000c -#define EBIU_AMBCTL0_B0TT_SHIFT 2 -#define EBIU_AMBCTL0_B0RDYPOL 0x00000002 -#define EBIU_AMBCTL0_B0RDYEN 0x00000001 - -#define EBIU_AMBCTL1_B3WAT_MASK 0xf0000000 -#define EBIU_AMBCTL1_B3WAT_SHIFT 28 -#define EBIU_AMBCTL1_B3RAT_MASK 0x0f000000 -#define EBIU_AMBCTL1_B3RAT_SHIFT 24 -#define EBIU_AMBCTL1_B3HT_MASK 0x00c00000 -#define EBIU_AMBCTL1_B3HT_SHIFT 22 -#define EBIU_AMBCTL1_B3ST_MASK 0x00300000 -#define EBIU_AMBCTL1_B3ST_SHIFT 20 -#define EBIU_AMBCTL1_B3TT_MASK 0x000c0000 -#define EBIU_AMBCTL1_B3TT_SHIFT 18 -#define EBIU_AMBCTL1_B3RDYPOL 0x00020000 -#define EBIU_AMBCTL1_B3RDYEN 0x00010000 -#define EBIU_AMBCTL1_B2WAT_MASK 0x0000f000 -#define EBIU_AMBCTL1_B2WAT_SHIFT 12 -#define EBIU_AMBCTL1_B2RAT_MASK 0x00000f00 -#define EBIU_AMBCTL1_B2RAT_SHIFT 8 -#define EBIU_AMBCTL1_B2HT_MASK 0x000000c0 -#define EBIU_AMBCTL1_B2HT_SHIFT 6 -#define EBIU_AMBCTL1_B2ST_MASK 0x00000030 -#define EBIU_AMBCTL1_B2ST_SHIFT 4 -#define EBIU_AMBCTL1_B2TT_MASK 0x0000000c -#define EBIU_AMBCTL1_B2TT_SHIFT 2 -#define EBIU_AMBCTL1_B2RDYPOL 0x00000002 -#define EBIU_AMBCTL1_B2RDYEN 0x00000001 - -#define EBIU_SDGCTL_CDDBG 0x40000000 -#define EBIU_SDGCTL_TCSR 0x20000000 -#define EBIU_SDGCTL_EMREN 0x10000000 -#define EBIU_SDGCTL_FBBRW 0x04000000 -#define EBIU_SDGCTL_EBUFE 0x02000000 -#define EBIU_SDGCTL_SRFS 0x01000000 -#define EBIU_SDGCTL_PSSE 0x00800000 -#define EBIU_SDGCTL_PSM 0x00400000 -#define EBIU_SDGCTL_PUPSD 0x00200000 -#define EBIU_SDGCTL_TWR_MASK 0x00180000 -#define EBIU_SDGCTL_TWR_SHIFT 19 -#define EBIU_SDGCTL_TRCD_MASK 0x00038000 -#define EBIU_SDGCTL_TRCD_SHIFT 15 -#define EBIU_SDGCTL_TRP_MASK 0x00003800 -#define EBIU_SDGCTL_TRP_SHIFT 11 -#define EBIU_SDGCTL_TRAS_MASK 0x000003c0 -#define EBIU_SDGCTL_TRAS_SHIFT 6 -#define EBIU_SDGCTL_PASR_MASK 0x00000030 -#define EBIU_SDGCTL_PASR_ALL 0x00000000 -#define EBIU_SDGCTL_PASR_0_1 0x00000010 -#define EBIU_SDGCTL_PASR_0 0x00000020 -#define EBIU_SDGCTL_CL_MASK 0x0000000c -#define EBIU_SDGCTL_CL_SHIFT 2 -#define EBIU_SDGCTL_SCTLE 0x00000001 - -#define EBIU_SDBCTL_EBCAW_MASK 0x0030 -#define EBIU_SDBCTL_SHIFT 4 -#define EBIU_SDBCTL_EBCAW_8 0x0000 -#define EBIU_SDBCTL_EBCAW_9 0x0010 -#define EBIU_SDBCTL_EBCAW_10 0x0020 -#define EBIU_SDBCTL_EBCAW_11 0x0030 -#define EBIU_SDBCTL_EBSZ_MASK 0x000e -#define EBIU_SDBCTL_EBSZ_SHIFT 1 -#define EBIU_SDBCTL_EBSZ_16M 0x0000 -#define EBIU_SDBCTL_EBSZ_32M 0x0002 -#define EBIU_SDBCTL_EBSZ_64M 0x0004 -#define EBIU_SDBCTL_EBSZ_128M 0x0006 -#define EBIU_SDBCTL_EBSZ_256M 0x0008 -#define EBIU_SDBCTL_EBSZ_512M 0x000a -#define EBIU_SDBCTL_EBE 0x0001 - -#define EBIU_SDRRC_RDIV_MASK 0x0fff -#define EBIU_SDRRC_RDIV_SHIFT 0 - -#define EBIU_SDSTAT_BGSTAT 0x0020 -#define EBIU_SDSTAT_SDEASE 0x0010 -#define EBIU_SDSTAT_SDRS 0x0008 -#define EBIU_SDSTAT_SDPUA 0x0004 -#define EBIU_SDSTAT_SDSRA 0x0002 -#define EBIU_SDSTAT_SDCI 0x0001 - - -#endif /* _ebiuRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ethernet.h b/bsps/bfin/include/libcpu/ethernet.h deleted file mode 100644 index 0a8fc0c4b0..0000000000 --- a/bsps/bfin/include/libcpu/ethernet.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * RTEMS network driver for Blackfin embedded ethernet controller - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ethernet_h_ -#define _ethernet_h_ - - -#define BFIN_ETHERNET_DEBUG_NONE 0x0000 -#define BFIN_ETHERNET_DEBUG_ALL 0xFFFF - -#define BFIN_ETHERNET_DEBUG (BFIN_ETHERNET_DEBUG_NONE) - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - uint32_t sclk; - void *ethBaseAddress; - void *rxdmaBaseAddress; - void *txdmaBaseAddress; - int rxDescCount; - int txDescCount; - enum {rmii, mii} phyType; - int phyAddr; -} bfin_ethernet_configuration_t; - - -void bfin_ethernet_rxdma_isr(int vector); -void bfin_ethernet_txdma_isr(int vector); -void bfin_ethernet_mac_isr(int vector); - -int bfin_ethernet_driver_attach(struct rtems_bsdnet_ifconfig *config, - int attaching, - bfin_ethernet_configuration_t *chip); - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ethernet_h_ */ - diff --git a/bsps/bfin/include/libcpu/ethernetRegs.h b/bsps/bfin/include/libcpu/ethernetRegs.h deleted file mode 100644 index 7bf85c576b..0000000000 --- a/bsps/bfin/include/libcpu/ethernetRegs.h +++ /dev/null @@ -1,419 +0,0 @@ -/* Blackfin Ethernet Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ethernetRegs_h_ -#define _ethernetRegs_h_ - -/* register addresses */ - -#define EMAC_OPMODE_OFFSET 0x0000 -#define EMAC_ADDRLO_OFFSET 0x0004 -#define EMAC_ADDRHI_OFFSET 0x0008 -#define EMAC_HASHLO_OFFSET 0x000c -#define EMAC_HASHHI_OFFSET 0x0010 -#define EMAC_STAADD_OFFSET 0x0014 -#define EMAC_STADAT_OFFSET 0x0018 -#define EMAC_FLC_OFFSET 0x001c -#define EMAC_VLAN1_OFFSET 0x0020 -#define EMAC_VLAN2_OFFSET 0x0024 -#define EMAC_WKUP_CTL_OFFSET 0x002c -#define EMAC_WKUP_FFMSK0_OFFSET 0x0030 -#define EMAC_WKUP_FFMSK1_OFFSET 0x0034 -#define EMAC_WKUP_FFMSK2_OFFSET 0x0038 -#define EMAC_WKUP_FFMSK3_OFFSET 0x003c -#define EMAC_WKUP_FFCMD_OFFSET 0x0040 -#define EMAC_WKUP_FFOFF_OFFSET 0x0044 -#define EMAC_WKUP_FFCRC01_OFFSET 0x0048 -#define EMAC_WKUP_FFCRC23_OFFSET 0x004c -#define EMAC_SYSCTL_OFFSET 0x0060 -#define EMAC_SYSTAT_OFFSET 0x0064 -#define EMAC_RX_STAT_OFFSET 0x0068 -#define EMAC_RX_STKY_OFFSET 0x006c -#define EMAC_RX_IRQE_OFFSET 0x0070 -#define EMAC_TX_STAT_OFFSET 0x0074 -#define EMAC_TX_STKY_OFFSET 0x0078 -#define EMAC_TX_IRQE_OFFSET 0x007c -#define EMAC_MMC_CTL_OFFSET 0x0080 -#define EMAC_MMC_RIRQS_OFFSET 0x0084 -#define EMAC_MMC_RIRQE_OFFSET 0x0088 -#define EMAC_MMC_TIRQS_OFFSET 0x008c -#define EMAC_MMC_TIRQE_OFFSET 0x0090 - -#define EMAC_RXC_OK_OFFSET 0x0100 -#define EMAC_RXC_FCS_OFFSET 0x0104 -#define EMAC_RXC_ALIGN_OFFSET 0x0108 -#define EMAC_RXC_OCTET_OFFSET 0x010c -#define EMAC_RXC_DMAOVF_OFFSET 0x0110 -#define EMAC_RXC_UNICST_OFFSET 0x0114 -#define EMAC_RXC_MULTI_OFFSET 0x0118 -#define EMAC_RXC_BROAD_OFFSET 0x011c -#define EMAC_RXC_LNERRI_OFFSET 0x0120 -#define EMAC_RXC_LNERRO_OFFSET 0x0124 -#define EMAC_RXC_LONG_OFFSET 0x0128 -#define EMAC_RXC_MACCTL_OFFSET 0x012c -#define EMAC_RXC_OPCODE_OFFSET 0x0130 -#define EMAC_RXC_PAUSE_OFFSET 0x0134 -#define EMAC_RXC_ALLFRM_OFFSET 0x0138 -#define EMAC_RXC_ALLOCT_OFFSET 0x013c -#define EMAC_RXC_TYPED_OFFSET 0x0140 -#define EMAC_RXC_SHORT_OFFSET 0x0144 -#define EMAC_RXC_EQ64_OFFSET 0x0148 -#define EMAC_RXC_LT128_OFFSET 0x014c -#define EMAC_RXC_LT256_OFFSET 0x0150 -#define EMAC_RXC_LT512_OFFSET 0x0154 -#define EMAC_RXC_LT1024_OFFSET 0x0158 -#define EMAC_RXC_GE1024_OFFSET 0x015c - -#define EMAC_TXC_OK_OFFSET 0x0180 -#define EMAC_TXC_1COL_OFFSET 0x0184 -#define EMAC_TXC_GT1COL_OFFSET 0x0188 -#define EMAC_TXC_OCTET_OFFSET 0x018c -#define EMAC_TXC_DEFER_OFFSET 0x0190 -#define EMAC_TXC_LATECL_OFFSET 0x0194 -#define EMAC_TXC_XS_COL_OFFSET 0x0198 -#define EMAC_TXC_DMAUND_OFFSET 0x019c -#define EMAC_TXC_CRSERR_OFFSET 0x01a0 -#define EMAC_TXC_UNICST_OFFSET 0x01a4 -#define EMAC_TXC_MULTI_OFFSET 0x01a8 -#define EMAC_TXC_BROAD_OFFSET 0x01ac -#define EMAC_TXC_ES_DFR_OFFSET 0x01b0 -#define EMAC_TXC_MACCTL_OFFSET 0x01b4 -#define EMAC_TXC_ALLFRM_OFFSET 0x01b8 -#define EMAC_TXC_ALLOCT_OFFSET 0x01bc -#define EMAC_TXC_EQ64_OFFSET 0x01c0 -#define EMAC_TXC_LT128_OFFSET 0x01c4 -#define EMAC_TXC_LT256_OFFSET 0x01c8 -#define EMAC_TXC_LT512_OFFSET 0x01cc -#define EMAC_TXC_LT1024_OFFSET 0x01d0 -#define EMAC_TXC_GE1024_OFFSET 0x01d4 -#define EMAC_TXC_ABORT_OFFSET 0x01d8 - - -/* register fields */ - -#define EMAC_OPMODE_DRO 0x10000000 -#define EMAC_OPMODE_LB 0x08000000 -#define EMAC_OPMODE_FDMODE 0x04000000 -#define EMAC_OPMODE_RMII_10 0x02000000 -#define EMAC_OPMODE_RMII 0x01000000 -#define EMAC_OPMODE_LCTRE 0x00800000 -#define EMAC_OPMODE_DRTY 0x00400000 -#define EMAC_OPMODE_BOLMT_MASK 0x00300000 -#define EMAC_OPMODE_BOLMT_1023 0x00000000 -#define EMAC_OPMODE_BOLMT_255 0x00100000 -#define EMAC_OPMODE_BOLMT_15 0x00200000 -#define EMAC_OPMODE_BOLMT_1 0x00300000 -#define EMAC_OPMODE_DC 0x00080000 -#define EMAC_OPMODE_DTXCRC 0x00040000 -#define EMAC_OPMODE_DTXPAD 0x00020000 -#define EMAC_OPMODE_TE 0x00010000 -#define EMAC_OPMODE_RAF 0x00001000 -#define EMAC_OPMODE_PSF 0x00000800 -#define EMAC_OPMODE_PBF 0x00000400 -#define EMAC_OPMODE_DBF 0x00000200 -#define EMAC_OPMODE_IFE 0x00000100 -#define EMAC_OPMODE_PR 0x00000080 -#define EMAC_OPMODE_PAM 0x00000040 -#define EMAC_OPMODE_HM 0x00000020 -#define EMAC_OPMODE_HU 0x00000010 -#define EMAC_OPMODE_ASTP 0x00000002 -#define EMAC_OPMODE_RE 0x00000001 - -#define EMAC_STAADD_PHYAD_MASK 0x0000f800 -#define EMAC_STAADD_PHYAD_SHIFT 11 -#define EMAC_STAADD_REGAD_MASK 0x000007c0 -#define EMAC_STAADD_REGAD_SHIFT 6 -#define EMAC_STAADD_STAIE 0x00000008 -#define EMAC_STAADD_STADISPRE 0x00000004 -#define EMAC_STAADD_STAOP 0x00000002 -#define EMAC_STAADD_STABUSY 0x00000001 - -#define EMAC_FLC_FLCPAUSE_MASK 0xffff0000 -#define EMAC_FLC_FLCPAUSE_SHIFT 16 -#define EMAC_FLC_BKPRSEN 0x00000008 -#define EMAC_FLC_PCF 0x00000004 -#define EMAC_FLC_FLCE 0x00000002 -#define EMAC_FLC_FLCBUSY 0x00000001 - -#define EMAC_WKUP_CTL_RWKS_MASK 0x00000f00 -#define EMAC_WKUP_CTL_RWKS_SHIFT 8 -#define EMAC_WKUP_CTL_MPKS 0x00000020 -#define EMAC_WKUP_CTL_GUWKE 0x00000008 -#define EMAC_WKUP_CTL_RWKE 0x00000004 -#define EMAC_WKUP_CTL_MPKE 0x00000002 -#define EMAC_WKUP_CTL_CAPWKFRM 0x00000001 - -#define EMAC_WKUP_FFCMD_3_TYPE 0x08000000 -#define EMAC_WKUP_FFCMD_3_EN 0x01000000 -#define EMAC_WKUP_FFCMD_2_TYPE 0x00080000 -#define EMAC_WKUP_FFCMD_2_EN 0x00010000 -#define EMAC_WKUP_FFCMD_1_TYPE 0x00000800 -#define EMAC_WKUP_FFCMD_1_EN 0x00000100 -#define EMAC_WKUP_FFCMD_0_TYPE 0x00000008 -#define EMAC_WKUP_FFCMD_0_EN 0x00000001 - -#define EMAC_WKUP_FFOFF_3_MASK 0xff000000 -#define EMAC_WKUP_FFOFF_3_SHIFT 24 -#define EMAC_WKUP_FFOFF_2_MASK 0x00ff0000 -#define EMAC_WKUP_FFOFF_2_SHIFT 16 -#define EMAC_WKUP_FFOFF_1_MASK 0x0000ff00 -#define EMAC_WKUP_FFOFF_1_SHIFT 8 -#define EMAC_WKUP_FFOFF_0_MASK 0x000000ff -#define EMAC_WKUP_FFOFF_0_SHIFT 0 - -#define EMAC_WKUP_FFCRC01_1_MASK 0xffff0000 -#define EMAC_WKUP_FFCRC01_1_SHIFT 16 -#define EMAC_WKUP_FFCRC01_0_MASK 0x0000ffff -#define EMAC_WKUP_FFCRC01_0_SHIFT 0 - -#define EMAC_WKUP_FFCRC23_3_MASK 0xffff0000 -#define EMAC_WKUP_FFCRC23_3_SHIFT 16 -#define EMAC_WKUP_FFCRC23_2_MASK 0x0000ffff -#define EMAC_WKUP_FFCRC23_2_SHIFT 0 - -#define EMAC_SYSCTL_MDCDIV_MASK 0x00003f00 -#define EMAC_SYSCTL_MDCDIV_SHIFT 8 -#define EMAC_SYSCTL_TXDWA 0x00000010 -#define EMAC_SYSCTL_RXCKS 0x00000004 -#define EMAC_SYSCTL_RXDWA 0x00000002 -#define EMAC_SYSCTL_PHYIE 0x00000001 - -#define EMAC_SYSTAT_STMDONE 0x00000080 -#define EMAC_SYSTAT_TXDMAERR 0x00000040 -#define EMAC_SYSTAT_RXDMAERR 0x00000020 -#define EMAC_SYSTAT_WAKEDET 0x00000010 -#define EMAC_SYSTAT_TXFSINT 0x00000008 -#define EMAC_SYSTAT_RXFSINT 0x00000004 -#define EMAC_SYSTAT_MMCINT 0x00000002 -#define EMAC_SYSTAT_PHYINT 0x00000001 - -#define EMAC_RX_STAT_RX_ACCEPT 0x80000000 -#define EMAC_RX_STAT_RX_VLAN2 0x40000000 -#define EMAC_RX_STAT_RX_VLAN1 0x20000000 -#define EMAC_RX_STAT_RX_TYPE 0x10000000 -#define EMAC_RX_STAT_RX_UCTL 0x08000000 -#define EMAC_RX_STAT_RX_CTL 0x04000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_MASK 0x03000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_ILLEGAL 0x03000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_BROADCAST 0x02000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_GROUP 0x01000000 -#define EMAC_RX_STAT_RX_BROAD_MULTI_UNICAST 0x00000000 -#define EMAC_RX_STAT_RX_RANGE 0x00800000 -#define EMAC_RX_STAT_RX_LATE 0x00400000 -#define EMAC_RX_STAT_RX_PHY 0x00200000 -#define EMAC_RX_STAT_RX_DMAO 0x00100000 -#define EMAC_RX_STAT_RX_ADDR 0x00080000 -#define EMAC_RX_STAT_RX_FRAG 0x00040000 -#define EMAC_RX_STAT_RX_LEN 0x00020000 -#define EMAC_RX_STAT_RX_CRC 0x00010000 -#define EMAC_RX_STAT_RX_ALIGN 0x00008000 -#define EMAC_RX_STAT_RX_LONG 0x00004000 -#define EMAC_RX_STAT_RX_OK 0x00002000 -#define EMAC_RX_STAT_RX_COMP 0x00001000 -#define EMAC_RX_STAT_RX_FRLEN_MASK 0x000007ff -#define EMAC_RX_STAT_RX_FRLEN_SHIFT 0 - -#define EMAC_RX_STKY_RX_ACCEPT 0x80000000 -#define EMAC_RX_STKY_RX_VLAN2 0x40000000 -#define EMAC_RX_STKY_RX_VLAN1 0x20000000 -#define EMAC_RX_STKY_RX_TYPE 0x10000000 -#define EMAC_RX_STKY_RX_UCTL 0x08000000 -#define EMAC_RX_STKY_RX_CTL 0x04000000 -#define EMAC_RX_STKY_RX_BROAD 0x02000000 -#define EMAC_RX_STKY_RX_MULTI 0x01000000 -#define EMAC_RX_STKY_RX_RANGE 0x00800000 -#define EMAC_RX_STKY_RX_LATE 0x00400000 -#define EMAC_RX_STKY_RX_PHY 0x00200000 -#define EMAC_RX_STKY_RX_DMAO 0x00100000 -#define EMAC_RX_STKY_RX_ADDR 0x00080000 -#define EMAC_RX_STKY_RX_FRAG 0x00040000 -#define EMAC_RX_STKY_RX_LEN 0x00020000 -#define EMAC_RX_STKY_RX_CRC 0x00010000 -#define EMAC_RX_STKY_RX_ALIGN 0x00008000 -#define EMAC_RX_STKY_RX_LONG 0x00004000 -#define EMAC_RX_STKY_RX_OK 0x00002000 -#define EMAC_RX_STKY_RX_COMP 0x00001000 - -#define EMAC_RX_IRQE_RX_ACCEPT 0x80000000 -#define EMAC_RX_IRQE_RX_VLAN2 0x40000000 -#define EMAC_RX_IRQE_RX_VLAN1 0x20000000 -#define EMAC_RX_IRQE_RX_TYPE 0x10000000 -#define EMAC_RX_IRQE_RX_UCTL 0x08000000 -#define EMAC_RX_IRQE_RX_CTL 0x04000000 -#define EMAC_RX_IRQE_RX_BROAD 0x02000000 -#define EMAC_RX_IRQE_RX_MULTI 0x01000000 -#define EMAC_RX_IRQE_RX_RANGE 0x00800000 -#define EMAC_RX_IRQE_RX_LATE 0x00400000 -#define EMAC_RX_IRQE_RX_PHY 0x00200000 -#define EMAC_RX_IRQE_RX_DMAO 0x00100000 -#define EMAC_RX_IRQE_RX_ADDR 0x00080000 -#define EMAC_RX_IRQE_RX_FRAG 0x00040000 -#define EMAC_RX_IRQE_RX_LEN 0x00020000 -#define EMAC_RX_IRQE_RX_CRC 0x00010000 -#define EMAC_RX_IRQE_RX_ALIGN 0x00008000 -#define EMAC_RX_IRQE_RX_LONG 0x00004000 -#define EMAC_RX_IRQE_RX_OK 0x00002000 -#define EMAC_RX_IRQE_RX_COMP 0x00001000 - -#define EMAC_TX_STAT_TX_FRLEN_MASK 0x07ff0000 -#define EMAC_TX_STAT_TX_FRLEN_SHIFT 16 -#define EMAC_TX_STAT_TX_RETRY 0x00008000 -#define EMAC_TX_STAT_TX_LOSS 0x00004000 -#define EMAC_TX_STAT_TX_CRS 0x00002000 -#define EMAC_TX_STAT_TX_DEFER 0x00001000 -#define EMAC_TX_STAT_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_STAT_TX_CCNT_SHIFT 8 -#define EMAC_TX_STAT_TX_MULTI_BROAD_MASK 0x000000c0 -#define EMAC_TX_STAT_TX_MULTI_BROAD_ILLEGAL 0x000000c0 -#define EMAC_TX_STAT_TX_MULTI_BROAD_GROUP 0x00000080 -#define EMAC_TX_STAT_TX_MULTI_BROAD_BROADCAST 0x00000040 -#define EMAC_TX_STAT_TX_MULTI_BROAD_UNICAST 0x00000000 -#define EMAC_TX_STAT_TX_EDEFER 0x00000020 -#define EMAC_TX_STAT_TX_DMAU 0x00000010 -#define EMAC_TX_STAT_TX_LATE 0x00000008 -#define EMAC_TX_STAT_TX_ECOLL 0x00000004 -#define EMAC_TX_STAT_TX_OK 0x00000002 -#define EMAC_TX_STAT_TX_COMP 0x00000001 - -#define EMAC_TX_STKY_TX_RETRY 0x00008000 -#define EMAC_TX_STKY_TX_LOSS 0x00004000 -#define EMAC_TX_STKY_TX_CRS 0x00002000 -#define EMAC_TX_STKY_TX_DEFER 0x00001000 -#define EMAC_TX_STKY_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_STKY_TX_CCNT_SHIFT 8 -#define EMAC_TX_STKY_TX_MULTI 0x00000080 -#define EMAC_TX_STKY_TX_BROAD 0x00000040 -#define EMAC_TX_STKY_TX_EDEFER 0x00000020 -#define EMAC_TX_STKY_TX_DMAU 0x00000010 -#define EMAC_TX_STKY_TX_LATE 0x00000008 -#define EMAC_TX_STAT_TX_ECOLL 0x00000004 -#define EMAC_TX_STAT_TX_OK 0x00000002 -#define EMAC_TX_STAT_TX_COMP 0x00000001 - -#define EMAC_TX_IRQE_TX_RETRY 0x00008000 -#define EMAC_TX_IRQE_TX_LOSS 0x00004000 -#define EMAC_TX_IRQE_TX_CRS 0x00002000 -#define EMAC_TX_IRQE_TX_DEFER 0x00001000 -#define EMAC_TX_IRQE_TX_CCNT_MASK 0x00000f00 -#define EMAC_TX_IRQE_TX_CCNT_SHIFT 8 -#define EMAC_TX_IRQE_TX_MULTI 0x00000080 -#define EMAC_TX_IRQE_TX_BROAD 0x00000040 -#define EMAC_TX_IRQE_TX_EDEFER 0x00000020 -#define EMAC_TX_IRQE_TX_DMAU 0x00000010 -#define EMAC_TX_IRQE_TX_LATE 0x00000008 -#define EMAC_TX_IRQE_TX_ECOLL 0x00000004 -#define EMAC_TX_IRQE_TX_OK 0x00000002 -#define EMAC_TX_IRQE_TX_COMP 0x00000001 - -#define EMAC_MMC_RIRQS_RX_GE1024_CNT 0x00800000 -#define EMAC_MMC_RIRQS_RX_LT1024_CNT 0x00400000 -#define EMAC_MMC_RIRQS_RX_LT512_CNT 0x00200000 -#define EMAC_MMC_RIRQS_RX_LT256_CNT 0x00100000 -#define EMAC_MMC_RIRQS_RX_LT128_CNT 0x00080000 -#define EMAC_MMC_RIRQS_RX_EQ64_CNT 0x00040000 -#define EMAC_MMC_RIRQS_RX_SHORT_CNT 0x00020000 -#define EMAC_MMC_RIRQS_RX_TYPED_CNT 0x00010000 -#define EMAC_MMC_RIRQS_RX_ALLO_CNT 0x00008000 -#define EMAC_MMC_RIRQS_RX_ALLF_CNT 0x00004000 -#define EMAC_MMC_RIRQS_RX_PAUSE_CNT 0x00002000 -#define EMAC_MMC_RIRQS_RX_OPCODE_CNT 0x00001000 -#define EMAC_MMC_RIRQS_RX_MACCTL_CNT 0x00000800 -#define EMAC_MMC_RIRQS_RX_LONG_CNT 0x00000400 -#define EMAC_MMC_RIRQS_RX_ORL_CNT 0x00000200 -#define EMAC_MMC_RIRQS_RX_IRL_CNT 0x00000100 -#define EMAC_MMC_RIRQS_RX_BROAD_CNT 0x00000080 -#define EMAC_MMC_RIRQS_RX_MULTI_CNT 0x00000040 -#define EMAC_MMC_RIRQS_RX_UNI_CNT 0x00000020 -#define EMAC_MMC_RIRQS_RX_LOST_CNT 0x00000010 -#define EMAC_MMC_RIRQS_RX_OCTET_CNT 0x00000008 -#define EMAC_MMC_RIRQS_RX_ALIGN_CNT 0x00000004 -#define EMAC_MMC_RIRQS_RX_FCS_CNT 0x00000002 -#define EMAC_MMC_RIRQS_RX_OK_CNT 0x00000001 - -#define EMAC_MMC_RIRQE_RX_GE1024_CNT 0x00800000 -#define EMAC_MMC_RIRQE_RX_LT1024_CNT 0x00400000 -#define EMAC_MMC_RIRQE_RX_LT512_CNT 0x00200000 -#define EMAC_MMC_RIRQE_RX_LT256_CNT 0x00100000 -#define EMAC_MMC_RIRQE_RX_LT128_CNT 0x00080000 -#define EMAC_MMC_RIRQE_RX_EQ64_CNT 0x00040000 -#define EMAC_MMC_RIRQE_RX_SHORT_CNT 0x00020000 -#define EMAC_MMC_RIRQE_RX_TYPED_CNT 0x00010000 -#define EMAC_MMC_RIRQE_RX_ALLO_CNT 0x00008000 -#define EMAC_MMC_RIRQE_RX_ALLF_CNT 0x00004000 -#define EMAC_MMC_RIRQE_RX_PAUSE_CNT 0x00002000 -#define EMAC_MMC_RIRQE_RX_OPCODE_CNT 0x00001000 -#define EMAC_MMC_RIRQE_RX_MACCTL_CNT 0x00000800 -#define EMAC_MMC_RIRQE_RX_LONG_CNT 0x00000400 -#define EMAC_MMC_RIRQE_RX_ORL_CNT 0x00000200 -#define EMAC_MMC_RIRQE_RX_IRL_CNT 0x00000100 -#define EMAC_MMC_RIRQE_RX_BROAD_CNT 0x00000080 -#define EMAC_MMC_RIRQE_RX_MULTI_CNT 0x00000040 -#define EMAC_MMC_RIRQE_RX_UNI_CNT 0x00000020 -#define EMAC_MMC_RIRQE_RX_LOST_CNT 0x00000010 -#define EMAC_MMC_RIRQE_RX_OCTET_CNT 0x00000008 -#define EMAC_MMC_RIRQE_RX_ALIGN_CNT 0x00000004 -#define EMAC_MMC_RIRQE_RX_FCS_CNT 0x00000002 -#define EMAC_MMC_RIRQE_RX_OK_CNT 0x00000001 - -#define EMAC_MMC_TIRQS_TX_ABORT_CNT 0x00400000 -#define EMAC_MMC_TIRQS_TX_GE1024_CNT 0x00200000 -#define EMAC_MMC_TIRQS_TX_LT1024_CNT 0x00100000 -#define EMAC_MMC_TIRQS_TX_LT512_CNT 0x00080000 -#define EMAC_MMC_TIRQS_TX_LT256_CNT 0x00040000 -#define EMAC_MMC_TIRQS_TX_LT128_CNT 0x00020000 -#define EMAC_MMC_TIRQS_TX_EQ64_CNT 0x00010000 -#define EMAC_MMC_TIRQS_TX_ALLO_CNT 0x00008000 -#define EMAC_MMC_TIRQS_TX_ALLF_CNT 0x00004000 -#define EMAC_MMC_TIRQS_TX_MACCTL_CNT 0x00002000 -#define EMAC_MMC_TIRQS_TX_EXDEF_CNT 0x00001000 -#define EMAC_MMC_TIRQS_TX_BROAD_CNT 0x00000800 -#define EMAC_MMC_TIRQS_TX_MULTI_CNT 0x00000400 -#define EMAC_MMC_TIRQS_TX_UNI_CNT 0x00000200 -#define EMAC_MMC_TIRQS_TX_CRS_CNT 0x00000100 -#define EMAC_MMC_TIRQS_TX_LOST_CNT 0x00000080 -#define EMAC_MMC_TIRQS_TX_ABORTC_CNT 0x00000040 -#define EMAC_MMC_TIRQS_TX_LATE_CNT 0x00000020 -#define EMAC_MMC_TIRQS_TX_DEFER_CNT 0x00000010 -#define EMAC_MMC_TIRQS_TX_OCTET_CNT 0x00000008 -#define EMAC_MMC_TIRQS_TX_MCOLL_CNT 0x00000004 -#define EMAC_MMC_TIRQS_TX_SCOLL_CNT 0x00000002 -#define EMAC_MMC_TIRQS_TX_OK_CNT 0x00000001 - -#define EMAC_MMC_TIRQE_TX_ABORT_CNT 0x00400000 -#define EMAC_MMC_TIRQE_TX_GE1024_CNT 0x00200000 -#define EMAC_MMC_TIRQE_TX_LT1024_CNT 0x00100000 -#define EMAC_MMC_TIRQE_TX_LT512_CNT 0x00080000 -#define EMAC_MMC_TIRQE_TX_LT256_CNT 0x00040000 -#define EMAC_MMC_TIRQE_TX_LT128_CNT 0x00020000 -#define EMAC_MMC_TIRQE_TX_EQ64_CNT 0x00010000 -#define EMAC_MMC_TIRQE_TX_ALLO_CNT 0x00008000 -#define EMAC_MMC_TIRQE_TX_ALLF_CNT 0x00004000 -#define EMAC_MMC_TIRQE_TX_MACCTL_CNT 0x00002000 -#define EMAC_MMC_TIRQE_TX_EXDEF_CNT 0x00001000 -#define EMAC_MMC_TIRQE_TX_BROAD_CNT 0x00000800 -#define EMAC_MMC_TIRQE_TX_MULTI_CNT 0x00000400 -#define EMAC_MMC_TIRQE_TX_UNI_CNT 0x00000200 -#define EMAC_MMC_TIRQE_TX_CRS_CNT 0x00000100 -#define EMAC_MMC_TIRQE_TX_LOST_CNT 0x00000080 -#define EMAC_MMC_TIRQE_TX_ABORTC_CNT 0x00000040 -#define EMAC_MMC_TIRQE_TX_LATE_CNT 0x00000020 -#define EMAC_MMC_TIRQE_TX_DEFER_CNT 0x00000010 -#define EMAC_MMC_TIRQE_TX_OCTET_CNT 0x00000008 -#define EMAC_MMC_TIRQE_TX_MCOLL_CNT 0x00000004 -#define EMAC_MMC_TIRQE_TX_SCOLL_CNT 0x00000002 -#define EMAC_MMC_TIRQE_TX_OK_CNT 0x00000001 - -#define EMAC_MMC_CTL_MMCE 0x00000008 -#define EMAC_MMC_CTL_CCOR 0x00000004 -#define EMAC_MMC_CTL_CROLL 0x00000002 -#define EMAC_MMC_CTL_RSTC 0x00000001 - - -#endif /* _ethernetRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/gpioRegs.h b/bsps/bfin/include/libcpu/gpioRegs.h deleted file mode 100644 index 02862916e1..0000000000 --- a/bsps/bfin/include/libcpu/gpioRegs.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Blackfin GPIO Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _gpioRegs_h_ -#define _gpioRegs_h_ - - -/* register addresses */ - -#define PORTIO_OFFSET 0x0000 -#define PORTIO_CLEAR_OFFSET 0x0004 -#define PORTIO_SET_OFFSET 0x0008 -#define PORTIO_TOGGLE_OFFSET 0x000c -#define PORTIO_MASKA_OFFSET 0x0010 -#define PORTIO_MASKA_CLEAR_OFFSET 0x0014 -#define PORTIO_MASKA_SET_OFFSET 0x0018 -#define PORTIO_MASKA_TOGGLE_OFFSET 0x001c -#define PORTIO_MASKB_OFFSET 0x0020 -#define PORTIO_MASKB_CLEAR_OFFSET 0x0024 -#define PORTIO_MASKB_SET_OFFSET 0x0028 -#define PORTIO_MASKB_TOGGLE_OFFSET 0x002c -#define PORTIO_DIR_OFFSET 0x0030 -#define PORTIO_POLAR_OFFSET 0x0034 -#define PORTIO_EDGE_OFFSET 0x0038 -#define PORTIO_BOTH_OFFSET 0x003c -#define PORTIO_INEN_OFFSET 0x0040 - - -#endif /* _gpioRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/interrupt.h b/bsps/bfin/include/libcpu/interrupt.h deleted file mode 100644 index 2c6b538bde..0000000000 --- a/bsps/bfin/include/libcpu/interrupt.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * RTEMS support for Blackfin interrupt controller - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _interrupt_h_ -#define _interrupt_h_ - -/* Some rules for using this module: - - SIC_IARx registers must not be changed after calling - bfin_interrupt_init(). - - The bfin_isr structures must stick around for as long as the isr is - registered. - - For any interrupt source (SIC bit) that could be shared, it is only - safe to disable an ISR through this module if the ultimate source is - also disabled (the ultimate source must be disabled prior to disabling - it through this module, and must remain disabled until after enabling - it through this module). - - For any source that is shared with modules that cannot be disabled, - give careful thought to the control of those interrupts. - bfin_interrupt_enable_all() or bfin_interrupt_enable_global() can - be used to help solve the problems caused by that. - - - Note that this module does not provide prioritization. It is assumed - that the priorities afforded by the CEC are sufficient. If finer - grained priority control is required then this wlll need to be - redesigned. -*/ - - -#ifdef __cplusplus -extern "C" { -#endif - -/* source is the source to the SIC (the bit number in SIC_ISR). isr is - the function that will be called when the interrupt is active. */ -typedef struct bfin_isr_s { - int source; - void (*isr)(int source); - /* the following are for internal use only */ - uint32_t mask; - int vector; - struct bfin_isr_s *next; -} bfin_isr_t; - -/* If non-default mapping is desired, the BSP should set the SIC_IARx - registers prior to calling this. */ -void bfin_interrupt_init(void); - -/* ISR starts out disabled */ -void bfin_interrupt_register(bfin_isr_t *isr); -void bfin_interrupt_unregister(bfin_isr_t *isr); - -/* enable/disable specific ISR */ -void bfin_interrupt_enable(bfin_isr_t *isr, bool enable); - -/* atomically enable/disable all ISRs attached to specified source */ -void bfin_interrupt_enable_all(int source, bool enable); - -/* disable a source independently of the individual ISR enables (starts - out all enabled) */ -void bfin_interrupt_enable_global(int source, bool enable); - -#ifdef __cplusplus -} -#endif - -#endif /* _interrupt_h_ */ - diff --git a/bsps/bfin/include/libcpu/memoryRegs.h b/bsps/bfin/include/libcpu/memoryRegs.h deleted file mode 100644 index 130235e3d1..0000000000 --- a/bsps/bfin/include/libcpu/memoryRegs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Blackfin Memory Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _memoryRegs_h_ -#define _memoryRegs_h_ - -/* register addresses */ -#define DMEM_CONTROL 0xffe00004 -#define DTEST_COMMAND 0xffe00300 -#define DTEST_DATA0 0xffe00400 -#define DTEST_DATA1 0xffe00404 - -#define IMEM_CONTROL 0xffe01004 - - -/* register fields */ -#define DMEM_CONTROL_PORT_PREF1 0x00002000 -#define DMEM_CONTROL_PORT_PREF0 0x00001000 -#define DMEM_CONTROL_DCBS 0x00000010 -#define DMEM_CONTROL_DMC_MASK 0x0000000c -#define DMEM_CONTROL_DMC_SHIFT 2 -#define DMEM_CONTROL_ENDCPLB 0x00000002 - -#define DTEST_COMMAND_ACCESS_WAY1 0x02000000 -#define DTEST_COMMAND_ACCESS_INSTRUCTION 0x01000000 -#define DTEST_COMMAND_ACCESS_BANKB 0x00800000 -#define DTEST_COMMAND_SRAM_ADDR_13_12_MASK 0x00030000 -#define DTEST_COMMAND_SRAM_ADDR_13_12_SHIFT 16 -#define DTEST_COMMAND_DATA_CACHE_SELECT 0x00004000 -#define DTEST_COMMAND_SET_INDEX_MASK 0x000007e0 -#define DTEST_COMMAND_SET_INDEX_SHIFT 5 -#define DTEST_COMMAND_DOUBLE_WORD_INDEX_MASK 0x00000018 -#define DTEST_COMMAND_DOUBLE_WORD_INDEX_SHIFT 3 -#define DTEST_COMMAND_ACCESS_DATA_ARRAY 0x00000004 -#define DTEST_COMMAND_WRITE_ACCESS 0x00000002 - -#define DTEST_DATA0_TAG_19_2_MASK 0xffffc000 -#define DTEST_DATA0_TAG_19_2_SHIFT 14 -#define DTEST_DATA0_TAG 0x00000800 -#define DTEST_DATA0_LRU 0x00000004 -#define DTEST_DATA0_DIRTY 0x00000002 -#define DTEST_DATA0_VALID 0x00000001 - -#define IMEM_CONTROL_LRUPRIORST 0x00002000 -#define IMEM_CONTROL_ILOC_MASK 0x00000078 -#define IMEM_CONTROL_ILOC_SHIFT 3 -#define IMEM_CONTROL_IMC 0x00000004 -#define IMEM_CONTROL_ENICPLB 0x00000002 - - -#endif /* _memoryRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/mmu.h b/bsps/bfin/include/libcpu/mmu.h deleted file mode 100644 index d6e2ea58a9..0000000000 --- a/bsps/bfin/include/libcpu/mmu.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Blackfin MMU Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -/* NOTE: this currently only implements a static table. It should be made - to handle more regions than fit in the CPLBs, with an exception handler - to do replacements as needed. This would of course require great care - to insure any storage required by the exception handler, including any - stack space, the exception handler itself, and the region descriptors - it needs to update the CPLBs, are in regions that will never be - replaced. */ - -#ifndef _mmu_h_ -#define _mmu_h_ - -#include - - -#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \ - ICPLB_DATA_CPLB_USER_RD | \ - ICPLB_DATA_CPLB_VALID) - -#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - -#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \ - DCPLB_DATA_CPLB_L1_CHBL | \ - DCPLB_DATA_CPLB_DIRTY | \ - DCPLB_DATA_CPLB_SUPV_WR | \ - DCPLB_DATA_CPLB_USER_WR | \ - DCPLB_DATA_CPLB_USER_RD | \ - DCPLB_DATA_CPLB_VALID) - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - struct { - void *address; - uint32_t flags; - } instruction[ICPLB_COUNT]; - struct { - void *address; - uint32_t flags; - } data[DCPLB_COUNT]; -} bfin_mmu_config_t; - - -void bfin_mmu_init(bfin_mmu_config_t *config); - - -#ifdef __cplusplus -} -#endif - -#endif /* _mmu_h_ */ - diff --git a/bsps/bfin/include/libcpu/mmuRegs.h b/bsps/bfin/include/libcpu/mmuRegs.h deleted file mode 100644 index 271ef4dcf5..0000000000 --- a/bsps/bfin/include/libcpu/mmuRegs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Blackfin MMU Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _mmuRegs_h_ -#define _mmuRegs_h_ - -/* register addresses */ -#define DCPLB_ADDR0 0xffe00100 -#define DCPLB_DATA0 0xffe00200 -#define DCPLB_COUNT 16 -#define DCPLB_ADDR_PITCH 4 -#define DCPLB_DATA_PITCH 4 -#define ICPLB_ADDR0 0xffe01100 -#define ICPLB_DATA0 0xffe01200 -#define ICPLB_COUNT 16 -#define ICPLB_ADDR_PITCH 4 -#define ICPLB_DATA_PITCH 4 - - -/* register fields */ -#define DCPLB_DATA_PAGE_SIZE_MASK 0x00030000 -#define DCPLB_DATA_PAGE_SIZE_1KB 0x00000000 -#define DCPLB_DATA_PAGE_SIZE_4KB 0x00010000 -#define DCPLB_DATA_PAGE_SIZE_1MB 0x00020000 -#define DCPLB_DATA_PAGE_SIZE_4MB 0x00030000 -#define DCPLB_DATA_CPLB_L1_AOW 0x00008000 -#define DCPLB_DATA_CPLB_WT 0x00004000 -#define DCPLB_DATA_CPLB_L1_CHBL 0x00001000 -#define DCPLB_DATA_CPLB_DIRTY 0x00000080 -#define DCPLB_DATA_CPLB_SUPV_WR 0x00000010 -#define DCPLB_DATA_CPLB_USER_WR 0x00000008 -#define DCPLB_DATA_CPLB_USER_RD 0x00000004 -#define DCPLB_DATA_CPLB_LOCK 0x00000002 -#define DCPLB_DATA_CPLB_VALID 0x00000001 - -#define ICPLB_DATA_PAGE_SIZE_MASK 0x00030000 -#define ICPLB_DATA_PAGE_SIZE_1KB 0x00000000 -#define ICPLB_DATA_PAGE_SIZE_4KB 0x00010000 -#define ICPLB_DATA_PAGE_SIZE_1MB 0x00020000 -#define ICPLB_DATA_PAGE_SIZE_4MB 0x00030000 -#define ICPLB_DATA_CPLB_L1_CHBL 0x00001000 -#define ICPLB_DATA_CPLB_LRUPRIO 0x00000100 -#define ICPLB_DATA_CPLB_USER_RD 0x00000004 -#define ICPLB_DATA_CPLB_LOCK 0x00000002 -#define ICPLB_DATA_CPLB_VALID 0x00000001 - -#endif /* _mmuRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/ppiRegs.h b/bsps/bfin/include/libcpu/ppiRegs.h deleted file mode 100644 index 0ff301aefc..0000000000 --- a/bsps/bfin/include/libcpu/ppiRegs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* Blackfin Parallel Peripheral Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _ppiRegs_h_ -#define _ppiRegs_h_ - - -/* register addresses */ - -#define PPI_CONTROL_OFFSET 0x0000 -#define PPI_STATUS_OFFSET 0x0004 -#define PPI_COUNT_OFFSET 0x0008 -#define PPI_DELAY_OFFSET 0x000c -#define PPI_FRAME_OFFSET 0x0010 - - -/* register fields */ - -#define PPI_CONTROL_POLS 0x8000 -#define PPI_CONTROL_POLC 0x4000 -#define PPI_CONTROL_DLEN_MASK 0x3800 -#define PPI_CONTROL_DLEN_8 0x0000 -#define PPI_CONTROL_DLEN_10 0x0800 -#define PPI_CONTROL_DLEN_11 0x1000 -#define PPI_CONTROL_DLEN_12 0x1800 -#define PPI_CONTROL_DLEN_13 0x2000 -#define PPI_CONTROL_DLEN_14 0x2800 -#define PPI_CONTROL_DLEN_15 0x3000 -#define PPI_CONTROL_DLEN_16 0x3800 -#define PPI_CONTROL_SKIP_EO 0x0400 -#define PPI_CONTROL_SKIP_EN 0x0200 -#define PPI_CONTROL_PACK_EN 0x0080 -#define PPI_CONTROL_FLD_SEL 0x0040 -#define PPI_CONTROL_PORT_CFG_MASK 0x0030 -#define PPI_CONTROL_PORT_CFG_SHIFT 4 -#define PPI_CONTROL_XFR_TYPE_MASK 0x000c -#define PPI_CONTROL_XFR_TYPE_SHIFT 2 -#define PPI_CONTROL_PORT_DIR 0x0002 -#define PPI_CONTROL_PORT_EN 0x0001 - -#define PPI_STATUS_ERR_NCOR 0x8000 -#define PPI_STATUS_ERR_DET 0x4000 -#define PPI_STATUS_UNDR 0x2000 -#define PPI_STATUS_OVR 0x1000 -#define PPI_STATUS_FT_ERR 0x0800 -#define PPI_STATUS_FLD 0x0400 -#define PPI_STATUS_LT_ERR_UNDR 0x0200 -#define PPI_STATUS_LT_ERR_OVR 0x0100 - - -#endif /* _ppiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/rtcRegs.h b/bsps/bfin/include/libcpu/rtcRegs.h deleted file mode 100644 index 09245c2b91..0000000000 --- a/bsps/bfin/include/libcpu/rtcRegs.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Blackfin RTC Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _rtcRegs_h_ -#define _rtcRegs_h_ - -/* register addresses */ - -#define RTC_STAT (RTC_BASE_ADDRESS + 0x0000) -#define RTC_ICTL (RTC_BASE_ADDRESS + 0x0004) -#define RTC_ISTAT (RTC_BASE_ADDRESS + 0x0008) -#define RTC_SWCNT (RTC_BASE_ADDRESS + 0x000c) -#define RTC_ALARM (RTC_BASE_ADDRESS + 0x0010) -#define RTC_PREN (RTC_BASE_ADDRESS + 0x0014) - - -/* register fields */ - -#define RTC_STAT_DAYS_MASK 0xfffe0000 -#define RTC_STAT_DAYS_SHIFT 17 -#define RTC_STAT_HOURS_MASK 0x0001f000 -#define RTC_STAT_HOURS_SHIFT 12 -#define RTC_STAT_MINUTES_MASK 0x00000fc0 -#define RTC_STAT_MINUTES_SHIFT 6 -#define RTC_STAT_SECONDS_MASK 0x0000003f -#define RTC_STAT_SECONDS_SHIFT 0 - -#define RTC_ICTL_WCIE 0x8000 -#define RTC_ICTL_DAIE 0x0040 -#define RTC_ICTL_24HIE 0x0020 -#define RTC_ICTL_HIE 0x0010 -#define RTC_ICTL_MIE 0x0008 -#define RTC_ICTL_SIE 0x0004 -#define RTC_ICTL_AIE 0x0002 -#define RTC_ICTL_SWIE 0x0001 - -#define RTC_ISTAT_WC 0x8000 -#define RTC_ISTAT_WP 0x4000 -#define RTC_ISTAT_DAEF 0x0040 -#define RTC_ISTAT_24HE 0x0020 -#define RTC_ISTAT_HEF 0x0010 -#define RTC_ISTAT_MEF 0x0008 -#define RTC_ISTAT_SEF 0x0004 -#define RTC_ISTAT_AEF 0x0002 -#define RTC_ISTAT_SWEF 0x0001 - -#define RTC_ALARM_DAYS_MASK 0xfff70000 -#define RTC_ALARM_DAYS_SHIFT 17 -#define RTC_ALARM_HOURS_MASK 0x0001f000 -#define RTC_ALARM_HOURS_SHIFT 12 -#define RTC_ALARM_MINUTES_MASK 0x00000fc0 -#define RTC_ALARM_MINUTES_SHIFT 10 -#define RTC_ALARM_SECONDS_MASK 0x0000003f -#define RTC_ALARM_SECONDS_SHIFT 0 - -#define RTC_PREN_PREN 0x0001 - -#endif /* _rtcRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/sicRegs.h b/bsps/bfin/include/libcpu/sicRegs.h deleted file mode 100644 index 79fdd0d77c..0000000000 --- a/bsps/bfin/include/libcpu/sicRegs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* Blackfin System Interrupt Controller Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sicRegs_h_ -#define _sicRegs_h_ - -/* register addresses */ - -#define SIC_IMASK (SIC_BASE_ADDRESS + 0x000c) -#define SIC_IMASK_PITCH (0x40) - -#define SIC_ISR (SIC_BASE_ADDRESS + 0x0020) -#define SIC_ISR_PITCH (0x40) - -#define SIC_IAR_BASE_ADDRESS (SIC_BASE_ADDRESS + 0x0010) -#define SIC_IAR_PITCH 0x04 - -#define SIC_IAR0 (SIC_BASE_ADDRESS + 0x0010) -#if SIC_IAR_COUNT > 1 -#define SIC_IAR1 (SIC_BASE_ADDRESS + 0x0014) -#endif -#if SIC_IAR_COUNT > 2 -#define SIC_IAR2 (SIC_BASE_ADDRESS + 0x0018) -#endif -#if SIC_IAR_COUNT > 3 -#define SIC_IAR3 (SIC_BASE_ADDRESS + 0x001c) -#endif - -#define SIC_IWR (SIC_BASE_ADDRESS + 0x0024) - - -/* register fields */ - - - -#endif /* _sicRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/spi.h b/bsps/bfin/include/libcpu/spi.h deleted file mode 100644 index db8bfaa612..0000000000 --- a/bsps/bfin/include/libcpu/spi.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * RTEMS driver for Blackfin SPI - * - * COPYRIGHT (c) 2010 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _spi_h -#define _spi_h - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - void *base; - /* remaining entries are for internal use */ - rtems_id sem; - int bytes_per_word; - uint16_t idle_pattern; - uint8_t *rd_ptr; - const uint8_t *wr_ptr; - int len; -} bfin_spi_state_t; - -typedef struct { - rtems_libi2c_bus_t bus; - bfin_spi_state_t p; -} bfin_spi_bus_t; - - -void bfin_spi_isr(int v); - -rtems_status_code bfin_spi_init(rtems_libi2c_bus_t *bus); - -rtems_status_code bfin_spi_send_start(rtems_libi2c_bus_t *bus); - -int bfin_spi_read_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); - -int bfin_spi_write_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len); - -int bfin_spi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg); - -#ifdef __cplusplus -} -#endif - - -#endif /* _spi_h */ diff --git a/bsps/bfin/include/libcpu/spiRegs.h b/bsps/bfin/include/libcpu/spiRegs.h deleted file mode 100644 index dcf792bb69..0000000000 --- a/bsps/bfin/include/libcpu/spiRegs.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Blackfin SPI Registers - * - * Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _spiRegs_h_ -#define _spiRegs_h_ - - -/* register addresses */ - -#define SPI_CTL_OFFSET 0x0000 -#define SPI_FLG_OFFSET 0x0004 -#define SPI_STAT_OFFSET 0x0008 -#define SPI_TDBR_OFFSET 0x000c -#define SPI_RDBR_OFFSET 0x0010 -#define SPI_BAUD_OFFSET 0x0014 -#define SPI_SHADOW_OFFSET 0x0018 - - -/* register fields */ - -#define SPI_CTL_SPE 0x4000 -#define SPI_CTL_WOM 0x2000 -#define SPI_CTL_MSTR 0x1000 -#define SPI_CTL_CPOL 0x0800 -#define SPI_CTL_CPHA 0x0400 -#define SPI_CTL_LSBF 0x0200 -#define SPI_CTL_SIZE 0x0100 -#define SPI_CTL_EMISO 0x0020 -#define SPI_CTL_PSSE 0x0010 -#define SPI_CTL_GM 0x0008 -#define SPI_CTL_SZ 0x0004 -#define SPI_CTL_TIMOD_MASK 0x0003 -#define SPI_CTL_TIMOD_RDBR 0x0000 -#define SPI_CTL_TIMOD_TDBR 0x0001 -#define SPI_CTL_TIMOD_DMA_RDBR 0x0002 -#define SPI_CTL_TIMOD_DMA_TDBR 0x0003 - -#define SPI_FLG_FLG7 0x8000 -#define SPI_FLG_FLG6 0x4000 -#define SPI_FLG_FLG5 0x2000 -#define SPI_FLG_FLG4 0x1000 -#define SPI_FLG_FLG3 0x0800 -#define SPI_FLG_FLG2 0x0400 -#define SPI_FLG_FLG1 0x0200 -#define SPI_FLG_FLS7 0x0080 -#define SPI_FLG_FLS6 0x0040 -#define SPI_FLG_FLS5 0x0020 -#define SPI_FLG_FLS4 0x0010 -#define SPI_FLG_FLS3 0x0008 -#define SPI_FLG_FLS2 0x0004 -#define SPI_FLG_FLS1 0x0002 - -#define SPI_STAT_TXCOL 0x0040 -#define SPI_STAT_RXS 0x0020 -#define SPI_STAT_RBSY 0x0010 -#define SPI_STAT_TXS 0x0008 -#define SPI_STAT_TXE 0x0004 -#define SPI_STAT_MODF 0x0002 -#define SPI_STAT_SPIF 0x0001 - - -#endif /* _spiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/sport.h b/bsps/bfin/include/libcpu/sport.h deleted file mode 100644 index 6ed481b593..0000000000 --- a/bsps/bfin/include/libcpu/sport.h +++ /dev/null @@ -1,2 +0,0 @@ -/* placeholder */ - diff --git a/bsps/bfin/include/libcpu/sportRegs.h b/bsps/bfin/include/libcpu/sportRegs.h deleted file mode 100644 index f9f263b024..0000000000 --- a/bsps/bfin/include/libcpu/sportRegs.h +++ /dev/null @@ -1,111 +0,0 @@ -/* Blackfin SPORT Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _sportRegs_h_ -#define _sportRegs_h_ - - -/* register addresses */ - -#define SPORT_TCR1_OFFSET 0x0000 -#define SPORT_TCR2_OFFSET 0x0004 -#define SPORT_TCLKDIV_OFFSET 0x0008 -#define SPORT_TFSDIV_OFFSET 0x000c -#define SPORT_TX_OFFSET 0x0010 -#define SPORT_RX_OFFSET 0x0018 -#define SPORT_RCR1_OFFSET 0x0020 -#define SPORT_RCR2_OFFSET 0x0024 -#define SPORT_RCLKDIV_OFFSET 0x0028 -#define SPORT_RFSDIV_OFFSET 0x002c -#define SPORT_STAT_OFFSET 0x0030 -#define SPORT_CHNL_OFFSET 0x0034 -#define SPORT_MCMC1_OFFSET 0x0038 -#define SPORT_MCMC2_OFFSET 0x003c -#define SPORT_MTCS0_OFFSET 0x0040 -#define SPORT_MTCS1_OFFSET 0x0044 -#define SPORT_MTCS2_OFFSET 0x0048 -#define SPORT_MTCS3_OFFSET 0x004c -#define SPORT_MRCS0_OFFSET 0x0050 -#define SPORT_MRCS1_OFFSET 0x0054 -#define SPORT_MRCS2_OFFSET 0x0058 -#define SPORT_MRCS3_OFFSET 0x005c - - -/* register fields */ - -#define SPORT_TCR1_TCKFE 0x4000 -#define SPORT_TCR1_LATFS 0x2000 -#define SPORT_TCR1_LTFS 0x1000 -#define SPORT_TCR1_DITFS 0x0800 -#define SPORT_TCR1_TFSR 0x0400 -#define SPORT_TCR1_ITFS 0x0200 -#define SPORT_TCR1_TLSBIT 0x0010 -#define SPORT_TCR1_TDTYPE_MASK 0x000c -#define SPORT_TCR1_TDTYPE_NORMAL 0x0000 -#define SPORT_TCR1_TDTYPE_ULAW 0x0008 -#define SPORT_TCR1_TDTYPE_ALAW 0x000c -#define SPORT_TCR1_ITCLK 0x0002 -#define SPORT_TCR1_TSPEN 0x0001 - -#define SPORT_TCR2_TRFST 0x0400 -#define SPORT_TCR2_TSFSE 0x0200 -#define SPORT_TCR2_TXSE 0x0100 -#define SPORT_TCR2_SLEN_MASK 0x001f -#define SPORT_TCR2_SLEN_SHIFT 0 - -#define SPORT_RCR1_RCKFE 0x4000 -#define SPORT_RCR1_LARFS 0x2000 -#define SPORT_RCR1_LRFS 0x1000 -#define SPORT_RCR1_RFSR 0x0400 -#define SPORT_RCR1_IRFS 0x0200 -#define SPORT_RCR1_RLSBIT 0x0010 -#define SPORT_RCR1_RDTYPE_MASK 0x000c -#define SPORT_RCR1_RDTYPE_ZEROFILL 0x0000 -#define SPORT_RCR1_RDTYPE_SIGNEXTEND 0x0004 -#define SPORT_RCR1_RDTYPE_ULAW 0x0008 -#define SPORT_RCR1_RDTYPE_ALAW 0x000c -#define SPORT_RCR1_IRCLK 0x0002 -#define SPORT_RCR1_RSPEN 0x0001 - -#define SPORT_RCR2_RRFST 0x0400 -#define SPORT_RCR2_RSFSE 0x0200 -#define SPORT_RCR2_RXSE 0x0100 -#define SPORT_RCR2_SLEN_MASK 0x001f -#define SPORT_RCR2_SLEN_SHIFT 0 - -#define SPORT_STAT_TXHRE 0x0040 -#define SPORT_STAT_TOVF 0x0020 -#define SPORT_STAT_TUVF 0x0010 -#define SPORT_STAT_TXF 0x0008 -#define SPORT_STAT_ROVF 0x0004 -#define SPORT_STAT_RUVF 0x0002 -#define SPORT_STAT_RXNE 0x0001 - -#define SPORT_CHNL_CHNL_MASK 0x03ff -#define SPORT_CHNL_CHNL_SHIFT 0 - -#define SPORT_MCMC1_WSIZE_MASK 0xf000 -#define SPORT_MCMC1_WSIZE_SHIFT 12 -#define SPORT_MCMC1_WOFF_MASK 0x03ff -#define SPORT_MCMC1_WOFF_SHIFT 0 - -#define SPORT_MCMC2_MFD_MASK 0xf000 -#define SPORT_MCMC2_MFD_SHIFT 12 -#define SPORT_MCMC2_FSDR 0x0080 -#define SPORT_MCMC2_MCMEN 0x0010 -#define SPORT_MCMC2_MCDRXPE 0x0008 -#define SPORT_MCMC2_MCDTXPE 0x0004 -#define SPORT_MCMC2_MCCRM_MASK 0x0003 -#define SPORT_MCMC2_MCCRM_BYPASS 0x0000 -#define SPORT_MCMC2_MCCRM_2_4 0x0002 -#define SPORT_MCMC2_MCCRM_8_16 0x0003 - - -#endif /* _sportRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/timerRegs.h b/bsps/bfin/include/libcpu/timerRegs.h deleted file mode 100644 index b66bae3339..0000000000 --- a/bsps/bfin/include/libcpu/timerRegs.h +++ /dev/null @@ -1,45 +0,0 @@ -/* Blackfin General Purpose Timer Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _timerRegs_h_ -#define _timerRegs_h_ - - -/* register addresses */ - -#define TIMER_CONFIG_OFFSET 0x00 -#define TIMER_WIDTH_OFFSET 0x04 -#define TIMER_PERIOD_OFFSET 0x08 -#define TIMER_COUNTER_OFFSET 0x0c - - -/* register fields */ - -#define TIMER_CONFIG_ERR_TYP_MASK 0xc000 -#define TIMER_CONFIG_ERR_TYP_NONE 0x0000 -#define TIMER_CONFIG_ERR_TYP_OVERFLOW 0x4000 -#define TIMER_CONFIG_ERR_TYP_PERIOD 0x8000 -#define TIMER_CONFIG_ERR_TYP_WIDTH 0xc000 -#define TIMER_CONFIG_EMU_RUN 0x0200 -#define TIMER_CONFIG_TOGGLE_HI 0x0100 -#define TIMER_CONFIG_CLK_SEL 0x0080 -#define TIMER_CONFIG_OUT_DIS 0x0040 -#define TIMER_CONFIG_TIN_SEL 0x0020 -#define TIMER_CONFIG_IRQ_ENA 0x0010 -#define TIMER_CONFIG_PERIOD_CNT 0x0008 -#define TIMER_CONFIG_PULSE_HI 0x0004 -#define TIMER_CONFIG_TMODE_MASK 0x0003 -#define TIMER_CONFIG_TMODE_RESET 0x0000 -#define TIMER_CONFIG_TMODE_PWM_OUT 0x0001 -#define TIMER_CONFIG_TMODE_WDTH_CAP 0x0002 -#define TIMER_CONFIG_TMODE_EXT_CLK 0x0003 - - -#endif /* _timerRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/twi.h b/bsps/bfin/include/libcpu/twi.h deleted file mode 100644 index 2392ba532b..0000000000 --- a/bsps/bfin/include/libcpu/twi.h +++ /dev/null @@ -1,68 +0,0 @@ -/* not yet implemented */ - -/* - * RTEMS driver for Blackfin TWI (I2C) - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _twi_h_ -#define _twi_h_ - - -#ifdef __cplusplus -extern "C" { -#endif - - -typedef struct { - uint32_t sclk; - void *base; - bool fast; - int8_t slave_address; -} bfin_twi_config_t; - -typedef struct bfin_twi_request_s { - bool write; - int count; - void *data; - /* Chained requests are done with repeated start conditions in between. - These are useful for atomic address write/data read transactions - (which can be important in multi-master configurations), and for - doing 10-bit addressing. */ - struct bfin_twi_request_s *next; -} bfin_twi_request_t; - -typedef rtems_status_code (*bfin_twi_callback_t)(int channel, - void *arg, - bool general_call, - bool write, - bool done, - int read_count, - uint8_t *data); - - -rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config); - -rtems_status_code bfin_twi_register_callback(int channel, - bfin_twi_callback_t callback, - void *arg); - -void bfin_twi_isr(int source); - -rtems_status_code bfin_twi_request(int channel, uint8_t address, - bfin_twi_request_t *request, - rtems_interval timeout); - - -#ifdef __cplusplus -} -#endif - -#endif /* _twi_h_ */ - diff --git a/bsps/bfin/include/libcpu/twiRegs.h b/bsps/bfin/include/libcpu/twiRegs.h deleted file mode 100644 index c776f7886e..0000000000 --- a/bsps/bfin/include/libcpu/twiRegs.h +++ /dev/null @@ -1,118 +0,0 @@ -/* Blackfin Two Wire Interface Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _twiRegs_h_ -#define _twiRegs_h_ - - -/* register addresses */ - -#define TWI_CLKDIV_OFFSET 0x0000 -#define TWI_CONTROL_OFFSET 0x0004 -#define TWI_SLAVE_CTL_OFFSET 0x0008 -#define TWI_SLAVE_STAT_OFFSET 0x000c -#define TWI_SLAVE_ADDR_OFFSET 0x0010 -#define TWI_MASTER_CTL_OFFSET 0x0014 -#define TWI_MASTER_STAT_OFFSET 0x0018 -#define TWI_MASTER_ADDR_OFFSET 0x001c -#define TWI_INT_STAT_OFFSET 0x0020 -#define TWI_INT_MASK_OFFSET 0x0024 -#define TWI_FIFO_CTL_OFFSET 0x0028 -#define TWI_FIFO_STAT_OFFSET 0x002c -#define TWI_XMT_DATA8_OFFSET 0x0080 -#define TWI_XMT_DATA16_OFFSET 0x0084 -#define TWI_RCV_DATA8_OFFSET 0x0088 -#define TWI_RCV_DATA16_OFFSET 0x008c - - -/* register fields */ - -#define TWI_CLKDIV_CLKHI_MASK 0xff00 -#define TWI_CLKDIV_CLKHI_SHIFT 8 -#define TWI_CLKDIV_CLKLOW_MASK 0x00ff -#define TWI_CLKDIV_CLKLOW_SHIFT 0 - -#define TWI_CONTROL_SCCB 0x0200 -#define TWI_CONTROL_TWI_ENA 0x0080 -#define TWI_CONTROL_PRESCALE_MASK 0x007f -#define TWI_CONTROL_PRESCALE_SHIFT 0 - -#define TWI_SLAVE_CTL_GEN 0x0010 -#define TWI_SLAVE_CTL_NAK 0x0008 -#define TWI_SLAVE_CTL_STDVAL 0x0004 -#define TWI_SLAVE_CTL_SEN 0x0001 - -#define TWI_SLAVE_STAT_GCALL 0x0002 -#define TWI_SLAVE_STAT_SDIR 0x0001 - -#define TWI_SLAVE_ADDR_SADDR_MASK 0x007f -#define TWI_SLAVE_ADDR_SADDR_SHIFT 0 - -#define TWI_MASTER_CTL_SCLOVR 0x8000 -#define TWI_MASTER_CTL_SDAOVR 0x4000 -#define TWI_MASTER_CTL_DCNT_MASK 0x3fc0 -#define TWI_MASTER_CTL_DCNT_SHIFT 6 -#define TWI_MASTER_CTL_RSTART 0x0020 -#define TWI_MASTER_CTL_STOP 0x0010 -#define TWI_MASTER_CTL_FAST 0x0008 -#define TWI_MASTER_CTL_MDIR 0x0004 -#define TWI_MASTER_CTL_MEN 0x0001 - -#define TWI_MASTER_STAT_BUSBUSY 0x0100 -#define TWI_MASTER_STAT_SCLSEN 0x0080 -#define TWI_MASTER_STAT_SDASEN 0x0040 -#define TWI_MASTER_STAT_BUFWRERR 0x0020 -#define TWI_MASTER_STAT_BUFRDERR 0x0010 -#define TWI_MASTER_STAT_DNAK 0x0008 -#define TWI_MASTER_STAT_ANAK 0x0004 -#define TWI_MASTER_STAT_LOSTARB 0x0002 -#define TWI_MASTER_STAT_MPROG 0x0001 - -#define TWI_MASTER_ADDR_MADDR_MASK 0x007f -#define TWI_MASTER_ADDR_MADDR_SHIFT 0 - -#define TWI_INT_STAT_RCVSERV 0x0080 -#define TWI_INT_STAT_XMTSERV 0x0040 -#define TWI_INT_STAT_MERR 0x0020 -#define TWI_INT_STAT_MCOMP 0x0010 -#define TWI_INT_STAT_SOVF 0x0008 -#define TWI_INT_STAT_SERR 0x0004 -#define TWI_INT_STAT_SCOMP 0x0002 -#define TWI_INT_STAT_SINIT 0x0001 - -#define TWI_INT_MASK_RCVSERVM 0x0080 -#define TWI_INT_MASK_XMTSERVM 0x0040 -#define TWI_INT_MASK_MERRM 0x0020 -#define TWI_INT_MASK_MCOMPM 0x0010 -#define TWI_INT_MASK_SOVFM 0x0008 -#define TWI_INT_MASK_SERRM 0x0004 -#define TWI_INT_MASK_SCOMPM 0x0002 -#define TWI_INT_MASK_SINITM 0x0001 - -#define TWI_FIFO_CTL_RCVINTLEN 0x0008 -#define TWI_FIFO_CTL_XMTINTLEN 0x0004 -#define TWI_FIFO_CTL_RCVFLUSH 0x0002 -#define TWI_FIFO_CTL_XMTFLUSH 0x0001 - -#define TWI_FIFO_STAT_RCVSTAT_MASK 0x000c -#define TWI_FIFO_STAT_RCVSTAT_EMPTY 0x0000 -#define TWI_FIFO_STAT_RCVSTAT_SHIFT 2 -#define TWI_FIFO_STAT_XMTSTAT_MASK 0x0003 -#define TWI_FIFO_STAT_XMTSTAT_FULL 0x0003 -#define TWI_FIFO_STAT_XMTSTAT_SHIFT 0 - -#define TWI_XMT_DATA8_XMTDATA8_MASK 0x00ff -#define TWI_XMT_DATA8_XMTDATA8_SHIFT 0 - -#define TWI_RCV_DATA8_RCVDATA8_MASK 0x00ff -#define TWI_RCV_DATA8_RCVDATA8_SHIFT 0 - - -#endif /* _twiRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/uart.h b/bsps/bfin/include/libcpu/uart.h deleted file mode 100644 index 730e0e261f..0000000000 --- a/bsps/bfin/include/libcpu/uart.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * RTEMS driver for Blackfin UARTs - * - * COPYRIGHT (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#ifndef _UART_H_ -#define _UART_H_ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** bfin_uart_channel object - */ -typedef struct { - const char *name; /** Holds name of the device */ - uint32_t uart_baseAddress; /** UART base address */ - uint32_t uart_rxDmaBaseAddress; /** RX DMA base address */ - uint32_t uart_txDmaBaseAddress; /** TX DMA base address */ - bool uart_useInterrupts; /** are interrupts used */ - bool uart_useDma; /** is dma used */ - int uart_baud; /** baud rate, 0 for default */ - - void *termios; /** termios associated */ - uint8_t volatile flags; /** flags for internal use */ - uint16_t length; /** length for internal use */ -} bfin_uart_channel_t; - - -typedef struct { - uint32_t freq; - int num_channels; - bfin_uart_channel_t *channels; -} bfin_uart_config_t; - -/** - * @param base_address defines the UART base address - * @param source defines the source that caused the interrupt. This argument - * will help us in identifying if Rx or TX caused the interrupt. - */ -typedef struct { - uint32_t base_address; - int source; -} bfin_uart_arg_t; - - - -char bfin_uart_poll_read(rtems_device_minor_number minor); - -void bfin_uart_poll_write(int minor, char c); - - -/** -* Uart initialization function. -* @param major major number of the device -* @param config configuration parameters -* @return rtems status code -*/ -rtems_status_code bfin_uart_initialize(rtems_device_major_number major, - bfin_uart_config_t *config); - - - -/** - * Opens the device in different modes. The supported modes are - * 1. Polling - * 2. Interrupt - * 3. DMA - * At exit the uart_Exit function will be called to flush the device. - * - * @param major Major number of the device - * @param minor Minor number of the device - * @param arg - * @return - */ -rtems_device_driver bfin_uart_open(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg); - - - -/** - * This function implements TX dma ISR. It clears the IRQ and dequeues a char - * The channel argument will have the base address. Since there are two uart - * and both the uarts can use the same tx dma isr. - * - * TODO: 1. Error checking 2. sending correct length ie after looking at the - * number of elements the uart transmitted. - * - * @param _arg argument passed to the interrupt handler. It contains the - * channel argument. - */ -void bfinUart_txDmaIsr(void *_arg); - - - -/** - * RX DMA ISR. - * The polling route is used for receiving the characters. This is a place - * holder for future implementation. - * @param _arg - */ -void bfinUart_rxDmaIsr(void *_arg); - - -/** - * This function implements TX ISR. The function gets called when the TX FIFO is - * empty. It clears the interrupt and dequeues the character. It only tx one - * character at a time. - * - * TODO: error handling. - * @param _arg gets the channel information. - */ -void bfinUart_txIsr(void *_arg); - - -/** -* This function implements RX ISR -*/ -void bfinUart_rxIsr(void *_arg); - - -#ifdef __cplusplus -} -#endif - -#endif /* _UART_H_ */ - diff --git a/bsps/bfin/include/libcpu/uartRegs.h b/bsps/bfin/include/libcpu/uartRegs.h deleted file mode 100644 index f48052e49b..0000000000 --- a/bsps/bfin/include/libcpu/uartRegs.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Blackfin UART Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _uartRegs_h_ -#define _uartRegs_h_ - -/* register addresses */ - -#define UART_RBR_OFFSET 0x0000 -#define UART_THR_OFFSET 0x0000 -#define UART_DLL_OFFSET 0x0000 -#define UART_IER_OFFSET 0x0004 -#define UART_DLH_OFFSET 0x0004 -#define UART_IIR_OFFSET 0x0008 -#define UART_LCR_OFFSET 0x000c -#define UART_MCR_OFFSET 0x0010 -#define UART_LSR_OFFSET 0x0014 -#define UART_SCR_OFFSET 0x001c -#define UART_GCTL_OFFSET 0x0024 - - -/* register fields */ - -#define UART_LCR_DLAB 0x80 -#define UART_LCR_SB 0x40 -#define UART_LCR_STP 0x20 -#define UART_LCR_EPS 0x10 -#define UART_LCR_PEN 0x08 -#define UART_LCR_STB 0x04 -#define UART_LCR_WLS_MASK 0x03 -#define UART_LCR_WLS_5 0x00 -#define UART_LCR_WLS_6 0x01 -#define UART_LCR_WLS_7 0x02 -#define UART_LCR_WLS_8 0x03 - -#define UART_MCR_LOOP 0x10 - -#define UART_LSR_TEMT 0x40 -#define UART_LSR_THRE 0x20 -#define UART_LSR_BI 0x10 -#define UART_LSR_FE 0x08 -#define UART_LSR_PE 0x04 -#define UART_LSR_OE 0x02 -#define UART_LSR_DR 0x01 - -#define UART_IER_ELSI 0x04 -#define UART_IER_ETBEI 0x02 -#define UART_IER_ERBFI 0x01 - -#define UART_IIR_STATUS_MASK 0x06 -#define UART_IIR_STATUS_THRE 0x02 -#define UART_IIR_STATUS_RDR 0x04 -#define UART_IIR_STATUS_LS 0x06 -#define UART_IIR_NINT 0x01 - -#define UART_GCTL_FFE 0x20 -#define UART_GCTL_FPE 0x10 -#define UART_GCTL_RPOLC 0x08 -#define UART_GCTL_TPOLC 0x04 -#define UART_GCTL_IREN 0x02 -#define UART_GCTL_UCEN 0x01 - -#endif /* _uartRegs_h_ */ diff --git a/bsps/bfin/include/libcpu/wdogRegs.h b/bsps/bfin/include/libcpu/wdogRegs.h deleted file mode 100644 index 9e76d345b0..0000000000 --- a/bsps/bfin/include/libcpu/wdogRegs.h +++ /dev/null @@ -1,33 +0,0 @@ -/* Blackfin Watchdog Registers - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _wdogRegs_h_ -#define _wdogRegs_h_ - -/* register addresses */ - -#define WDOG_CTL (WDOG_BASE_ADDRESS + 0x0000) -#define WDOG_CNT (WDOG_BASE_ADDRESS + 0x0004) -#define WDOG_STAT (WDOG_BASE_ADDRESS + 0x0008) - - -/* register fields */ - -#define WDOG_CTL_WDRO 0x8000 -#define WDOG_CTL_WDEN_MASK 0x0ff0 -#define WDOG_CTL_WDEN_DISABLE 0x0ad0 -#define WDOG_CTL_WDEV_MASK 0x0006 -#define WDOG_CTL_WDEV_RESET 0x0000 -#define WDOG_CTL_WDEV_NMI 0x0002 -#define WDOG_CTL_WDEV_GPI 0x0004 -#define WDOG_CTL_WDEV_DISABLE 0x0006 - - -#endif /* _wdogRegs_h_ */ diff --git a/bsps/bfin/shared/cache/cache.c b/bsps/bfin/shared/cache/cache.c deleted file mode 100644 index ea5061bc9c..0000000000 --- a/bsps/bfin/shared/cache/cache.c +++ /dev/null @@ -1,134 +0,0 @@ -/* Blackfin Cache Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include - -#define CPU_DATA_CACHE_ALIGNMENT 32 -#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 - -#ifdef BSP_DATA_CACHE_CONFIG -#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG -#else -/* use 16K of each SRAM bank */ -#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT) -#endif - -/* There are many syncs in the following code because they should be - harmless except for wasting time, and this is easier than figuring out - exactly where they're needed to protect from the effects of write - buffers and queued reads. Many of them are likely unnecessary. */ - - -static void _CPU_cache_flush_1_data_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr)); -} - -/* Blackfins can't just invalidate cache; they can only do flush + - invalidate. If the line isn't dirty then this is equivalent to - just an invalidate. Even if it is dirty, this should still be - okay since with a pure invalidate method the caller would have no - way to insure the dirty line hadn't been written out anyway prior - to the invalidate. */ -static void _CPU_cache_invalidate_1_data_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr)); -} - -static void _CPU_cache_freeze_data(void) { -} - -static void _CPU_cache_unfreeze_data(void) { -} - -static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) { - - __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr)); -} - -static void _CPU_cache_freeze_instruction(void) { -} - -static void _CPU_cache_unfreeze_instruction(void) { -} - -/* incredibly inefficient... It would be better to make use of the - DTEST_COMMAND/DTEST_DATAx registers to find the addresses in each - cache line and flush just those. However the documentation I've - seen on those is a bit sketchy, and I sure wouldn't want to get it - wrong. */ -static void _CPU_cache_flush_entire_data(void) { - uint32_t i; - - i = 0; - __asm__ __volatile__ ("ssync"); - do { - __asm__ __volatile__ ("flush [%0]" :: "a" (i)); - i += CPU_DATA_CACHE_ALIGNMENT; - } while (i); - __asm__ __volatile__ ("ssync"); -} - -static void _CPU_cache_invalidate_entire_data(void) { - uint32_t dmemControl; - - __asm__ __volatile__ ("ssync"); - dmemControl = *(uint32_t volatile *) DMEM_CONTROL; - *(uint32_t volatile *) DMEM_CONTROL = dmemControl & ~DMEM_CONTROL_DMC_MASK; - *(uint32_t volatile *) DMEM_CONTROL = dmemControl; - __asm__ __volatile__ ("ssync"); -} - -/* this does not actually enable data cache unless CPLBs are also enabled. - LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */ -static void _CPU_cache_enable_data(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG; - __asm__ __volatile__ ("ssync"); -} - -static void _CPU_cache_disable_data(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK; - __asm__ __volatile__ ("ssync"); -} - -static void _CPU_cache_invalidate_entire_instruction(void) { - uint32_t imemControl; - - __asm__ __volatile__ ("ssync"); - imemControl = *(uint32_t volatile *) IMEM_CONTROL; - *(uint32_t volatile *) IMEM_CONTROL = imemControl & ~IMEM_CONTROL_IMC; - *(uint32_t volatile *) IMEM_CONTROL = imemControl; - __asm__ __volatile__ ("ssync"); -} - -/* this only actually enables the instruction cache if the CPLBs are also - enabled. */ -static void _CPU_cache_enable_instruction(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC; - __asm__ __volatile__ ("ssync"); -} - -static void _CPU_cache_disable_instruction(void) { - - __asm__ __volatile__ ("ssync"); - *(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC; - __asm__ __volatile__ ("ssync"); -} - -#include "../../../shared/cache/cacheimpl.h" diff --git a/bsps/bfin/shared/dev/clock.c b/bsps/bfin/shared/dev/clock.c deleted file mode 100644 index 4d500f6ccb..0000000000 --- a/bsps/bfin/shared/dev/clock.c +++ /dev/null @@ -1,69 +0,0 @@ -/* RTEMS Clock Tick Driver for Blackfin. Uses Blackfin Core Timer. - */ - -/* - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include -#include -#include -#include -#include - - -#include -#include - -#if (BFIN_ON_SKYEYE) -#define CLOCK_DRIVER_USE_FAST_IDLE 1 -#endif - -volatile uint32_t Clock_driver_ticks; - -static rtems_isr clockISR(rtems_vector_number vector) { - - Clock_driver_ticks += 1; - -#if CLOCK_DRIVER_USE_FAST_IDLE - do { - rtems_clock_tick(); - } while ( _Thread_Heir == _Thread_Executing && _Thread_Executing->is_idle ); -#else - rtems_clock_tick(); -#endif -} - -/* - * Clock_exit - * - * This routine allows the clock driver to exit by masking the interrupt and - * disabling the clock's counter. - */ -static void Clock_exit(void) -{ - *(uint32_t volatile *) TCNTL = 0; -} - -void _Clock_Initialize( void ) -{ - Clock_driver_ticks = 0; - - set_vector(clockISR, CEC_CORE_TIMER_VECTOR, 1); - - *(uint32_t volatile *) TCNTL = TCNTL_TMPWR | TCNTL_TAUTORLD; - *(uint32_t volatile *) TSCALE = 0; - *(uint32_t volatile *) TPERIOD = CCLK / 1000000 * - rtems_configuration_get_microseconds_per_tick(); - *(uint32_t volatile *) TCNTL = TCNTL_TMPWR | TCNTL_TAUTORLD | TCNTL_TMREN; - - atexit(Clock_exit); -} diff --git a/bsps/bfin/shared/dev/rtc.c b/bsps/bfin/shared/dev/rtc.c deleted file mode 100644 index e3fb48b4bf..0000000000 --- a/bsps/bfin/shared/dev/rtc.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Real Time Clock Driver for Blackfin - */ - -/* - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Prototypes and routines used below - */ -int Leap_years_until_now (int year); - -void Init_RTC(void) -{ - *((uint16_t*)RTC_PREN) = RTC_PREN_PREN; /* Enable Prescaler */ -} - -/* - * Read time from RTEMS' clock manager and set it to RTC - */ -void setRealTimeFromRTEMS (void) -{ - rtems_time_of_day time_buffer; - rtems_status_code status; - - status = rtems_clock_get_tod( &time_buffer ); - if (status == RTEMS_SUCCESSFUL){ - setRealTime(&time_buffer); - } -} - -/* - * Read real time from RTC and set it to RTEMS' clock manager - */ -void setRealTimeToRTEMS (void) -{ - rtems_time_of_day time_buffer; - - getRealTime(&time_buffer); - rtems_clock_set( &time_buffer ); -} - -/* - * Set the RTC time - */ -int setRealTime( - const rtems_time_of_day *tod -) -{ - uint32_t days; - rtems_time_of_day tod_temp; - - tod_temp = *tod; - - days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \ - _TOD_Days_to_date[1][tod_temp.month] + tod_temp.day - 1; - if (tod_temp.month < 3) - days += Leap_years_until_now (tod_temp.year - 1); - else - days += Leap_years_until_now (tod_temp.year); - - *((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)| - (tod_temp.hour << RTC_STAT_HOURS_SHIFT)| - (tod_temp.minute << RTC_STAT_MINUTES_SHIFT)| - tod_temp.second; - - return 0; -} - -/* - * Get the time from the RTC. - */ -void getRealTime( - rtems_time_of_day *tod -) -{ - uint32_t days, rtc_reg; - rtems_time_of_day tod_temp = { 0, 0, 0 }; - int n, Leap_year; - - rtc_reg = *((uint32_t volatile *)RTC_STAT); - - days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1; - - /* finding year */ - tod_temp.year = days/365 + TOD_BASE_YEAR; - if (days%365 > Leap_years_until_now (tod_temp.year - 1)) { - days = (days%365) - Leap_years_until_now (tod_temp.year - 1); - } else { - tod_temp.year--; - days = (days%365) + 365 - Leap_years_until_now (tod_temp.year - 1); - } - - /* finding month and day */ - Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) || - (!(tod_temp.year%400)))?0:1; - for (n=1; n<=12; n++) { - if (days <= _TOD_Days_to_date[Leap_year][n+1]) { - tod_temp.month = n; - tod_temp.day = days - _TOD_Days_to_date[Leap_year][n]; - break; - } - } - - tod_temp.hour = (rtc_reg & RTC_STAT_HOURS_MASK) >> RTC_STAT_HOURS_SHIFT; - tod_temp.minute = (rtc_reg & RTC_STAT_MINUTES_MASK) >> RTC_STAT_MINUTES_SHIFT; - tod_temp.second = (rtc_reg & RTC_STAT_SECONDS_MASK); - tod_temp.ticks = 0; - *tod = tod_temp; -} - -/* - * Return the difference between RTC and RTEMS' clock manager time in minutes. - * If the difference is greater than 1 day, this returns 9999. - */ -int checkRealTime (void) -{ - rtems_time_of_day rtems_tod; - rtems_time_of_day rtc_tod; - uint32_t rtems_time; - uint32_t rtc_time; - - (void) rtems_clock_get_tod( &rtems_tod ); - getRealTime ( &rtc_tod ); - - rtems_time = _TOD_To_seconds( &rtems_tod ); - rtc_time = _TOD_To_seconds( &rtc_tod ); - - return rtems_time - rtc_time; -} - -int Leap_years_until_now (int year) -{ - return ((year/4 - year/100 + year/400) - - ((TOD_BASE_YEAR - 1)/4 - (TOD_BASE_YEAR - 1)/100 + - (TOD_BASE_YEAR - 1)/400)); -} - -rtems_device_driver rtc_initialize( - rtems_device_major_number major, - rtems_device_minor_number minor_arg, - void *arg -) -{ - rtems_status_code status; - - /* - * Register and initialize the primary RTC's - */ - - status = rtems_io_register_name( RTC_DEVICE_NAME, major, 0 ); - if (status != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(status); - } - - Init_RTC(); - - setRealTimeToRTEMS(); - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver rtc_read( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - rtems_libio_rw_args_t *rw = arg; - rtems_time_of_day *tod = (rtems_time_of_day *) rw->buffer; - - rw->offset = 0; - rw->bytes_moved = 0; - - if (rw->count != sizeof( rtems_time_of_day)) { - return RTEMS_INVALID_SIZE; - } - - getRealTime( tod); - - rw->bytes_moved = rw->count; - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver rtc_write( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - int rv = 0; - rtems_libio_rw_args_t *rw = arg; - const rtems_time_of_day *tod = (const rtems_time_of_day *) rw->buffer; - - rw->offset = 0; - rw->bytes_moved = 0; - - if (rw->count != sizeof( rtems_time_of_day)) { - return RTEMS_INVALID_SIZE; - } - - rv = setRealTime( tod); - if (rv != 0) { - return RTEMS_IO_ERROR; - } - - rw->bytes_moved = rw->count; - - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver rtc_open( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver rtc_close( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - return RTEMS_SUCCESSFUL; -} - -rtems_device_driver rtc_control( - rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg -) -{ - return RTEMS_NOT_IMPLEMENTED; -} diff --git a/bsps/bfin/shared/dev/spi.c b/bsps/bfin/shared/dev/spi.c deleted file mode 100644 index e1024e8d10..0000000000 --- a/bsps/bfin/shared/dev/spi.c +++ /dev/null @@ -1,240 +0,0 @@ -/* SPI driver for Blackfin - * - * Copyright (c) 2010 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - - -#ifndef BFIN_REG16 -#define BFIN_REG16(base, offset) \ - (*((uint16_t volatile *) ((uint8_t *)(base) + (offset)))) -#endif - - -static bfin_spi_state_t *bfin_spi; - - -void bfin_spi_isr(int v) { - bfin_spi_state_t *state; - uint16_t r; - - state = bfin_spi; - if (state->len > state->bytes_per_word) { - if (state->wr_ptr) { - if (state->bytes_per_word == 2) - r = *(uint16_t *) state->wr_ptr; - else - r = (uint16_t) *state->wr_ptr; - state->wr_ptr += state->bytes_per_word; - } else - r = state->idle_pattern; - BFIN_REG16(state->base, SPI_TDBR_OFFSET) = r; - } - state->len -= state->bytes_per_word; - if (state->len <= 0) { - /* - The transfers are done, so I don't want to kick off another - transfer or get any more interrupts. Reading the last word from - SPI_SHADOW instead of SPI_RDBR should prevent it from triggering - another transfer, but that doesn't clear the interrupt flag. I - could mask the interrupt in the SIC, but that would preclude ever - using the DMA channel that shares the interrupt independently (and - they might just share it with something more important in some other - member of the Blackfin family). And who knows what problems it - might cause in this code potentially dealing with that still pended - interrupt at the beginning of the next transfer. - - So instead I disable the SPI interface, read the data from RDBR - (thus clearing the interrupt but not triggering another transfer - since the interface is disabled), then re-eanble the interface. - This has the problem that the bf537 tri-states the SPI signals - while the interface is disabled. Either adding pull-ups on at - least the chip select signals, or using GPIOs for them so they're - not controlled by the SPI module, would be correct fixes for that - (really pull-ups/downs should be added to the SPI CLK and MOSI - signals as well to insure they cannot float into some region that - causes input structures to consume excessive power). Or they can - all be left alone, assuming that there's enough capacitance on the - lines to prevent any problems for the short time they're being left - disabled. - - An alternative approach I attempted involved switching TIMOD - between RDBR and TDBR when starting and finishing a transfer, but - I didn't get anywhere with that. In my limited testing TIMOD TDBR - wasn't behaving as I expected it to, but maybe with more - experimentation I'd find some solution there. However I'm out - of time for this project, at least for now. - */ - - BFIN_REG16(state->base, SPI_CTL_OFFSET) &= ~SPI_CTL_SPE; - r = BFIN_REG16(state->base, SPI_RDBR_OFFSET); - BFIN_REG16(state->base, SPI_CTL_OFFSET) |= SPI_CTL_SPE; - rtems_semaphore_release(state->sem); - } else - r = BFIN_REG16(state->base, SPI_RDBR_OFFSET); - - if (state->rd_ptr) { - if (state->bytes_per_word == 2) - *(uint16_t *) state->rd_ptr = r; - else - *state->rd_ptr = (uint8_t) r; - state->rd_ptr += state->bytes_per_word; - } -} - -static rtems_status_code setTFRMode(rtems_libi2c_bus_t *bus, - const rtems_libi2c_tfr_mode_t *tfrMode) { - rtems_status_code result; - bfin_spi_state_t *state; - uint32_t divisor; - uint16_t ctrl; - - result = RTEMS_SUCCESSFUL; - state = &((bfin_spi_bus_t *) bus)->p; - - if (result == RTEMS_SUCCESSFUL) { - if (tfrMode->bits_per_char != 8 && - tfrMode->bits_per_char != 16) - result = RTEMS_INVALID_NUMBER; - if (tfrMode->baudrate <= 0) - result = RTEMS_INVALID_NUMBER; - } - if (result == RTEMS_SUCCESSFUL) { - divisor = (SCLK / 2 + tfrMode->baudrate - 1) / - tfrMode->baudrate; - if (divisor < 2) - divisor = 2; - else if (divisor > 65535) - result = RTEMS_INVALID_NUMBER; - } - if (result == RTEMS_SUCCESSFUL) { - state->idle_pattern = (uint16_t) tfrMode->idle_char; - state->bytes_per_word = (tfrMode->bits_per_char > 8) ? 2 : 1; - BFIN_REG16(state->base, SPI_BAUD_OFFSET) = divisor; - ctrl = BFIN_REG16(state->base, SPI_CTL_OFFSET); - if (tfrMode->lsb_first) - ctrl |= SPI_CTL_LSBF; - else - ctrl &= ~SPI_CTL_LSBF; - if (tfrMode->bits_per_char > 8) - ctrl |= SPI_CTL_SIZE; - else - ctrl &= ~SPI_CTL_SIZE; - if (tfrMode->clock_inv) - ctrl |= SPI_CTL_CPOL; - else - ctrl &= ~SPI_CTL_CPOL; - if (tfrMode->clock_phs) - ctrl |= SPI_CTL_CPHA; - else - ctrl &= ~SPI_CTL_CPHA; - BFIN_REG16(state->base, SPI_CTL_OFFSET) = ctrl; - } - - return result; -} - -static int readWrite(rtems_libi2c_bus_t *bus, uint8_t *rdBuf, - const uint8_t *wrBuf, int len) { - rtems_status_code result; - bfin_spi_state_t *state; - uint16_t r; - - result = RTEMS_SUCCESSFUL; - state = &((bfin_spi_bus_t *) bus)->p; - - if (len) { - state->rd_ptr = rdBuf; - state->wr_ptr = wrBuf; - state->len = len; - if (state->wr_ptr) { - if (state->bytes_per_word == 2) - r = *(uint16_t *) state->wr_ptr; - else - r = (uint16_t) *state->wr_ptr; - state->wr_ptr += state->bytes_per_word; - } else - r = state->idle_pattern; - BFIN_REG16(state->base, SPI_TDBR_OFFSET) = r; - BFIN_REG16(state->base, SPI_RDBR_OFFSET); /* trigger */ - /* wait until done */ - do { - result = rtems_semaphore_obtain(state->sem, RTEMS_WAIT, 100); - } while (result == RTEMS_SUCCESSFUL && state->len > 0); - } - - return (result == RTEMS_SUCCESSFUL) ? len : -result; -} - - -rtems_status_code bfin_spi_init(rtems_libi2c_bus_t *bus) { - rtems_status_code result; - bfin_spi_state_t *state; - - state = &((bfin_spi_bus_t *) bus)->p; - - BFIN_REG16(state->base, SPI_CTL_OFFSET) = SPI_CTL_SPE | - SPI_CTL_MSTR | - SPI_CTL_CPHA | - SPI_CTL_TIMOD_RDBR; - - result = rtems_semaphore_create(rtems_build_name('s','p','i','s'), - 0, - RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE, - 0, - &state->sem); - if (result == RTEMS_SUCCESSFUL) - bfin_spi = state; /* for isr */ - - return result; -} - -rtems_status_code bfin_spi_send_start(rtems_libi2c_bus_t *bus) { - - return RTEMS_SUCCESSFUL; -} - -int bfin_spi_read_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len) { - - return readWrite(bus, buf, NULL, len); -} - -int bfin_spi_write_bytes(rtems_libi2c_bus_t *bus, unsigned char *buf, int len) { - - return readWrite(bus, NULL, buf, len); -} - -int bfin_spi_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) { - int result; - - result = -RTEMS_NOT_DEFINED; - switch(cmd) { - case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: - result = -setTFRMode(bus, (const rtems_libi2c_tfr_mode_t *) arg); - break; - case RTEMS_LIBI2C_IOCTL_READ_WRITE: - result = readWrite(bus, - ((rtems_libi2c_read_write_t *) arg)->rd_buf, - ((rtems_libi2c_read_write_t *) arg)->wr_buf, - ((rtems_libi2c_read_write_t *) arg)->byte_cnt); - break; - default: - break; - } - - return result; -} - diff --git a/bsps/bfin/shared/dev/sport.c b/bsps/bfin/shared/dev/sport.c deleted file mode 100644 index 6ed481b593..0000000000 --- a/bsps/bfin/shared/dev/sport.c +++ /dev/null @@ -1,2 +0,0 @@ -/* placeholder */ - diff --git a/bsps/bfin/shared/dev/timer.c b/bsps/bfin/shared/dev/timer.c deleted file mode 100644 index 02540fe2ce..0000000000 --- a/bsps/bfin/shared/dev/timer.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * @brief Timer for Blackfin - * - * This file manages the benchmark timer used by the RTEMS Timing Test - * Suite. Each measured time period is demarcated by calls to - * benchmark_timer_initialize() and benchmark_timer_read(). - * benchmark_timer_read() usually returns the number of microseconds - * since benchmark_timer_initialize() exitted. - */ - -/* - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include - -uint32_t Timer_interrupts; -bool benchmark_timer_find_average_overhead; - -/* - * benchmark_timer_initialize - * - * Blackfin processor has a counter for clock cycles. - */ -void benchmark_timer_initialize( void ) -{ - - /*reset counters*/ - __asm__ ("R2 = 0;"); - __asm__ ("CYCLES = R2;"); - __asm__ ("CYCLES2 = R2;"); - /*start counters*/ - __asm__ ("R2 = SYSCFG;"); - __asm__ ("BITSET(R2,1);"); - __asm__ ("SYSCFG = R2"); - -} - -/* - * The following controls the behavior of benchmark_timer_read(). - * - * AVG_OVEREHAD is the overhead for starting and stopping the timer. It - * is usually deducted from the number returned. - * - * LEAST_VALID is the lowest number this routine should trust. Numbers - * below this are "noise" and zero is returned. - */ - -#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ - /* (Y countdowns) to start/stop the timer. */ - /* This value is in microseconds. */ -#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ - -benchmark_timer_t benchmark_timer_read( void ) -{ - uint32_t clicks; - uint32_t total; - register uint32_t cycles __asm__ ("R2"); - - /* stop counter */ - __asm__ ("R2 = SYSCFG;"); - __asm__ ("BITCLR(R2,1);"); - __asm__ ("SYSCFG = R2;"); - __asm__ ("R2 = CYCLES;"); - - - clicks = cycles; /* Clock cycles */ - - /* converting to microseconds */ - total = clicks / (CCLK/1000000); - - if ( benchmark_timer_find_average_overhead == 1 ) - return total; /* in XXX microsecond units */ - else { - if ( total < LEAST_VALID ) - return 0; /* below timer resolution */ - /* - * Somehow convert total into microseconds - */ - return (total - AVG_OVERHEAD); - } -} - -void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) -{ - benchmark_timer_find_average_overhead = find_flag; -} diff --git a/bsps/bfin/shared/dev/twi.c b/bsps/bfin/shared/dev/twi.c deleted file mode 100644 index 0d6e6ca0b1..0000000000 --- a/bsps/bfin/shared/dev/twi.c +++ /dev/null @@ -1,253 +0,0 @@ -/* this is not much more than a shell; it does not do anything useful yet */ - -/* TWI (I2C) driver for Blackfin - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include - -#include -#include - - -#ifndef N_BFIN_TWI -#define N_BFIN_TWI 1 -#endif - -#define BFIN_REG16(base, offset) \ - (*((uint16_t volatile *) ((char *)(base) + (offset)))) - - -static struct { - void *base; - rtems_id irqSem; - rtems_id mutex; - bfin_twi_callback_t callback; - void *callbackArg; - bfin_twi_request_t volatile *req; - uint8_t volatile *dataPtr; - int volatile count; - bool volatile masterActive; - rtems_status_code volatile masterResult; - bool volatile slaveActive; -} twi[N_BFIN_TWI]; - - -rtems_status_code bfin_twi_init(int channel, bfin_twi_config_t *config) { - rtems_status_code result; - void *base; - - if (channel < 0 || channel >= N_BFIN_TWI) - return RTEMS_INVALID_NUMBER; - - base = config->base; - twi[channel].base = base; - - result = rtems_semaphore_create(rtems_build_name('t','w','i','s'), - 0, - RTEMS_FIFO | - RTEMS_SIMPLE_BINARY_SEMAPHORE | - RTEMS_NO_INHERIT_PRIORITY | - RTEMS_NO_PRIORITY_CEILING | - RTEMS_LOCAL, - 0, - &twi[channel].irqSem); - result = rtems_semaphore_create(rtems_build_name('t','w','i','m'), - 1, - RTEMS_PRIORITY | - RTEMS_SIMPLE_BINARY_SEMAPHORE | - RTEMS_INHERIT_PRIORITY | - RTEMS_NO_PRIORITY_CEILING | - RTEMS_LOCAL, - 0, - &twi[channel].mutex); - BFIN_REG16(base, TWI_CONTROL_OFFSET) = - (uint16_t) (((config->sclk +9999999) / 10000000) << - TWI_CONTROL_PRESCALE_SHIFT) | - TWI_CONTROL_TWI_ENA; - BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ? - ((8 << TWI_CLKDIV_CLKHI_SHIFT) | - (17 << TWI_CLKDIV_CLKLOW_SHIFT)) : - ((33 << TWI_CLKDIV_CLKHI_SHIFT) | - (67 << TWI_CLKDIV_CLKLOW_SHIFT)); - BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; - BFIN_REG16(base, TWI_MASTER_CTL_OFFSET) = config->fast ? - TWI_MASTER_CTL_FAST : - 0; - BFIN_REG16(base, TWI_SLAVE_ADDR_OFFSET) = (uint16_t) config->slave_address << - TWI_SLAVE_ADDR_SADDR_SHIFT; - BFIN_REG16(base, TWI_MASTER_STAT_OFFSET) = TWI_MASTER_STAT_BUFWRERR | - TWI_MASTER_STAT_BUFRDERR | - TWI_MASTER_STAT_DNAK | - TWI_MASTER_STAT_ANAK | - TWI_MASTER_STAT_LOSTARB; - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = TWI_FIFO_CTL_XMTFLUSH | - TWI_FIFO_CTL_RCVFLUSH; - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = 0; - BFIN_REG16(base, TWI_INT_STAT_OFFSET) = TWI_INT_STAT_RCVSERV | - TWI_INT_STAT_XMTSERV | - TWI_INT_STAT_MERR | - TWI_INT_STAT_MCOMP | - TWI_INT_STAT_SOVF | - TWI_INT_STAT_SERR | - TWI_INT_STAT_SCOMP | - TWI_INT_STAT_SINIT; - BFIN_REG16(base, TWI_INT_MASK_OFFSET) = TWI_INT_MASK_RCVSERVM | - TWI_INT_MASK_XMTSERVM; - - return result; -} - -rtems_status_code bfin_twi_register_callback(int channel, - bfin_twi_callback_t callback, - void *arg) { - void *base; - int level; - - if (channel < 0 || channel >= N_BFIN_TWI) - return RTEMS_INVALID_NUMBER; - - base = twi[channel].base; - if (callback == NULL) - BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = 0; - rtems_interrupt_disable(level); - twi[channel].callback = callback; - twi[channel].callbackArg = arg; - rtems_interrupt_enable(level); - if (callback != NULL) - BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = TWI_SLAVE_CTL_GEN | - TWI_SLAVE_CTL_SEN; - - return RTEMS_SUCCESSFUL; -} - -void bfin_twi_isr(int source) { - void *base; - int i; - uint16_t r; - uint16_t stat; - - for (i = 0; i < N_BFIN_TWI; i++) { - base = twi[i].base; - if (base) { - stat = BFIN_REG16(base, TWI_INT_STAT_OFFSET); - if (stat) { - BFIN_REG16(base, TWI_INT_STAT_OFFSET) = stat; - if ((stat & TWI_INT_STAT_SINIT) && !twi[i].slaveActive) { - twi[i].slaveActive = true; - r = BFIN_REG16(base, TWI_FIFO_CTL_OFFSET); - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r | TWI_FIFO_CTL_XMTFLUSH; - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r; - r = BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET); - BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = r | TWI_SLAVE_CTL_STDVAL; - } - if (twi[i].slaveActive) { - - - if (stat & (TWI_INT_STAT_SCOMP | TWI_INT_STAT_SERR)) { - - - r = BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET); - BFIN_REG16(base, TWI_SLAVE_CTL_OFFSET) = r & ~TWI_SLAVE_CTL_STDVAL; - twi[i].slaveActive = false; - - - } - } - if (twi[i].masterActive && !twi[i].slaveActive) { - - - if (stat & (TWI_INT_STAT_MCOMP | TWI_INT_STAT_MERR)) { - if (!(stat & TWI_INT_STAT_MERR)) { - - - rtems_semaphore_release(twi[i].irqSem); - - - } else - rtems_semaphore_release(twi[i].irqSem); - } - } - } - } - } -} - -rtems_status_code bfin_twi_request(int channel, uint8_t address, - bfin_twi_request_t *request, - rtems_interval timeout) { - rtems_status_code result; - void *base; - rtems_interrupt_level level; - uint16_t r; - uint16_t masterMode; - - if (channel < 0 || channel >= N_BFIN_TWI) - return RTEMS_INVALID_NUMBER; - result = rtems_semaphore_obtain(twi[channel].mutex, - RTEMS_WAIT, RTEMS_NO_TIMEOUT); - if (result == RTEMS_SUCCESSFUL) { - base = twi[channel].base; - twi[channel].req = request; - - if (request->write) { - twi[channel].dataPtr = request->data; - twi[channel].count = request->count; - } else - twi[channel].count = 0; - - BFIN_REG16(base, TWI_MASTER_ADDR_OFFSET) = (uint16_t) address << - TWI_MASTER_ADDR_MADDR_SHIFT; - masterMode = BFIN_REG16(base, TWI_MASTER_CTL_OFFSET); - masterMode |= (request->count << TWI_MASTER_CTL_DCNT_SHIFT); - if (request->next) - masterMode |= TWI_MASTER_CTL_RSTART; - if (!request->write) - masterMode |= TWI_MASTER_CTL_MDIR; - masterMode |= TWI_MASTER_CTL_MEN; - rtems_interrupt_disable(level); - if (!twi[channel].slaveActive) { - r = BFIN_REG16(base, TWI_FIFO_CTL_OFFSET); - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r | TWI_FIFO_CTL_XMTFLUSH; - BFIN_REG16(base, TWI_FIFO_CTL_OFFSET) = r; - if (request->write) { - while (twi[channel].count && - (BFIN_REG16(base, TWI_FIFO_STAT_OFFSET) & - TWI_FIFO_STAT_XMTSTAT_MASK) != - TWI_FIFO_STAT_XMTSTAT_FULL) { - BFIN_REG16(base, TWI_XMT_DATA8_OFFSET) = - (uint16_t) *twi[channel].dataPtr++; - twi[channel].count--; - } - } - twi[channel].masterActive = true; - BFIN_REG16(base, TWI_MASTER_CTL_OFFSET) = masterMode; - } else { - twi[channel].masterActive = false; - twi[channel].masterResult = -1; /* BISON (code should be equiv to lost arbitration) */ - } - rtems_interrupt_enable(level); - while (result == RTEMS_SUCCESSFUL && twi[channel].masterActive) - result = rtems_semaphore_obtain(twi[channel].irqSem, - RTEMS_WAIT, timeout); - if (result == RTEMS_SUCCESSFUL) - result = twi[channel].masterResult; - else { - /* BISON abort */ - - - - } - rtems_semaphore_release(twi[channel].mutex); - } - return result; -} - diff --git a/bsps/bfin/shared/dev/uart.c b/bsps/bfin/shared/dev/uart.c deleted file mode 100644 index 18a522e121..0000000000 --- a/bsps/bfin/shared/dev/uart.c +++ /dev/null @@ -1,528 +0,0 @@ -/* UART driver for Blackfin - */ - -/* - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -/* flags */ -#define BFIN_UART_XMIT_BUSY 0x01 - -static bfin_uart_config_t *uartsConfig; - -static int pollRead(int minor) -{ - int c; - uint32_t base; - - base = uartsConfig->channels[minor].uart_baseAddress; - - /* check to see if driver is using interrupts so this call will be - harmless (though non-functional) in case some debug code tries to - use it */ - if (!uartsConfig->channels[minor].uart_useInterrupts && - *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR) - c = *((uint16_t volatile *) (base + UART_RBR_OFFSET)); - else - c = -1; - - return c; -} - -char bfin_uart_poll_read(rtems_device_minor_number minor) -{ - int c; - - do { - c = pollRead(minor); - } while (c == -1); - - return c; -} - -void bfin_uart_poll_write(int minor, char c) -{ - uint32_t base; - - base = uartsConfig->channels[minor].uart_baseAddress; - - while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE)) - ; - *(uint16_t volatile *) (base + UART_THR_OFFSET) = c; -} - -/* - * Console Termios Support Entry Points - * - */ - -static ssize_t pollWrite(int minor, const char *buf, size_t len) -{ - size_t count; - for ( count = 0; count < len; count++ ) - bfin_uart_poll_write(minor, *buf++); - - return count; -} - -/** - * Routine to initialize the hardware. It initialize the DMA, - * interrupt if required. - * @param channel channel information - */ -static void initializeHardware(bfin_uart_channel_t *channel) -{ - uint16_t divisor = 0; - uint32_t base = 0; - uint32_t tx_dma_base = 0; - - if ( NULL == channel ) { - return; - } - - base = channel->uart_baseAddress; - tx_dma_base = channel->uart_txDmaBaseAddress; - /** - * RX based DMA and interrupt is not supported yet - * uint32_t tx_dma_base = 0; - * - * rx_dma_base = channel->uart_rxDmaBaseAddress; - */ - - - *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0; - - if ( 0 != channel->uart_baud) { - divisor = (uint16_t) (uartsConfig->freq / - (channel->uart_baud * 16)); - } else { - divisor = (uint16_t) (uartsConfig->freq / (9600 * 16)); - } - - *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB; - *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); - *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); - - *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8; - - *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN; - - /** - * To clear previous status - * divisor is a temp variable here - */ - divisor = *(uint16_t volatile *) (base + UART_LSR_OFFSET); - divisor = *(uint16_t volatile *) (base + UART_RBR_OFFSET); - divisor = *(uint16_t volatile *) (base + UART_IIR_OFFSET); - - if ( channel->uart_useDma ) { - *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0; - *(uint16_t volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN - | DMA_CONFIG_SYNC ; - *(uint16_t volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |= - DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; - - } else { - /** - * We use polling or interrupts only sending one char at a time :( - */ - } -} - - -/** - * Set the UART attributes. - * @param minor - * @param termios - * @return - */ -static int setAttributes(int minor, const struct termios *termios) -{ - uint32_t base; - int baud; - uint16_t divisor; - uint16_t lcr; - - base = uartsConfig->channels[minor].uart_baseAddress; - switch (termios->c_ospeed) { - case B0: baud = 0; break; - case B50: baud = 50; break; - case B75: baud = 75; break; - case B110: baud = 110; break; - case B134: baud = 134; break; - case B150: baud = 150; break; - case B200: baud = 200; break; - case B300: baud = 300; break; - case B600: baud = 600; break; - case B1200: baud = 1200; break; - case B1800: baud = 1800; break; - case B2400: baud = 2400; break; - case B4800: baud = 4800; break; - case B9600: baud = 9600; break; - case B19200: baud = 19200; break; - case B38400: baud = 38400; break; - case B57600: baud = 57600; break; - case B115200: baud = 115200; break; - case B230400: baud = 230400; break; - case B460800: baud = 460800; break; - default: baud = -1; break; - } - if (baud > 0 && uartsConfig->channels[minor].uart_baud) - baud = uartsConfig->channels[minor].uart_baud; - switch (termios->c_cflag & CSIZE) { - case CS5: lcr = UART_LCR_WLS_5; break; - case CS6: lcr = UART_LCR_WLS_6; break; - case CS7: lcr = UART_LCR_WLS_7; break; - default: - case CS8: lcr = UART_LCR_WLS_8; break; - } - switch (termios->c_cflag & (PARENB | PARODD)) { - case PARENB: - lcr |= UART_LCR_PEN | UART_LCR_EPS; - break; - case PARENB | PARODD: - lcr |= UART_LCR_PEN; - break; - default: - break; - } - if (termios->c_cflag & CSTOPB) - lcr |= UART_LCR_STB; - - if (baud > 0) { - divisor = (uint16_t) (uartsConfig->freq / (baud * 16)); - *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr | UART_LCR_DLAB; - *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff); - *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff); - } - *(uint16_t volatile *) (base + UART_LCR_OFFSET) = lcr; - - return 0; -} - -/** - * Interrupt based uart tx routine. The routine writes one character at a time. - * - * @param minor Minor number to indicate uart number - * @param buf Character buffer which stores characters to be transmitted. - * @param len Length of buffer to be transmitted. - * @return - */ -static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) -{ - uint32_t base = 0; - bfin_uart_channel_t* channel = NULL; - - /** - * Sanity Check - */ - if ( - NULL == buf || NULL == channel || NULL == uartsConfig - || minor < 0 || 0 == len - ) { - return 0; - } - - channel = &(uartsConfig->channels[minor]); - - if ( NULL == channel || channel->flags & BFIN_UART_XMIT_BUSY ) { - return 0; - } - - base = channel->uart_baseAddress; - - channel->flags |= BFIN_UART_XMIT_BUSY; - channel->length = 1; - *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf; - *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; - - return 0; -} - -/** - * This function implements RX ISR - */ -void bfinUart_rxIsr(void *_arg) -{ - /** - * TODO: UART RX ISR implementation. - */ -} - -/** - * This function implements TX ISR. The function gets called when the TX FIFO is - * empty. It clears the interrupt and dequeues the character. It only tx one - * character at a time. - * - * TODO: error handling. - * @param _arg gets the channel information. - */ -void bfinUart_txIsr(void *_arg) -{ - bfin_uart_channel_t* channel = NULL; - uint32_t base = 0; - - /** - * Sanity check - */ - if (NULL == _arg) { - /** It should never be NULL */ - return; - } - - channel = (bfin_uart_channel_t *) _arg; - - base = channel->uart_baseAddress; - - *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI; - channel->flags &= ~BFIN_UART_XMIT_BUSY; - - rtems_termios_dequeue_characters(channel->termios, channel->length); -} - -/** - * interrupt based DMA write Routine. It configure the DMA to write len bytes. - * The DMA supports 64K data only. - * - * @param minor Identification number of the UART. - * @param buf Character buffer pointer - * @param len length of data items to be written - * @return data already written - */ -static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) -{ - uint32_t base = 0; - bfin_uart_channel_t* channel = NULL; - uint32_t tx_dma_base = 0; - - /** - * Sanity Check - */ - if ( NULL == buf || 0 > minor || NULL == uartsConfig || 0 == len ) { - return 0; - } - - channel = &(uartsConfig->channels[minor]); - - /** - * Sanity Check and check for transmit busy. - */ - if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) { - return 0; - } - - base = channel->uart_baseAddress; - tx_dma_base = channel->uart_txDmaBaseAddress; - - channel->flags |= BFIN_UART_XMIT_BUSY; - channel->length = len; - - *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN; - *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf; - *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length; - *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1; - *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN; - *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI; - - return 0; -} - -/** - * RX DMA ISR. - * The polling route is used for receiving the characters. This is a place - * holder for future implementation. - * @param _arg - */ -void bfinUart_rxDmaIsr(void *_arg) -{ -/** - * TODO: Implementation of RX DMA - */ -} - -/** - * This function implements TX dma ISR. It clears the IRQ and dequeues a char - * The channel argument will have the base address. Since there are two uart - * and both the uarts can use the same tx dma isr. - * - * TODO: 1. Error checking 2. sending correct length ie after looking at the - * number of elements the uart transmitted. - * - * @param _arg argument passed to the interrupt handler. It contains the - * channel argument. - */ -void bfinUart_txDmaIsr(void *_arg) -{ - bfin_uart_channel_t* channel = NULL; - uint32_t tx_dma_base = 0; - - /** - * Sanity check - */ - if (NULL == _arg) { - /** It should never be NULL */ - return; - } - - channel = (bfin_uart_channel_t *) _arg; - - tx_dma_base = channel->uart_txDmaBaseAddress; - - if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) - & DMA_IRQ_STATUS_DMA_DONE)) { - - *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET) - |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR; - channel->flags &= ~BFIN_UART_XMIT_BUSY; - rtems_termios_dequeue_characters(channel->termios, channel->length); - } else { - /* UART DMA did not generate interrupt. - * This routine must not be called. - */ - } -} - -/** - * Function called during exit - */ -static void uart_exit(void) -{ - /** - * TODO: Flushing of quques - */ -} - -/** - * Opens the device in different modes. The supported modes are - * 1. Polling - * 2. Interrupt - * 3. DMA - * At exit the uart_Exit function will be called to flush the device. - * - * @param major Major number of the device - * @param minor Minor number of the device - * @param arg - * @return - */ -rtems_device_driver bfin_uart_open(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg) { - rtems_status_code sc = RTEMS_NOT_DEFINED; - rtems_libio_open_close_args_t *args = NULL; - - /** - * Callback function for polling - */ - static const rtems_termios_callbacks pollCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - pollRead, /* pollRead */ - pollWrite, /* write */ - setAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_POLLED /* outputUsesInterrupts */ - }; - - /** - * Callback function for interrupt based transfers without DMA. - * We use interrupts for writing only. For reading we use polling. - */ - static const rtems_termios_callbacks interruptCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - pollRead, /* pollRead */ - uart_interruptWrite, /* write */ - setAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ - }; - - /** - * Callback function for interrupt based DMA transfers. - * We use interrupts for writing only. For reading we use polling. - */ - static const rtems_termios_callbacks interruptDmaCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - NULL, /* pollRead */ - uart_DmaWrite, /* write */ - setAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_IRQ_DRIVEN /* outputUsesInterrupts */ - }; - - if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) { - return RTEMS_INVALID_NUMBER; - } - - /** - * Opens device for handling uart send request either by - * 1. interrupt with DMA - * 2. interrupt based - * 3. Polling - */ - if ( uartsConfig->channels[minor].uart_useDma ) { - sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks); - } else { - sc = rtems_termios_open(major, minor, arg, - uartsConfig->channels[minor].uart_useInterrupts ? - &interruptCallbacks : &pollCallbacks); - } - - args = arg; - uartsConfig->channels[minor].termios = args->iop->data1; - - atexit(uart_exit); - - return sc; -} - -/** -* Uart initialization function. -* @param major major number of the device -* @param config configuration parameters -* @return rtems status code -*/ -rtems_status_code bfin_uart_initialize( - rtems_device_major_number major, - bfin_uart_config_t *config -) -{ - rtems_status_code sc = RTEMS_NOT_DEFINED; - int i = 0; - - rtems_termios_initialize(); - - /* - * Register Device Names - */ - uartsConfig = config; - for (i = 0; i < config->num_channels; i++) { - config->channels[i].termios = NULL; - config->channels[i].flags = 0; - initializeHardware(&(config->channels[i])); - sc = rtems_io_register_name(config->channels[i].name, major, i); - if (RTEMS_SUCCESSFUL != sc) { - return sc; - } - } - - return sc; -} diff --git a/bsps/bfin/shared/doxygen.h b/bsps/bfin/shared/doxygen.h deleted file mode 100644 index 4ada8402e9..0000000000 --- a/bsps/bfin/shared/doxygen.h +++ /dev/null @@ -1,15 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSImplDoxygen - * - * @brief This header file defines bfin-specific groups. - */ - -/** - * @defgroup RTEMSBSPsBfin Blackfin - * - * @ingroup RTEMSBSPs - * - * @brief Blackfin Board Support Packages. - */ diff --git a/bsps/bfin/shared/interrupt.c b/bsps/bfin/shared/interrupt.c deleted file mode 100644 index 7fe1eb19f7..0000000000 --- a/bsps/bfin/shared/interrupt.c +++ /dev/null @@ -1,196 +0,0 @@ -/* Support for Blackfin interrupt controller - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include -#include - -#include -#include -#include -#include -#include - - -static struct { - uint32_t mask; - bfin_isr_t *head; -} vectors[CEC_INTERRUPT_COUNT]; - -static uint32_t globalMask; - - -static rtems_isr interruptHandler(rtems_vector_number vector) { - bfin_isr_t *isr; - uint32_t sourceMask; - - vector -= CEC_INTERRUPT_BASE_VECTOR; - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - isr = vectors[vector].head; - sourceMask = *(uint32_t volatile *) SIC_ISR & - *(uint32_t volatile *) SIC_IMASK; - while (isr) { - if (sourceMask & isr->mask) { - isr->isr(isr->source); - sourceMask = *(uint32_t volatile *) SIC_ISR & - *(uint32_t volatile *) SIC_IMASK; - } - isr = isr->next; - } - } -} - -void bfin_interrupt_init(void) { - int source; - int vector; - uint32_t r; - int i; - int j; - - globalMask = ~(uint32_t) 0; - *(uint32_t volatile *) SIC_IMASK = 0; - memset(vectors, 0, sizeof(vectors)); - /* build mask showing what SIC sources drive each CEC vector */ - source = 0; - for (i = 0; i < SIC_IAR_COUNT; i++) { - r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH); - for (j = 0; j < 8; j++) { - vector = r & 0x0f; - if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) { - if (vectors[vector].mask == 0) - /* install our local handler */ - set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1); - vectors[vector].mask |= (1 << source); - } - r >>= 4; - source++; - } - } -} - -/* modify SIC_IMASK based on ISR list for a particular CEC vector */ -static void setMask(int vector) { - bfin_isr_t *isr; - uint32_t mask; - uint32_t r; - - mask = 0; - isr = vectors[vector].head; - while (isr) { - mask |= isr->mask; - isr = isr->next; - } - r = *(uint32_t volatile *) SIC_IMASK; - r &= ~vectors[vector].mask; - r |= mask; - r &= globalMask; - *(uint32_t volatile *) SIC_IMASK = r; -} - -/* add an ISR to the list for whichever vector it belongs to */ -void bfin_interrupt_register(bfin_isr_t *isr) { - bfin_isr_t *walk; - rtems_interrupt_level isrLevel; - - /* find the appropriate vector */ - for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++) - if (vectors[isr->vector].mask & (1 << isr->source)) - break; - if (isr->vector < CEC_INTERRUPT_COUNT) { - isr->next = NULL; - isr->mask = 0; - rtems_interrupt_disable(isrLevel); - /* find the current end of the list */ - walk = vectors[isr->vector].head; - while (walk && walk->next) - walk = walk->next; - /* append new isr to list */ - if (walk) - walk->next = isr; - else - vectors[isr->vector].head = isr; - rtems_interrupt_enable(isrLevel); - } else - /* we failed, but make vector a legal value so other calls into - this module with this isr descriptor won't do anything bad */ - isr->vector = 0; -} - -void bfin_interrupt_unregister(bfin_isr_t *isr) { - bfin_isr_t *walk, *prev; - rtems_interrupt_level isrLevel; - - rtems_interrupt_disable(isrLevel); - walk = vectors[isr->vector].head; - prev = NULL; - /* find this isr in our list */ - while (walk && walk != isr) { - prev = walk; - walk = walk->next; - } - if (walk) { - /* if found, remove it */ - if (prev) - prev->next = walk->next; - else - vectors[isr->vector].head = walk->next; - /* fix up SIC_IMASK if necessary */ - setMask(isr->vector); - } - rtems_interrupt_enable(isrLevel); -} - -void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) { - rtems_interrupt_level isrLevel; - - rtems_interrupt_disable(isrLevel); - isr->mask = enable ? (1 << isr->source) : 0; - setMask(isr->vector); - rtems_interrupt_enable(isrLevel); -} - -void bfin_interrupt_enable_all(int source, bool enable) { - rtems_interrupt_level isrLevel; - int vector; - bfin_isr_t *walk; - - for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) - if (vectors[vector].mask & (1 << source)) - break; - if (vector < CEC_INTERRUPT_COUNT) { - rtems_interrupt_disable(isrLevel); - walk = vectors[vector].head; - while (walk) { - walk->mask = enable ? (1 << source) : 0; - walk = walk->next; - } - setMask(vector); - rtems_interrupt_enable(isrLevel); - } -} - -void bfin_interrupt_enable_global(int source, bool enable) { - int vector; - rtems_interrupt_level isrLevel; - - for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++) - if (vectors[vector].mask & (1 << source)) - break; - if (vector < CEC_INTERRUPT_COUNT) { - rtems_interrupt_disable(isrLevel); - if (enable) - globalMask |= 1 << source; - else - globalMask &= ~(1 << source); - setMask(vector); - rtems_interrupt_enable(isrLevel); - } -} - diff --git a/bsps/bfin/shared/mmu.c b/bsps/bfin/shared/mmu.c deleted file mode 100644 index bf3311b5b4..0000000000 --- a/bsps/bfin/shared/mmu.c +++ /dev/null @@ -1,44 +0,0 @@ -/* Blackfin MMU Support - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - - -#include - -#include -#include - -/* NOTE: see notes in mmu.h */ - -void bfin_mmu_init(bfin_mmu_config_t *config) { - intptr_t addr; - intptr_t data; - int i; - - addr = (intptr_t) ICPLB_ADDR0; - data = (intptr_t) ICPLB_DATA0; - for (i = 0; i < sizeof(config->instruction) / sizeof(config->instruction[0]); - i++) { - *(uint32_t volatile *) addr = (uint32_t) config->instruction[i].address; - addr += ICPLB_ADDR_PITCH; - *(uint32_t volatile *) data = config->instruction[i].flags; - data += ICPLB_DATA_PITCH; - } - *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_ENICPLB; - addr = (intptr_t) DCPLB_ADDR0; - data = (intptr_t) DCPLB_DATA0; - for (i = 0; i < sizeof(config->data) / sizeof(config->data[0]); i++) { - *(uint32_t volatile *) addr = (uint32_t) config->data[i].address; - addr += DCPLB_ADDR_PITCH; - *(uint32_t volatile *) data = config->data[i].flags; - data += DCPLB_DATA_PITCH; - } - *(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_ENDCPLB; -} - diff --git a/bsps/bfin/shared/start/start.S b/bsps/bfin/shared/start/start.S deleted file mode 100644 index acf742cea2..0000000000 --- a/bsps/bfin/shared/start/start.S +++ /dev/null @@ -1,95 +0,0 @@ - -#include - -#include -#include - -#ifndef LO -#define LO(con32) ((con32) & 0xFFFF) -#endif -#ifndef HI -#define HI(con32) (((con32) >> 16) & 0xFFFF) -#endif - -#if (BFIN_ON_SKYEYE) - .section .init -#else - .section .l1code -#endif - .align 4 - - .global __start -__start: - - /* Start by setting up a stack */ - sp.h = __ISR_Stack_area_end; - sp.l = __ISR_Stack_area_end; - - /* Maybe we should zero the memory in the .bss section. */ - - /* This changes to the supervisor mode */ - p0.l = START; - p0.h = START; - p1.l = LO(EVT15); - p1.h = HI(EVT15); - - [P1] = P0; - - P0.h = HI(IMASK); - P0.l = LO(IMASK); - R0 = [P0]; - /* R1.l = EVT_IVG15 & 0xFFFF; */ - R1.l = 0x8000; - - R0 = R0 | R1; - - [P0] = R0; - - RAISE 15; - - P0.l = WAIT; - P0.h = WAIT; - - RETI = P0; - RTI; - - /* endless loop to wait */ - WAIT: - jump WAIT; - - START: - [--SP] = RETI; - - p0.h = _bss_start; - p0.l = _bss_start; - p1.h = _end; - p1.l = _end; - r0 = p0; - r1 = p1; - r1 = r1 - r0; - p1 = r1; - r0 = 0; - - /* Set _bss_start until _end to zero */ - lsetup(loop1,loop2) LC0 = p1; - loop1: b[p0] = r0; - loop2: p0 +=1; - - /* call boot_card( 0, 0 ) */ - r0 = 0; - r1 = 0; - p0.l = _boot_card; - p0.h = _boot_card; - - call (p0); - - HLT - p0.l = _exit; - p0.h = _exit; - P3 = P4; - jump (p0) /* Should not return. */ - -.global _bfin_null_isr -_bfin_null_isr: - rti; - diff --git a/cpukit/libdl/rtl-mdreloc-bfin.c b/cpukit/libdl/rtl-mdreloc-bfin.c deleted file mode 100644 index cf3f3f88c0..0000000000 --- a/cpukit/libdl/rtl-mdreloc-bfin.c +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/** - * @file - * - * @ingroup - * - * @brief - */ - -/* - * Copyright (C) 2014 Chris Johns . - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -#include -#include -#include -#include "rtl-elf.h" -#include "rtl-error.h" -#include -#include "rtl-unwind.h" -#include "rtl-unwind-dw2.h" - -uint32_t -rtems_rtl_elf_section_flags (const rtems_rtl_obj_t* obj, - const Elf_Shdr* shdr) -{ - return 0; -} - -uint32_t -rtems_rtl_elf_arch_parse_section (const rtems_rtl_obj* obj, - int section, - const char* name, - const Elf_Shdr* shdr, - const uint32_t flags) -{ - (void) obj; - (void) section; - (void) name; - (void) shdr; - return flags; -} - -bool -rtems_rtl_elf_arch_section_alloc (const rtems_rtl_obj* obj, - rtems_rtl_obj_sect* sect) -{ - (void) obj; - (void) sect; - return false; -} - -bool -rtems_rtl_elf_arch_section_free (const rtems_rtl_obj* obj, - rtems_rtl_obj_sect* sect) -{ - (void) obj; - (void) sect; - return false; -} - -bool -rtems_rtl_elf_rel_resolve_sym (Elf_Word type) -{ - return true; -} - -static inline Elf_Addr -load_ptr(void *where) -{ - Elf_Addr res; - - memcpy(&res, where, sizeof(res)); - - return (res); -} - -uint32_t rtems_rtl_obj_tramp_alignment (const rtems_rtl_obj* obj) -{ - (void) obj; - return sizeof(uint32_t); -} - -size_t -rtems_rtl_elf_relocate_tramp_max_size (void) -{ - /* - * Disable by returning 0. - */ - return 0; -} - -rtems_rtl_elf_rel_status -rtems_rtl_elf_relocate_rela_tramp (rtems_rtl_obj* obj, - const Elf_Rela* rela, - const rtems_rtl_obj_sect* sect, - const char* symname, - const Elf_Byte syminfo, - const Elf_Word symvalue) -{ - (void) obj; - (void) rela; - (void) sect; - (void) symname; - (void) syminfo; - (void) symvalue; - return rtems_rtl_elf_rel_no_error; -} - -rtems_rtl_elf_rel_status -rtems_rtl_elf_relocate_rela (rtems_rtl_obj* obj, - const Elf_Rela* rela, - const rtems_rtl_obj_sect* sect, - const char* symname, - const Elf_Byte syminfo, - const Elf_Word symvalue) -{ - Elf_Addr target = 0; - Elf_Addr *where; - Elf_Word tmp; - Elf_Word size; //byte - - where = (Elf_Addr *)(sect->base + rela->r_offset); - - if (rtems_rtl_trace (RTEMS_RTL_TRACE_RELOC)) { - printf("rela relocation type is %d relocated address 0x%08x", - ELF_R_TYPE(rela->r_info), where); - } - - tmp = symvalue; - switch (ELF_R_TYPE(rela->r_info)) { - case R_TYPE(UNUSED0): - break; - - case R_TYPE(HUIMM16): - tmp = symvalue >> 16; - case R_TYPE(LUIMM16): - case R_TYPE(RIMM16): - size = 2; - break; - - case R_TYPE(BYTE4_DATA): - size = 4; - break; - - case R_TYPE(PCREL24): - case R_TYPE(PCREL24_JU): - where = (Elf_Addr*)((Elf_Addr)where - 2); /* Back 2 bytes */ - tmp = symvalue - (Elf_Addr)where; - tmp >>= 1; - if ((tmp & 0x20000000) == 0x20000000) - tmp |= 0xc0000000; - - if ((tmp & 0xff000000) && (~tmp & 0xff800000)) { - printf("PCREL24/PCREL24_JU Overflow\n"); - return rtems_rtl_elf_rel_failure; - } - - tmp = (load_ptr(where) & 0x0000ff00) | ((tmp & 0x0000ffff) << 16) | - ((tmp & 0x00ff0000) >> 16); - size = 4; - break; - - case R_TYPE(PCREL12_JUMP_S): - tmp = symvalue - (Elf_Addr)where; - tmp >>= 1; - if ((tmp & 0x20000000) == 0x20000000) - tmp |= 0xc0000000; - - if ((tmp & 0xfffff000) && (~tmp & 0xfffff800)) { - printf("PCREL12_JUMP_S Overflow\n"); - return rtems_rtl_elf_rel_failure; - } - - tmp = ((*(uint16_t *)where) & 0xf000) | (tmp & 0xfff); - size = 2; - break; - - default: - printf("Unspported rela type\n"); - return rtems_rtl_elf_rel_failure; - } - - memcpy((void*)where, &tmp, size); - - return rtems_rtl_elf_rel_no_error; -} - -rtems_rtl_elf_rel_status -rtems_rtl_elf_relocate_rel_tramp (rtems_rtl_obj* obj, - const Elf_Rel* rel, - const rtems_rtl_obj_sect* sect, - const char* symname, - const Elf_Byte syminfo, - const Elf_Word symvalue) -{ - (void) obj; - (void) rel; - (void) sect; - (void) symname; - (void) syminfo; - (void) symvalue; - rtems_rtl_set_error (EINVAL, "rel type record not supported"); - return rtems_rtl_elf_rel_failure; -} - -rtems_rtl_elf_rel_status -rtems_rtl_elf_relocate_rel (rtems_rtl_obj* obj, - const Elf_Rel* rel, - const rtems_rtl_obj_sect* sect, - const char* symname, - const Elf_Byte syminfo, - const Elf_Word symvalue) -{ - (void) obj; - (void) rel; - (void) sect; - (void) symname; - (void) syminfo; - (void) symvalue; - rtems_rtl_set_error (EINVAL, "rel type record not supported"); - return rtems_rtl_elf_rel_failure; -} - -bool -rtems_rtl_elf_unwind_parse (const rtems_rtl_obj* obj, - const char* name, - uint32_t flags) -{ - return rtems_rtl_elf_unwind_dw2_parse (obj, name, flags); -} - -bool -rtems_rtl_elf_unwind_register (rtems_rtl_obj* obj) -{ - return rtems_rtl_elf_unwind_dw2_register (obj); -} - -bool -rtems_rtl_elf_unwind_deregister (rtems_rtl_obj* obj) -{ - return rtems_rtl_elf_unwind_dw2_deregister (obj); -} diff --git a/cpukit/score/cpu/bfin/bfin-exception-frame-print.c b/cpukit/score/cpu/bfin/bfin-exception-frame-print.c deleted file mode 100644 index d6c49f5569..0000000000 --- a/cpukit/score/cpu/bfin/bfin-exception-frame-print.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2012 embedded brains GmbH & Co. KG - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ) -{ - /* TODO */ -} diff --git a/cpukit/score/cpu/bfin/cpu.c b/cpukit/score/cpu/bfin/cpu.c deleted file mode 100644 index e0f91aae3e..0000000000 --- a/cpukit/score/cpu/bfin/cpu.c +++ /dev/null @@ -1,168 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Dependent Source - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - - -extern void _ISR15_Handler(void); -extern void _CPU_Emulation_handler(void); -extern void _CPU_Reset_handler(void); -extern void _CPU_NMI_handler(void); -extern void _CPU_Exception_handler(void); -extern void _CPU_Unhandled_Interrupt_handler(void); - -void _CPU_Initialize(void) -{ - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ - - - - CPU_ISR_raw_handler ignored; - -#if 0 - /* occassionally useful debug stuff */ - int i; - _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored); - _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored); - _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored); - _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored); - for (i = 5; i < 15; i++) - _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored); -#endif - - /* install handler that will be used to call _Thread_Dispatch */ - _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored ); - /* enable self nesting */ - __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004)); -} - -/* - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ - - register uint32_t _tmpimask; - - /*read from the IMASK registers*/ - - _tmpimask = *((uint32_t*)IMASK); - - return (_tmpimask & 0xffe0) ? 0 : 1; -} - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -) -{ - CPU_ISR_raw_handler *interrupt_table; - - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ - - /* base of vector table on blackfin architecture */ - interrupt_table = (void*)0xFFE02000; - - *old_handler = interrupt_table[ vector ]; - interrupt_table[ vector ] = new_handler; - -} - -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -) -{ - CPU_ISR_raw_handler ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); -} - -void *_CPU_Thread_Idle_body(uintptr_t ignored) -{ - while (1) { - __asm__ __volatile__("ssync; idle; ssync"); - } -} - -/* - * Copied from the arm port. - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -) -{ - uint32_t stack_high; /* highest "stack aligned" address */ - stack_high = ((uint32_t)(stack_base) + size); - - /* blackfin abi requires caller to reserve 12 bytes on stack */ - the_context->register_sp = stack_high - 12; - the_context->register_rets = (uint32_t) entry_point; - the_context->imask = new_level ? 0 : 0xffff; -} diff --git a/cpukit/score/cpu/bfin/cpu_asm.S b/cpukit/score/cpu/bfin/cpu_asm.S deleted file mode 100644 index 9e3984ad8f..0000000000 --- a/cpukit/score/cpu/bfin/cpu_asm.S +++ /dev/null @@ -1,576 +0,0 @@ -/* cpu_asm.S - * - * This file contains the basic algorithms for all assembly code used - * in the Blackfin port of RTEMS. These algorithms must be implemented - * in assembly language - * - * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA - * written by Allan Hessenflow - * - * Based on earlier version: - * - * Copyright (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include -#include -#include -#include - -#define LO(con32) ((con32) & 0xFFFF) -#define HI(con32) (((con32) >> 16) & 0xFFFF) - - -#if 0 -/* some debug routines */ - .globl SYM(_CPU_write_char); -SYM(_CPU_write_char): - p0.h = 0xffc0; - p0.l = 0x0400; -txWaitLoop: - r1 = w[p0 + 0x14]; - cc = bittst(r1, 5); - if !cc jump txWaitLoop; - w[p0 + 0x00] = r0; - rts; - - .globl SYM(_CPU_write_crlf); -SYM(_CPU_write_crlf): - r0 = '\r'; - [--sp] = rets; - call SYM(_CPU_write_char); - rets = [sp++]; - r0 = '\n'; - jump SYM(_CPU_write_char); - -SYM(_CPU_write_space): - r0 = ' '; - jump SYM(_CPU_write_char); - - .globl SYM(_CPU_write_nybble); -SYM(_CPU_write_nybble:) - r1 = 0x0f; - r0 = r0 & r1; - r0 += '0'; - r1 = '9'; - cc = r0 <= r1; - if cc jump SYM(_CPU_write_char); - r0 += 'a' - '0' - 10; - jump SYM(_CPU_write_char); - - .globl SYM(_CPU_write_byte); -SYM(_CPU_write_byte): - [--sp] = r0; - [--sp] = rets; - r0 >>= 4; - call SYM(_CPU_write_nybble); - rets = [sp++]; - r0 = [sp++]; - jump SYM(_CPU_write_nybble); - -SYM(_CPU_write_chawmp): - [--sp] = r0; - [--sp] = rets; - r0 >>= 8; - call SYM(_CPU_write_byte); - rets = [sp++]; - r0 = [sp++]; - jump SYM(_CPU_write_byte); - -SYM(_CPU_write_gawble): - [--sp] = r0; - [--sp] = rets; - r0 >>= 16; - call SYM(_CPU_write_chawmp); - rets = [sp++]; - r0 = [sp++]; - jump SYM(_CPU_write_chawmp); - -SYM(_CPU_dump_registers): - [--sp] = rets; - [--sp] = r0; - [--sp] = r1; - [--sp] = p0; - r0 = [sp + 8]; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = [sp + 4]; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r2; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r3; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r4; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r5; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r6; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = r7; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_crlf); - r0 = [sp]; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = p1; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = p2; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = p3; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = p4; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = p5; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = fp; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_space); - r0 = sp; - r0 += 16; - call SYM(_CPU_write_gawble); - call SYM(_CPU_write_crlf); - - p0 = [sp++]; - r1 = [sp++]; - r0 = [sp++]; - rets = [sp++]; - rts; - - .globl SYM(_CPU_Exception_handler); -SYM(_CPU_Exception_handler): - usp = sp; - sp.h = 0xffb0; - sp.l = 0x1000; - [--sp] = (r7:0,p5:0); - - r0 = 'x'; - call SYM(_CPU_write_char); - jump hcf; - - - .globl SYM(_CPU_Emulation_handler); -SYM(_CPU_Emulation_handler): - usp = sp; - sp.h = 0xffb0; - sp.l = 0x1000; - [--sp] = (r7:0,p5:0); - - r0 = 'e'; - call SYM(_CPU_write_char); - jump hcf; - - .globl SYM(_CPU_Reset_handler); -SYM(_CPU_Reset_handler): - usp = sp; - sp.h = 0xffb0; - sp.l = 0x1000; - [--sp] = (r7:0,p5:0); - - r0 = 'r'; - call SYM(_CPU_write_char); - jump hcf; - - .globl SYM(_CPU_NMI_handler); -SYM(_CPU_NMI_handler): - usp = sp; - sp.h = 0xffb0; - sp.l = 0x1000; - [--sp] = (r7:0,p5:0); - - r0 = 'n'; - call SYM(_CPU_write_char); - jump hcf; - - .globl SYM(_CPU_Unhandled_Interrupt_handler); -SYM(_CPU_Unhandled_Interrupt_handler): - usp = sp; - sp.h = 0xffb0; - sp.l = 0x1000; - [--sp] = (r7:0,p5:0); - - call SYM(_CPU_write_crlf); - r0 = 'i'; - call SYM(_CPU_write_char); - p0.h = HI(IPEND); - p0.l = LO(IPEND); - r0 = [p0]; - call SYM(_CPU_write_chawmp); - jump hcf; - -hcf: - idle; - jump hcf; - -#endif - - -/* _CPU_Context_switch - * - * This routine performs a normal non-FP context switch. - * - * bfin Specific Information: - * - * For now we simply save all registers. - * - */ - -/* make sure this sequence stays in sync with the definition for - Context_Control in rtems/score/cpu.h */ - .globl SYM(_CPU_Context_switch) -SYM(_CPU_Context_switch): - /* Start saving context R0 = current, R1=heir */ - p0 = r0; - [p0++] = r4; - [p0++] = r5; - [p0++] = r6; - [p0++] = r7; - - /* save pointer registers */ - [p0++] = p3; - [p0++] = p4; - [p0++] = p5; - [p0++] = fp; - [p0++] = sp; - - /* save rets */ - r0 = rets; - [p0++] = r0; - - /* save IMASK */ - p1.h = HI(IMASK); - p1.l = LO(IMASK); - r0 = [p1]; - [p0++] = r0; - - p0 = r1; -restore: - /* restore data registers */ - r4 = [p0++]; - r5 = [p0++]; - r6 = [p0++]; - r7 = [p0++]; - - /* restore pointer registers */ - p3 = [p0++]; - p4 = [p0++]; - p5 = [p0++]; - fp = [p0++]; - sp = [p0++]; - - /* restore rets */ - r0 = [p0++]; - rets = r0; - - /* restore IMASK */ - r0 = [p0++]; - p1.h = HI(IMASK); - p1.l = LO(IMASK); - [p1] = r0; - - rts; - - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - * - * Blackfin Specific Information: - * - * none - * - */ - .globl SYM(_CPU_Context_restore) -SYM(_CPU_Context_restore): - p0 = r0; - jump restore; - - - .globl SYM(_ISR_Handler) -SYM(_ISR_Handler): - /* all interrupts are disabled at this point */ - /* the following few items are pushed onto the task stack for at - most one interrupt; nested interrupts will be using the interrupt - stack for everything. */ - [--sp] = astat; - [--sp] = p1; - [--sp] = p0; - [--sp] = r1; - [--sp] = r0; - p0.h = ISR_NEST_LEVEL; - p0.l = ISR_NEST_LEVEL; - r0 = [p0]; - r0 += 1; - [p0] = r0; - cc = r0 <= 1 (iu); - if !cc jump noStackSwitch; - /* setup interrupt stack */ - r0 = sp; - p0.h = INTERRUPT_STACK_HIGH; - p0.l = INTERRUPT_STACK_HIGH; - sp = [p0]; - [--sp] = r0; -noStackSwitch: - /* disable thread dispatch */ - p0.h = THREAD_DISPATCH_DISABLE_LEVEL; - p0.l = THREAD_DISPATCH_DISABLE_LEVEL; - r0 = [p0]; - r0 += 1; - [p0] = r0; - - [--sp] = reti; /* interrupts are now enabled */ - - /* figure out what vector we are */ - p0.h = HI(IPEND); - p0.l = LO(IPEND); - r1 = [p0]; - /* we should only get here for events that require RTI to return */ - r1 = r1 >> 5; - r0 = 4; - /* at least one bit must be set, so this loop will exit */ -vectorIDLoop: - r0 += 1; - r1 = rot r1 by -1; - if !cc jump vectorIDLoop; - - [--sp] = r2; - r2.h = SYM(_ISR_Vector_table); - r2.l = SYM(_ISR_Vector_table); - r1 = r0 << 2; - r1 = r1 + r2; - p0 = r1; - p0 = [p0]; - cc = p0 == 0; - if cc jump noHandler; - - /* r2, r0, r1, p0, p1, astat are already saved */ - [--sp] = a1.x; - [--sp] = a1.w; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = r3; - [--sp] = p3; - [--sp] = p2; - [--sp] = lc1; - [--sp] = lc0; - [--sp] = lt1; - [--sp] = lt0; - [--sp] = lb1; - [--sp] = lb0; - [--sp] = i3; - [--sp] = i2; - [--sp] = i1; - [--sp] = i0; - [--sp] = m3; - [--sp] = m2; - [--sp] = m1; - [--sp] = m0; - [--sp] = l3; - [--sp] = l2; - [--sp] = l1; - [--sp] = l0; - [--sp] = b3; - [--sp] = b2; - [--sp] = b1; - [--sp] = b0; - [--sp] = rets; - /* call user isr; r0 = vector number, r1 = frame pointer */ - r1 = fp; /* is this really what should be passed here? */ - r2 = 0; - l0 = r2; - l1 = r2; - l2 = r2; - l3 = r2; - sp += -12; /* bizarre abi... */ - call (p0); - sp += 12; - rets = [sp++]; - b0 = [sp++]; - b1 = [sp++]; - b2 = [sp++]; - b3 = [sp++]; - l0 = [sp++]; - l1 = [sp++]; - l2 = [sp++]; - l3 = [sp++]; - m0 = [sp++]; - m1 = [sp++]; - m2 = [sp++]; - m3 = [sp++]; - i0 = [sp++]; - i1 = [sp++]; - i2 = [sp++]; - i3 = [sp++]; - lb0 = [sp++]; - lb1 = [sp++]; - lt0 = [sp++]; - lt1 = [sp++]; - lc0 = [sp++]; - lc1 = [sp++]; - p2 = [sp++]; - p3 = [sp++]; - r3 = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - a1.w = [sp++]; - a1.x = [sp++]; - -noHandler: - r2 = [sp++]; - /* this disables interrupts again */ - reti = [sp++]; - - p0.h = ISR_NEST_LEVEL; - p0.l = ISR_NEST_LEVEL; - r0 = [p0]; - r0 += -1; - [p0] = r0; - cc = r0 == 0; - if !cc jump noStackRestore; - sp = [sp]; -noStackRestore: - - /* check this stuff to ensure context_switch_necessary and - isr_signals_to_thread_executing are being handled appropriately. */ - p0.h = THREAD_DISPATCH_DISABLE_LEVEL; - p0.l = THREAD_DISPATCH_DISABLE_LEVEL; - r0 = [p0]; - r0 += -1; - [p0] = r0; - cc = r0 == 0; - if !cc jump noDispatch - - /* do thread dispatch if necessary */ - p0.h = DISPATCH_NEEDED; - p0.l = DISPATCH_NEEDED; - r0 = B[p0] (Z); - cc = r0 == 0; - if cc jump noDispatch -doDispatch: - raise 15; -noDispatch: - r0 = [sp++]; - r1 = [sp++]; - p0 = [sp++]; - p1 = [sp++]; - astat = [sp++]; - rti - - -/* the approach here is for the main interrupt handler, when a dispatch is - wanted, to do a "raise 15". when the main interrupt handler does its - "rti", the "raise 15" takes effect and we end up here. we can now - safely call _Thread_Dispatch, and do an "rti" to get back to the - original interrupted function. this does require self-nesting to be - enabled; the maximum nest depth is the number of tasks. */ - .global SYM(_ISR15_Handler) -SYM(_ISR15_Handler): - [--sp] = reti; - [--sp] = rets; - [--sp] = astat; - [--sp] = a1.x; - [--sp] = a1.w; - [--sp] = a0.x; - [--sp] = a0.w; - [--sp] = r3; - [--sp] = r2; - [--sp] = r1; - [--sp] = r0; - [--sp] = p3; - [--sp] = p2; - [--sp] = p1; - [--sp] = p0; - [--sp] = lc1; - [--sp] = lc0; - [--sp] = lt1; - [--sp] = lt0; - [--sp] = lb1; - [--sp] = lb0; - [--sp] = i3; - [--sp] = i2; - [--sp] = i1; - [--sp] = i0; - [--sp] = m3; - [--sp] = m2; - [--sp] = m1; - [--sp] = m0; - [--sp] = l3; - [--sp] = l2; - [--sp] = l1; - [--sp] = l0; - [--sp] = b3; - [--sp] = b2; - [--sp] = b1; - [--sp] = b0; - r2 = 0; - l0 = r2; - l1 = r2; - l2 = r2; - l3 = r2; - sp += -12; /* bizarre abi... */ - call SYM(_Thread_Dispatch); - sp += 12; - b0 = [sp++]; - b1 = [sp++]; - b2 = [sp++]; - b3 = [sp++]; - l0 = [sp++]; - l1 = [sp++]; - l2 = [sp++]; - l3 = [sp++]; - m0 = [sp++]; - m1 = [sp++]; - m2 = [sp++]; - m3 = [sp++]; - i0 = [sp++]; - i1 = [sp++]; - i2 = [sp++]; - i3 = [sp++]; - lb0 = [sp++]; - lb1 = [sp++]; - lt0 = [sp++]; - lt1 = [sp++]; - lc0 = [sp++]; - lc1 = [sp++]; - p0 = [sp++]; - p1 = [sp++]; - p2 = [sp++]; - p3 = [sp++]; - r0 = [sp++]; - r1 = [sp++]; - r2 = [sp++]; - r3 = [sp++]; - a0.w = [sp++]; - a0.x = [sp++]; - a1.w = [sp++]; - a1.x = [sp++]; - astat = [sp++]; - rets = [sp++]; - reti = [sp++]; - rti; - diff --git a/cpukit/score/cpu/bfin/include/machine/elf_machdep.h b/cpukit/score/cpu/bfin/include/machine/elf_machdep.h deleted file mode 100644 index cf0dc19221..0000000000 --- a/cpukit/score/cpu/bfin/include/machine/elf_machdep.h +++ /dev/null @@ -1,28 +0,0 @@ -#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB - -#define ELF32_MACHDEP_ID_CASES \ - case EM_BLACKFIN: \ - break; - -#define ELF32_MACHDEP_ID EM_BLACKFIN - -#define ARCH_ELFSIZE 32 - -#define R_BFIN_UNUSED0 0 - -#define R_BFIN_RIMM16 5 -#define R_BFIN_LUIMM16 6 -#define R_BFIN_HUIMM16 7 -#define R_BFIN_PCREL12_JUMP_S 8 -#define R_BFIN_PCREL24_JUMP_X 9 -#define R_BFIN_PCREL24 10 -#define R_BFIN_PCREL24_JU 13 -#define R_BFIN_PCREL24_CALL_X 14 - -#define R_BFIN_BYTE_DATA 16 -#define R_BFIN_BYTE2_DATA 17 -#define R_BFIN_BYTE4_DATA 18 - - - -#define R_TYPE(name) __CONCAT(R_BFIN_,name) diff --git a/cpukit/score/cpu/bfin/include/rtems/asm.h b/cpukit/score/cpu/bfin/include/rtems/asm.h deleted file mode 100644 index 5d133ddbdd..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - * @file - * - * @brief Address the Problems Caused by Incompatible Flavor of - * Assemblers and Toolsets - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * @note The spacing in the use of these macros - * is critical to them working as advertised. - */ - -/* - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - */ - -#ifndef _RTEMS_ASM_H -#define _RTEMS_ASM_H - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include -#include - -#ifndef __USER_LABEL_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all C program symbols. - */ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -/** - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - * - * This symbol is prefixed to all register names. - */ -#define __REGISTER_PREFIX__ -#endif - -#include - -/** Use the right prefix for global labels. */ -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/** Use the right prefix for registers. */ -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -/* - * Define macros to handle section beginning and ends. - */ - - -/** This macro is used to denote the beginning of a code declaration. */ -#define BEGIN_CODE_DCL .text -/** This macro is used to denote the end of a code declaration. */ -#define END_CODE_DCL -/** This macro is used to denote the beginning of a data declaration section. */ -#define BEGIN_DATA_DCL .data -/** This macro is used to denote the end of a data declaration section. */ -#define END_DATA_DCL -/** This macro is used to denote the beginning of a code section. */ -#define BEGIN_CODE .text -/** This macro is used to denote the end of a code section. */ -#define END_CODE -/** This macro is used to denote the beginning of a data section. */ -#define BEGIN_DATA -/** This macro is used to denote the end of a data section. */ -#define END_DATA -/** - * This macro is used to denote the beginning of the - * unitialized data section. - */ -#define BEGIN_BSS -/** This macro is used to denote the end of the unitialized data section. */ -#define END_BSS -/** This macro is used to denote the end of the assembly file. */ -#define END - -/** - * This macro is used to declare a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define PUBLIC(sym) .globl SYM (sym) - -/** - * This macro is used to prototype a public global symbol. - * - * @note This must be tailored for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ -#define EXTERN(sym) .globl SYM (sym) - -#endif diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h deleted file mode 100644 index 86142a6c62..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h +++ /dev/null @@ -1,430 +0,0 @@ -/** - * @file - * - * @brief Basic MMR for the Blackfin 52x CPU - * - * This file defines basic MMR for the Blackfin 52x CPU. - * The MMR have been taken from the ADSP-BF52x Blackfin Processor - * Hardware Reference from Analog Devices. Mentioned Chapters - * refer to this Documentation. - * - * Based on bf533.h - */ - -/* - * COPYRIGHT (c) 2006. - * Atos Automacao Industrial LTDA. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * - * Author: Rohan Kangralkar, ECE Department Northeastern University - * Date: 02/15/2011 - */ - -#ifndef _RTEMS_BFIN_52x_H -#define _RTEMS_BFIN_52x_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Clock and System Control Chapter 8 */ -#define PLL_CTL 0xFFC00000L -#define PLL_DIV 0xFFC00004L -#define VR_CTL 0xFFC00008L -#define PLL_STAT 0xFFC0000CL -#define PLL_LOCKCNT 0xFFC00010L -#define SWRST 0xFFC00100L -#define SYSCR 0xFFC00104L - -/* SPI Controller Chapter 10 */ -#define SPI_CTL 0xFFC00500L -#define SPI_FLG 0xFFC00504L -#define SPI_STAT 0xFFC00508L -#define SPI_TDBR 0xFFC0050CL -#define SPI_RDBR 0xFFC00510L -#define SPI_BAUD 0xFFC00514L -#define SPI_SHADOW 0xFFC00518L - -/* SPORT0 Controller */ -#define SPORT0_TCR1 0xFFC00800L -#define SPORT0_TCR2 0xFFC00804L -#define SPORT0_TCLKDIV 0xFFC00808L -#define SPORT0_TFSDIV 0xFFC0080CL -#define SPORT0_TX 0xFFC00810L -#define SPORT0_RX 0xFFC00818L -#define SPORT0_RCR1 0xFFC00820L -#define SPORT0_RCR2 0xFFC00824L -#define SPORT0_RCLKDIV 0xFFC00828L -#define SPORT0_RFSDIV 0xFFC0082CL -#define SPORT0_STAT 0xFFC00830L -#define SPORT0_CHNL 0xFFC00834L -#define SPORT0_MCMC1 0xFFC00838L -#define SPORT0_MCMC2 0xFFC0083CL -#define SPORT0_MTCS0 0xFFC00840L -#define SPORT0_MTCS1 0xFFC00844L -#define SPORT0_MTCS2 0xFFC00848L -#define SPORT0_MTCS3 0xFFC0084CL -#define SPORT0_MRCS0 0xFFC00850L -#define SPORT0_MRCS1 0xFFC00854L -#define SPORT0_MRCS2 0xFFC00858L -#define SPORT0_MRCS3 0xFFC0085CL - -/* Parallel Peripheral Interface (PPI) Chapter 11 */ - -#define PPI_CONTROL 0xFFC01000L -#define PPI_STATUS 0xFFC01004L -#define PPI_COUNT 0xFFC01008L -#define PPI_DELAY 0xFFC0100CL -#define PPI_FRAME 0xFFC01010L - -/********* PPI MASKS ***********/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 -#define PORT_DIR 0x00000002 -#define XFR_TYPE 0x0000000C -#define PORT_CFG 0x00000030 -#define FLD_SEL 0x00000040 -#define PACK_EN 0x00000080 -#define DMA32 0x00000100 -#define SKIP_EN 0x00000200 -#define SKIP_EO 0x00000400 -#define DLENGTH 0x00003800 -#define DLEN_8 0x0 -#define DLEN(x) (((x-9) & 0x07) << 11) -#define POL 0x0000C000 - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 -#define FT_ERR 0x00000800 -#define OVR 0x00001000 -#define UNDR 0x00002000 -#define ERR_DET 0x00004000 -#define ERR_NCOR 0x00008000 - -/* SPORT1 Controller Chapter 12 */ -#define SPORT1_TCR1 0xFFC00900L -#define SPORT1_TCR2 0xFFC00904L -#define SPORT1_TCLKDIV 0xFFC00908L -#define SPORT1_TFSDIV 0xFFC0090CL -#define SPORT1_TX 0xFFC00910L -#define SPORT1_RX 0xFFC00918L -#define SPORT1_RCR1 0xFFC00920L -#define SPORT1_RCR2 0xFFC00924L -#define SPORT1_RCLKDIV 0xFFC00928L -#define SPORT1_RFSDIV 0xFFC0092CL -#define SPORT1_STAT 0xFFC00930L -#define SPORT1_CHNL 0xFFC00934L -#define SPORT1_MCMC1 0xFFC00938L -#define SPORT1_MCMC2 0xFFC0093CL -#define SPORT1_MTCS0 0xFFC00940L -#define SPORT1_MTCS1 0xFFC00944L -#define SPORT1_MTCS2 0xFFC00948L -#define SPORT1_MTCS3 0xFFC0094CL -#define SPORT1_MRCS0 0xFFC00950L -#define SPORT1_MRCS1 0xFFC00954L -#define SPORT1_MRCS2 0xFFC00958L -#define SPORT1_MRCS3 0xFFC0095CL - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 -#define ITCLK 0x0002 -#define TDTYPE 0x000C -#define TLSBIT 0x0010 -#define ITFS 0x0200 -#define TFSR 0x0400 -#define DITFS 0x0800 -#define LTFS 0x1000 -#define LATFS 0x2000 -#define TCKFE 0x4000 - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F -#define TXSE 0x0100 -#define TSFSE 0x0200 -#define TRFST 0x0400 - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 -#define IRCLK 0x0002 -#define RDTYPE 0x000C -#define RULAW 0x0008 -#define RALAW 0x000C -#define RLSBIT 0x0010 -#define IRFS 0x0200 -#define RFSR 0x0400 -#define LRFS 0x1000 -#define LARFS 0x2000 -#define RCKFE 0x4000 - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F -#define RXSE 0x0100 -#define RSFSE 0x0200 -#define RRFST 0x0400 - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 -#define RUVF 0x0002 -#define ROVF 0x0004 -#define TXF 0x0008 -#define TUVF 0x0010 -#define TOVF 0x0020 -#define TXHRE 0x0040 - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 -#define WOFF 0x000003FF - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 -#define MCDTXPE 0x00000004 -#define MCDRXPE 0x00000008 -#define MCMEN 0x00000010 -#define FSDR 0x00000080 -#define MFD 0x0000F000 - -/* UART Controller Chapter 13 */ -#define UART_THR 0xFFC00400L -#define UART_RBR 0xFFC00400L -#define UART_DLL 0xFFC00400L -#define UART_IER 0xFFC00404L -#define UART_DLH 0xFFC00404L -#define UART_IIR 0xFFC00408L -#define UART_LCR 0xFFC0040CL -#define UART_MCR 0xFFC00410L -#define UART_LSR 0xFFC00414L -#define UART_SCR 0xFFC0041CL -#define UART_GCTL 0xFFC00424L - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* General Purpose IO Chapter 14*/ -#define FIO_FLAG_D 0xFFC00700L -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL -#define FIO_DIR 0xFFC00730L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL -#define FIO_INEN 0xFFC00740L - - -/* General Purpose IO Chapter 9*/ -#define PORTH_FER 0xFFC03208 -#define PORTH_MUX 0xFFC03218 -#define PORTHIO_DIR 0xFFC01730 -#define PORTHIO_INEN 0xFFC01740 -#define PORTHIO 0xFFC01700 -#define PORTHIO_SET 0xFFC01708 -#define PORTHIO_CLEAR 0xFFC01704 -#define PORTHIO_TOGGLE 0xFFC0170C - - -#define FIO_INEN 0xFFC00740L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL - - - -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL - - -/* General Purpose IO Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - - -/* TIMER 0, 1, 2 Chapter 15 */ -#define TIMER0_CONFIG 0xFFC00600L -#define TIMER0_COUNTER 0xFFC00604L -#define TIMER0_PERIOD 0xFFC00608L -#define TIMER0_WIDTH 0xFFC0060CL - -#define TIMER1_CONFIG 0xFFC00610L -#define TIMER1_COUNTER 0xFFC00614L -#define TIMER1_PERIOD 0xFFC00618L -#define TIMER1_WIDTH 0xFFC0061CL - -#define TIMER2_CONFIG 0xFFC00620L -#define TIMER2_COUNTER 0xFFC00624L -#define TIMER2_PERIOD 0xFFC00628L -#define TIMER2_WIDTH 0xFFC0062CL - -#define TIMER_ENABLE 0xFFC00640L -#define TIMER_DISABLE 0xFFC00644L -#define TIMER_STATUS 0xFFC00648L - -/* Real Time Clock Chapter 16 */ -#define RTC_STAT 0xFFC00300L -#define RTC_ICTL 0xFFC00304L -#define RTC_ISTAT 0xFFC00308L -#define RTC_SWCNT 0xFFC0030CL -#define RTC_ALARM 0xFFC00310L -#define RTC_FAST 0xFFC00314L -#define RTC_PREN 0xFFC00314L - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 -#define PREN 0x00000001 - -/* Asynchronous Memory Controller EBUI, Chapter 17*/ -#define EBIU_AMGCTL 0xFFC00A00L -#define EBIU_AMBCTL0 0xFFC00A04L -#define EBIU_AMBCTL1 0xFFC00A08L - -/* SDRAM Controller External Bus Interface Unit */ - -#define EBIU_SDGCTL 0xFFC00A10L -#define EBIU_SDBCTL 0xFFC00A14L -#define EBIU_SDRRC 0xFFC00A18L -#define EBIU_SDSTAT 0xFFC00A1CL - - - - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/*** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ -/*** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ -/*** ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ -/*** DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h deleted file mode 100644 index 2b2f97cdc7..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h +++ /dev/null @@ -1,405 +0,0 @@ -/** - * @file - * - * @brief Basic MMR for the Blackfin 531/532/533 CPU - * - * This file defines basic MMR for the Blackfin 531/532/533 CPU. - * The MMR have been taken from the ADSP-BF533 Blackfin Processor - * Hardware Reference from Analog Devices. Mentioned Chapters - * refer to this Documentation. - * - * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF) - * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined - * in bfin.h which is included. - */ -/* - * COPYRIGHT (c) 2006. - * Atos Automacao Industrial LTDA. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_BFIN_533_H -#define _RTEMS_BFIN_533_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Clock and System Control Chapter 8 */ -#define PLL_CTL 0xFFC00000L -#define PLL_DIV 0xFFC00004L -#define VR_CTL 0xFFC00008L -#define PLL_STAT 0xFFC0000CL -#define PLL_LOCKCNT 0xFFC00010L -#define SWRST 0xFFC00100L -#define SYSCR 0xFFC00104L - -/* SPI Controller Chapter 10 */ -#define SPI_CTL 0xFFC00500L -#define SPI_FLG 0xFFC00504L -#define SPI_STAT 0xFFC00508L -#define SPI_TDBR 0xFFC0050CL -#define SPI_RDBR 0xFFC00510L -#define SPI_BAUD 0xFFC00514L -#define SPI_SHADOW 0xFFC00518L - -/* SPORT0 Controller */ -#define SPORT0_TCR1 0xFFC00800L -#define SPORT0_TCR2 0xFFC00804L -#define SPORT0_TCLKDIV 0xFFC00808L -#define SPORT0_TFSDIV 0xFFC0080CL -#define SPORT0_TX 0xFFC00810L -#define SPORT0_RX 0xFFC00818L -#define SPORT0_RCR1 0xFFC00820L -#define SPORT0_RCR2 0xFFC00824L -#define SPORT0_RCLKDIV 0xFFC00828L -#define SPORT0_RFSDIV 0xFFC0082CL -#define SPORT0_STAT 0xFFC00830L -#define SPORT0_CHNL 0xFFC00834L -#define SPORT0_MCMC1 0xFFC00838L -#define SPORT0_MCMC2 0xFFC0083CL -#define SPORT0_MTCS0 0xFFC00840L -#define SPORT0_MTCS1 0xFFC00844L -#define SPORT0_MTCS2 0xFFC00848L -#define SPORT0_MTCS3 0xFFC0084CL -#define SPORT0_MRCS0 0xFFC00850L -#define SPORT0_MRCS1 0xFFC00854L -#define SPORT0_MRCS2 0xFFC00858L -#define SPORT0_MRCS3 0xFFC0085CL - -/* Parallel Peripheral Interface (PPI) Chapter 11 */ - -#define PPI_CONTROL 0xFFC01000L -#define PPI_STATUS 0xFFC01004L -#define PPI_COUNT 0xFFC01008L -#define PPI_DELAY 0xFFC0100CL -#define PPI_FRAME 0xFFC01010L - -/********* PPI MASKS ***********/ -/* PPI_CONTROL Masks */ -#define PORT_EN 0x00000001 -#define PORT_DIR 0x00000002 -#define XFR_TYPE 0x0000000C -#define PORT_CFG 0x00000030 -#define FLD_SEL 0x00000040 -#define PACK_EN 0x00000080 -#define DMA32 0x00000100 -#define SKIP_EN 0x00000200 -#define SKIP_EO 0x00000400 -#define DLENGTH 0x00003800 -#define DLEN_8 0x0 -#define DLEN(x) (((x-9) & 0x07) << 11) -#define POL 0x0000C000 - -/* PPI_STATUS Masks */ -#define FLD 0x00000400 -#define FT_ERR 0x00000800 -#define OVR 0x00001000 -#define UNDR 0x00002000 -#define ERR_DET 0x00004000 -#define ERR_NCOR 0x00008000 - -/* SPORT1 Controller Chapter 12 */ -#define SPORT1_TCR1 0xFFC00900L -#define SPORT1_TCR2 0xFFC00904L -#define SPORT1_TCLKDIV 0xFFC00908L -#define SPORT1_TFSDIV 0xFFC0090CL -#define SPORT1_TX 0xFFC00910L -#define SPORT1_RX 0xFFC00918L -#define SPORT1_RCR1 0xFFC00920L -#define SPORT1_RCR2 0xFFC00924L -#define SPORT1_RCLKDIV 0xFFC00928L -#define SPORT1_RFSDIV 0xFFC0092CL -#define SPORT1_STAT 0xFFC00930L -#define SPORT1_CHNL 0xFFC00934L -#define SPORT1_MCMC1 0xFFC00938L -#define SPORT1_MCMC2 0xFFC0093CL -#define SPORT1_MTCS0 0xFFC00940L -#define SPORT1_MTCS1 0xFFC00944L -#define SPORT1_MTCS2 0xFFC00948L -#define SPORT1_MTCS3 0xFFC0094CL -#define SPORT1_MRCS0 0xFFC00950L -#define SPORT1_MRCS1 0xFFC00954L -#define SPORT1_MRCS2 0xFFC00958L -#define SPORT1_MRCS3 0xFFC0095CL - -/* SPORTx_TCR1 Masks */ -#define TSPEN 0x0001 -#define ITCLK 0x0002 -#define TDTYPE 0x000C -#define TLSBIT 0x0010 -#define ITFS 0x0200 -#define TFSR 0x0400 -#define DITFS 0x0800 -#define LTFS 0x1000 -#define LATFS 0x2000 -#define TCKFE 0x4000 - -/* SPORTx_TCR2 Masks */ -#define SLEN 0x001F -#define TXSE 0x0100 -#define TSFSE 0x0200 -#define TRFST 0x0400 - -/* SPORTx_RCR1 Masks */ -#define RSPEN 0x0001 -#define IRCLK 0x0002 -#define RDTYPE 0x000C -#define RULAW 0x0008 -#define RALAW 0x000C -#define RLSBIT 0x0010 -#define IRFS 0x0200 -#define RFSR 0x0400 -#define LRFS 0x1000 -#define LARFS 0x2000 -#define RCKFE 0x4000 - -/* SPORTx_RCR2 Masks */ -#define SLEN 0x001F -#define RXSE 0x0100 -#define RSFSE 0x0200 -#define RRFST 0x0400 - -/* SPORTx_STAT Masks */ -#define RXNE 0x0001 -#define RUVF 0x0002 -#define ROVF 0x0004 -#define TXF 0x0008 -#define TUVF 0x0010 -#define TOVF 0x0020 -#define TXHRE 0x0040 - -/* SPORTx_MCMC1 Masks */ -#define WSIZE 0x0000F000 -#define WOFF 0x000003FF - -/* SPORTx_MCMC2 Masks */ -#define MCCRM 0x00000003 -#define MCDTXPE 0x00000004 -#define MCDRXPE 0x00000008 -#define MCMEN 0x00000010 -#define FSDR 0x00000080 -#define MFD 0x0000F000 - -/* UART Controller Chapter 13 */ -#define UART_THR 0xFFC00400L -#define UART_RBR 0xFFC00400L -#define UART_DLL 0xFFC00400L -#define UART_IER 0xFFC00404L -#define UART_DLH 0xFFC00404L -#define UART_IIR 0xFFC00408L -#define UART_LCR 0xFFC0040CL -#define UART_MCR 0xFFC00410L -#define UART_LSR 0xFFC00414L -#define UART_SCR 0xFFC0041CL -#define UART_GCTL 0xFFC00424L - -/* - * UART CONTROLLER MASKS - */ - -/* UART_LCR */ -#define DLAB 0x80 -#define SB 0x40 -#define STP 0x20 -#define EPS 0x10 -#define PEN 0x08 -#define STB 0x04 -#define WLS(x) ((x-5) & 0x03) - -#define DLAB_P 0x07 -#define SB_P 0x06 -#define STP_P 0x05 -#define EPS_P 0x04 -#define PEN_P 0x03 -#define STB_P 0x02 -#define WLS_P1 0x01 -#define WLS_P0 0x00 - -/* UART_MCR */ -#define LOOP_ENA 0x10 -#define LOOP_ENA_P 0x04 - -/* UART_LSR */ -#define TEMT 0x40 -#define THRE 0x20 -#define BI 0x10 -#define FE 0x08 -#define PE 0x04 -#define OE 0x02 -#define DR 0x01 - -#define TEMP_P 0x06 -#define THRE_P 0x05 -#define BI_P 0x04 -#define FE_P 0x03 -#define PE_P 0x02 -#define OE_P 0x01 -#define DR_P 0x00 - -/* UART_IER */ -#define ELSI 0x04 -#define ETBEI 0x02 -#define ERBFI 0x01 - -#define ELSI_P 0x02 -#define ETBEI_P 0x01 -#define ERBFI_P 0x00 - -/* UART_IIR */ -#define STATUS(x) ((x << 1) & 0x06) -#define NINT 0x01 -#define STATUS_P1 0x02 -#define STATUS_P0 0x01 -#define NINT_P 0x00 - -/* UART_GCTL */ -#define FFE 0x20 -#define FPE 0x10 -#define RPOLC 0x08 -#define TPOLC 0x04 -#define IREN 0x02 -#define UCEN 0x01 - -#define FFE_P 0x05 -#define FPE_P 0x04 -#define RPOLC_P 0x03 -#define TPOLC_P 0x02 -#define IREN_P 0x01 -#define UCEN_P 0x00 - -/* General Purpose IO Chapter 14*/ -#define FIO_FLAG_D 0xFFC00700L -#define FIO_FLAG_C 0xFFC00704L -#define FIO_FLAG_S 0xFFC00708L -#define FIO_FLAG_T 0xFFC0070CL -#define FIO_MASKA_D 0xFFC00710L -#define FIO_MASKA_C 0xFFC00714L -#define FIO_MASKA_S 0xFFC00718L -#define FIO_MASKA_T 0xFFC0071CL -#define FIO_MASKB_D 0xFFC00720L -#define FIO_MASKB_C 0xFFC00724L -#define FIO_MASKB_S 0xFFC00728L -#define FIO_MASKB_T 0xFFC0072CL -#define FIO_DIR 0xFFC00730L -#define FIO_POLAR 0xFFC00734L -#define FIO_EDGE 0xFFC00738L -#define FIO_BOTH 0xFFC0073CL -#define FIO_INEN 0xFFC00740L - -/* General Purpose IO Masks */ -#define PF0 0x0001 -#define PF1 0x0002 -#define PF2 0x0004 -#define PF3 0x0008 -#define PF4 0x0010 -#define PF5 0x0020 -#define PF6 0x0040 -#define PF7 0x0080 -#define PF8 0x0100 -#define PF9 0x0200 -#define PF10 0x0400 -#define PF11 0x0800 -#define PF12 0x1000 -#define PF13 0x2000 -#define PF14 0x4000 -#define PF15 0x8000 - - -/* TIMER 0, 1, 2 Chapter 15 */ -#define TIMER0_CONFIG 0xFFC00600L -#define TIMER0_COUNTER 0xFFC00604L -#define TIMER0_PERIOD 0xFFC00608L -#define TIMER0_WIDTH 0xFFC0060CL - -#define TIMER1_CONFIG 0xFFC00610L -#define TIMER1_COUNTER 0xFFC00614L -#define TIMER1_PERIOD 0xFFC00618L -#define TIMER1_WIDTH 0xFFC0061CL - -#define TIMER2_CONFIG 0xFFC00620L -#define TIMER2_COUNTER 0xFFC00624L -#define TIMER2_PERIOD 0xFFC00628L -#define TIMER2_WIDTH 0xFFC0062CL - -/* - * These are defined in bsps/bfin/include/bf52x.h. Ensure those definitions - * are consistent with our expectations. -#define TIMER_ENABLE 0xFFC00640L -#define TIMER_DISABLE 0xFFC00644L -#define TIMER_STATUS 0xFFC00648L -*/ -#if ((TIMER_ENABLE != 0xFFC00640L) || \ - (TIMER_DISABLE != 0xFFC00644L) || \ - (TIMER_STATUS != 0xFFC00648L)) -#error "Timer register addresses are inconsistent" -#endif - -/* Real Time Clock Chapter 16 */ -#define RTC_STAT 0xFFC00300L -#define RTC_ICTL 0xFFC00304L -#define RTC_ISTAT 0xFFC00308L -#define RTC_SWCNT 0xFFC0030CL -#define RTC_ALARM 0xFFC00310L -#define RTC_FAST 0xFFC00314L -#define RTC_PREN 0xFFC00314L - -/* RTC_FAST Mask (RTC_PREN Mask) */ -#define ENABLE_PRESCALE 0x00000001 -#define PREN 0x00000001 - -/* Asynchronous Memory Controller EBUI, Chapter 17*/ -#define EBIU_AMGCTL 0xFFC00A00L -#define EBIU_AMBCTL0 0xFFC00A04L -#define EBIU_AMBCTL1 0xFFC00A08L - -/* SDRAM Controller External Bus Interface Unit */ - -#define EBIU_SDGCTL 0xFFC00A10L -#define EBIU_SDBCTL 0xFFC00A14L -#define EBIU_SDRRC 0xFFC00A18L -#define EBIU_SDSTAT 0xFFC00A1CL - - - - -/* DCPLB_DATA and ICPLB_DATA Registers */ -/*** Bit Positions */ -#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ -/*** Masks */ -#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ -#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ -#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ -#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ -#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ -#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ -#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ -#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ -/*** ICPLB_DATA only */ -#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ -/*** DCPLB_DATA only */ -#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ -#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ -#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ -#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ - /* 1= allocate cache lines on write-through writes. */ -#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ - - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h deleted file mode 100644 index 4ba0b2b295..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file - * - * @brief Macros for MMR register common to all Blackfin Processors - * - * This file defines Macros for MMR register common to all Blackfin - * Processors. - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_BFIN_BFIN_H -#define _RTEMS_BFIN_BFIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Scratchpad SRAM */ - -#define SCRATCH 0xFFB00000 -#define SCRATCH_SIZE 0x1000 -#define SCRATCH_TOP 0xFFB00ffc - - -/* System Interrupt Controller Chapter 4*/ -#define SIC_RVECT 0xFFC00108 -#define SIC_IMASK 0xFFC0010C -#define SIC_IAR0 0xFFC00110 -#define SIC_IAR1 0xFFC00114 -#define SIC_IAR2 0xFFC00118 -#define SIC_ISR 0xFFC00120 -#define SIC_IWR 0xFFC00124 - -/* Event Vector Table Chapter 4 */ - -#define EVT0 0xFFE02000 -#define EVT1 0xFFE02004 -#define EVT2 0xFFE02008 -#define EVT3 0xFFE0200C -#define EVT4 0xFFE02010 -#define EVT5 0xFFE02014 -#define EVT6 0xFFE02018 -#define EVT7 0xFFE0201C -#define EVT8 0xFFE02020 -#define EVT9 0xFFE02024 -#define EVT10 0xFFE02028 -#define EVT11 0xFFE0202C -#define EVT12 0xFFE02030 -#define EVT13 0xFFE02034 -#define EVT14 0xFFE02038 -#define EVT15 0xFFE0203C -#define IMASK 0xFFE02104 -#define IPEND 0xFFE02108 -#define ILAT 0xFFE0210C -#define IPRIO 0xFFE02110 - - -#define TCNTL 0xFFE03000 -#define TPERIOD 0xFFE03004 -#define TSCALE 0xFFE03008 -#define TCOUNT 0xFFE0300C - -/* Masks for Timer Control */ -#define TMPWR 0x00000001 -#define TMREN 0x00000002 -#define TAUTORLD 0x00000004 -#define TINT 0x00000008 - -/* Event Bit Positions */ -#define EVT_IVTMR_P 0x00000006 - -#define EVT_IVTMR (1 << EVT_IVTMR_P) - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/bfin.h b/cpukit/score/cpu/bfin/include/rtems/score/bfin.h deleted file mode 100644 index caa3a51830..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/score/bfin.h +++ /dev/null @@ -1,69 +0,0 @@ -/** - * @file - * - * @brief Blackfin Set up Basic CPU Dependency Settings Based on - * Compiler Settings - * - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the Blackfin port. - */ - -/* - * - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * modified by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_BFIN_H -#define _RTEMS_SCORE_BFIN_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* - * This file contains the information required to build - * RTEMS for a particular member of the Blackfin family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ -#if defined(__BFIN__) -#define CPU_MODEL_NAME "BF533" -#define BF_HAS_FPU 0 -#else - -#error "Unsupported CPU Model" - -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "BFIN" - -#ifdef __cplusplus -} -#endif - -#endif /* _RTEMS_SCORE_BFIN_H */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu.h deleted file mode 100644 index a1c379ea3d..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/score/cpu.h +++ /dev/null @@ -1,617 +0,0 @@ -/** - * @file - * - * @brief Blackfin CPU Department Source - * - * This include file contains information pertaining to the Blackfin - * processor. - */ - -/* - * COPYRIGHT (c) 1989-2006. - * On-Line Applications Research Corporation (OAR). - * adapted to Blackfin by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/* conditional compilation parameters */ - -/* - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * BFIN Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER TRUE - -#define CPU_HARDWARE_FP FALSE - -#define CPU_SOFTWARE_FP FALSE - -#define CPU_ALL_TASKS_ARE_FP FALSE - -#define CPU_IDLE_TASK_IS_FP FALSE - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP FALSE - -/* FIXME: Is this the right value? */ -#define CPU_CACHE_LINE_BYTES 32 - -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -#define CPU_MAXIMUM_PROCESSORS 32 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -#ifndef ASM - -/** - * @defgroup RTEMSScoreCPUBfinCPUContext Processor Dependent Context Management - * - * @ingroup RTEMSScoreCPUBfin - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -/**@{**/ - -/** - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ - -/* make sure this stays in sync with the assembly function - __CPU_Context_switch in cpu_asm.S */ -typedef struct { - uint32_t register_r4; - uint32_t register_r5; - uint32_t register_r6; - uint32_t register_r7; - - uint32_t register_p3; - uint32_t register_p4; - uint32_t register_p5; - uint32_t register_fp; - uint32_t register_sp; - - uint32_t register_rets; - - uint32_t imask; -} Context_Control; - -#define _CPU_Context_Get_SP( _context ) \ - (_context)->register_sp - -/** - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - /*uint32_t special_interrupt_register;*/ -} CPU_Interrupt_frame; - -/** @} */ - -/** - * @defgroup RTEMSScoreCPUBfinCPUInterrupt Processor Dependent Interrupt Management - * - * @ingroup RTEMSScoreCPUBfin - */ -/** @{ **/ -/** @} **/ - -#endif /* ASM */ - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16 - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * @addtogroup RTEMSScoreCPUBfinCPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*8) - -#define CPU_SIZEOF_POINTER 4 - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -#define CPU_STACK_ALIGNMENT 8 - -#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES - -#ifndef ASM - -/* - * ISR handler macros - */ - -/** - * @addtogroup RTEMSScoreCPUBfinCPUInterrupt - */ -/**@{**/ - -/** - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Disable( _level ) \ - { \ - __asm__ volatile ("cli %0; csync \n" : "=d" (_level) ); \ - } - - -/** - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _level ) { \ - __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) ); \ - } - -/** - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _level ) { \ - __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \ - : : "d"(_level) : "R0" ); \ - } - -static inline bool _CPU_ISR_Is_enabled( uint32_t level ) -{ - return level != 0; -} - -/** - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( _new_level ) \ - { \ - __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \ - } - -/** - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** @} */ - -/* Context handler macros */ - -/** - * @addtogroup RTEMSScoreCPUBfinCPUContext - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * @param[in] _the_context is the context structure to be initialized - * @param[in] _stack_base is the lowest physical address of this task's stack - * @param[in] _size is the size of this task's stack - * @param[in] _isr is the interrupt disable level - * @param[in] _entry_point is the thread's entry point. This is - * always @a _Thread_Handler - * @param[in] _is_fp is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - * @param[in] tls_area is the thread-local storage (TLS) area - * - * Port Specific Information: - * - * See implementation in cpu.c - */ -void _CPU_Context_Initialize( - Context_Control *the_context, - uint32_t *stack_base, - uint32_t size, - uint32_t new_level, - void *entry_point, - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* end of Context handler macros */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -#define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE - -/* functions */ - -/** - * @brief CPU initialize. - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -typedef void ( *CPU_ISR_raw_handler )( void ); - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - CPU_ISR_raw_handler new_handler, - CPU_ISR_raw_handler *old_handler -); - -typedef void ( *CPU_ISR_handler )( uint32_t ); - -void _CPU_ISR_install_vector( - uint32_t vector, - CPU_ISR_handler new_handler, - CPU_ISR_handler *old_handler -); - -RTEMS_NO_RETURN void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @addtogroup RTEMSScoreCPUBfinCPUContext - */ -/**@{**/ - -/** - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); - -/** @} */ - -/* FIXME */ -typedef CPU_Interrupt_frame CPU_Exception_frame; - -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); - -/** - * - * @defgroup RTEMSScoreCPUBfinCPUEndian CPUEndian - * - * @ingroup RTEMSScoreCPUBfin - * - * @brief CPUEndian - */ -/** @{ */ -/* - * - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -/** - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -/** @} */ - -typedef uint32_t CPU_Counter_ticks; - -uint32_t _CPU_Counter_frequency( void ); - -CPU_Counter_ticks _CPU_Counter_read( void ); - -/** Type that can store a 32-bit integer or a pointer. */ -typedef uintptr_t CPU_Uint32ptr; - -#endif /* ASM */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h deleted file mode 100644 index 4f78c9d358..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h +++ /dev/null @@ -1,27 +0,0 @@ -/** - * @file - * - * @brief Blackfin Assembly File - * - * Defines a couple of Macros used in cpu_asm.S - */ - -/* - * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. - * written by Alain Schaefer - * and Antonio Giovanini - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - */ - -#ifndef _RTEMS_SCORE_CPU_ASM_H -#define _RTEMS_SCORE_CPU_ASM_H - - - -#endif - -/* end of file */ diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h deleted file mode 100644 index cc56aa3bbd..0000000000 --- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h +++ /dev/null @@ -1,89 +0,0 @@ -/** - * @file - * - * @brief CPU Port Implementation API - */ - -/* - * Copyright (c) 2013 embedded brains GmbH & Co. KG - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_SCORE_CPUIMPL_H -#define _RTEMS_SCORE_CPUIMPL_H - -#include - -/** - * @defgroup RTEMSScoreCPUBfin Blackfin - * - * @ingroup RTEMSScoreCPU - * - * @brief Blackfin Architecture Support - * - * @{ - */ - -#define CPU_PER_CPU_CONTROL_SIZE 0 - -#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern ) -{ - (void) pattern; - - /* TODO */ -} - -static inline void _CPU_Context_validate( uintptr_t pattern ) -{ - (void) pattern; - - while (1) { - /* TODO */ - } -} - -static inline void _CPU_Instruction_illegal( void ) -{ - __asm__ volatile ( ".word 0" ); -} - -static inline void _CPU_Instruction_no_operation( void ) -{ - __asm__ volatile ( "nop" ); -} - -static inline void _CPU_Use_thread_local_storage( - const Context_Control *context -) -{ - (void) context; -} - -static inline void *_CPU_Get_TLS_thread_pointer( - const Context_Control *context -) -{ - (void) context; - return NULL; -} - -#ifdef __cplusplus -} -#endif - -#endif /* ASM */ - -/** @} */ - -#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/spec/build/bsps/bfin/TLL6527M/abi.yml b/spec/build/bsps/bfin/TLL6527M/abi.yml deleted file mode 100644 index b046347ce0..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/abi.yml +++ /dev/null @@ -1,18 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -mcpu=bf527 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/bsptll6527m.yml b/spec/build/bsps/bfin/TLL6527M/bsptll6527m.yml deleted file mode 100644 index 521cfcb520..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/bsptll6527m.yml +++ /dev/null @@ -1,62 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: bfin -bsp: TLL6527M -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: TLL6527M -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/bfin/TLL6527M/include/bsp.h - - bsps/bfin/TLL6527M/include/cplb.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/bfin/TLL6527M/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/bfin/TLL6527M/start/linkcmds -links: -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: ../obj -- role: build-dependency - uid: ../start -- role: build-dependency - uid: abi -- role: build-dependency - uid: optconbaud -- role: build-dependency - uid: optconirq -- role: build-dependency - uid: optirqtbl -- role: build-dependency - uid: optskyeye -- role: build-dependency - uid: optuartdma -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/bfin/TLL6527M/console/console.c -- bsps/bfin/TLL6527M/start/bspstart.c -- bsps/bfin/TLL6527M/start/interrupt.c -- bsps/bfin/shared/cache/cache.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/optconbaud.yml b/spec/build/bsps/bfin/TLL6527M/optconbaud.yml deleted file mode 100644 index 1c64f99a2e..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/optconbaud.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 9600 -description: | - The baudrate of the console uart. -enabled-by: true -format: '{}' -links: [] -name: CONSOLE_BAUDRATE -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/optconirq.yml b/spec/build/bsps/bfin/TLL6527M/optconirq.yml deleted file mode 100644 index fe608331a6..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/optconirq.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 1 -description: | - The console driver can operate in either polled or interrupt mode. -enabled-by: true -format: '{}' -links: [] -name: CONSOLE_USE_INTERRUPTS -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/optirqtbl.yml b/spec/build/bsps/bfin/TLL6527M/optirqtbl.yml deleted file mode 100644 index f7f03482c3..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/optirqtbl.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: true -description: | - Select if INTERRUPT use table or link list -enabled-by: true -links: [] -name: INTERRUPT_USE_TABLE -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/optskyeye.yml b/spec/build/bsps/bfin/TLL6527M/optskyeye.yml deleted file mode 100644 index 0dde0e0607..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/optskyeye.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - (BSP--Skyeye) If defined, disable features which are not supported on Skyeye. -enabled-by: true -links: [] -name: BFIN_ON_SKYEYE -type: build diff --git a/spec/build/bsps/bfin/TLL6527M/optuartdma.yml b/spec/build/bsps/bfin/TLL6527M/optuartdma.yml deleted file mode 100644 index 29e4a3cc1f..0000000000 --- a/spec/build/bsps/bfin/TLL6527M/optuartdma.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: true -description: | - The uart driver can operate in dma mode with interrupts. Set to 1 if DMA operation is required -enabled-by: true -links: [] -name: UART_USE_DMA -type: build diff --git a/spec/build/bsps/bfin/bf537Stamp/abi.yml b/spec/build/bsps/bfin/bf537Stamp/abi.yml deleted file mode 100644 index 0979b140df..0000000000 --- a/spec/build/bsps/bfin/bf537Stamp/abi.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: [] -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/bfin/bf537Stamp/bspbf537stamp.yml b/spec/build/bsps/bfin/bf537Stamp/bspbf537stamp.yml deleted file mode 100644 index cf21257129..0000000000 --- a/spec/build/bsps/bfin/bf537Stamp/bspbf537stamp.yml +++ /dev/null @@ -1,55 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: bfin -bsp: bf537Stamp -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: bf537Stamp -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/bfin/bf537Stamp/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/bfin/bf537Stamp/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/bfin/bf537Stamp/start/linkcmds -links: -- role: build-dependency - uid: abi -- role: build-dependency - uid: optconirq -- role: build-dependency - uid: optskyeye -- role: build-dependency - uid: start -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: ../obj -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/bfin/bf537Stamp/console/console.c -- bsps/bfin/bf537Stamp/start/bspstart.c -- bsps/bfin/shared/cache/cache.c -- bsps/bfin/shared/interrupt.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/bfin/bf537Stamp/optconirq.yml b/spec/build/bsps/bfin/bf537Stamp/optconirq.yml deleted file mode 100644 index aed1f2cbf5..0000000000 --- a/spec/build/bsps/bfin/bf537Stamp/optconirq.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 0 -description: | - The console driver can operate in either polled or interrupt mode. -enabled-by: true -format: '{}' -links: [] -name: CONSOLE_USE_INTERRUPTS -type: build diff --git a/spec/build/bsps/bfin/bf537Stamp/optskyeye.yml b/spec/build/bsps/bfin/bf537Stamp/optskyeye.yml deleted file mode 100644 index 0dde0e0607..0000000000 --- a/spec/build/bsps/bfin/bf537Stamp/optskyeye.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - (BSP--Skyeye) If defined, disable features which are not supported on Skyeye. -enabled-by: true -links: [] -name: BFIN_ON_SKYEYE -type: build diff --git a/spec/build/bsps/bfin/bf537Stamp/start.yml b/spec/build/bsps/bfin/bf537Stamp/start.yml deleted file mode 100644 index 86f085eb34..0000000000 --- a/spec/build/bsps/bfin/bf537Stamp/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/bfin/bf537Stamp/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/bfin/eZKit533/abi.yml b/spec/build/bsps/bfin/eZKit533/abi.yml deleted file mode 100644 index 0979b140df..0000000000 --- a/spec/build/bsps/bfin/eZKit533/abi.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: [] -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/bfin/eZKit533/bspezkit533.yml b/spec/build/bsps/bfin/eZKit533/bspezkit533.yml deleted file mode 100644 index d8482b7557..0000000000 --- a/spec/build/bsps/bfin/eZKit533/bspezkit533.yml +++ /dev/null @@ -1,56 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: bfin -bsp: eZKit533 -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: eZKit533 -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/bfin/eZKit533/include/bsp.h - - bsps/bfin/eZKit533/include/cplb.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/bfin/eZKit533/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/bfin/eZKit533/start/linkcmds -links: -- role: build-dependency - uid: abi -- role: build-dependency - uid: optconirq -- role: build-dependency - uid: optskyeye -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: ../obj -- role: build-dependency - uid: ../start -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/bfin/eZKit533/console/console-io.c -- bsps/bfin/eZKit533/start/bspstart.c -- bsps/bfin/shared/cache/cache.c -- bsps/bfin/shared/interrupt.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/bfin/eZKit533/optconirq.yml b/spec/build/bsps/bfin/eZKit533/optconirq.yml deleted file mode 100644 index aed1f2cbf5..0000000000 --- a/spec/build/bsps/bfin/eZKit533/optconirq.yml +++ /dev/null @@ -1,17 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-integer: null -- define: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: 0 -description: | - The console driver can operate in either polled or interrupt mode. -enabled-by: true -format: '{}' -links: [] -name: CONSOLE_USE_INTERRUPTS -type: build diff --git a/spec/build/bsps/bfin/eZKit533/optskyeye.yml b/spec/build/bsps/bfin/eZKit533/optskyeye.yml deleted file mode 100644 index 0dde0e0607..0000000000 --- a/spec/build/bsps/bfin/eZKit533/optskyeye.yml +++ /dev/null @@ -1,16 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-boolean: null -- define-condition: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: false -description: | - (BSP--Skyeye) If defined, disable features which are not supported on Skyeye. -enabled-by: true -links: [] -name: BFIN_ON_SKYEYE -type: build diff --git a/spec/build/bsps/bfin/grp.yml b/spec/build/bsps/bfin/grp.yml deleted file mode 100644 index 49e4176c1a..0000000000 --- a/spec/build/bsps/bfin/grp.yml +++ /dev/null @@ -1,49 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: group -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: true -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/bfin/include/bf52x.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/bfin/include/bsp/interrupt.h -- destination: ${BSP_INCLUDEDIR}/libcpu - source: - - bsps/bfin/include/libcpu/bf533.h - - bsps/bfin/include/libcpu/bf537.h - - bsps/bfin/include/libcpu/cecRegs.h - - bsps/bfin/include/libcpu/coreTimerRegs.h - - bsps/bfin/include/libcpu/dmaRegs.h - - bsps/bfin/include/libcpu/ebiuRegs.h - - bsps/bfin/include/libcpu/ethernet.h - - bsps/bfin/include/libcpu/ethernetRegs.h - - bsps/bfin/include/libcpu/gpioRegs.h - - bsps/bfin/include/libcpu/interrupt.h - - bsps/bfin/include/libcpu/memoryRegs.h - - bsps/bfin/include/libcpu/mmu.h - - bsps/bfin/include/libcpu/mmuRegs.h - - bsps/bfin/include/libcpu/ppiRegs.h - - bsps/bfin/include/libcpu/rtcRegs.h - - bsps/bfin/include/libcpu/sicRegs.h - - bsps/bfin/include/libcpu/spi.h - - bsps/bfin/include/libcpu/spiRegs.h - - bsps/bfin/include/libcpu/sport.h - - bsps/bfin/include/libcpu/sportRegs.h - - bsps/bfin/include/libcpu/timerRegs.h - - bsps/bfin/include/libcpu/twi.h - - bsps/bfin/include/libcpu/twiRegs.h - - bsps/bfin/include/libcpu/uart.h - - bsps/bfin/include/libcpu/uartRegs.h - - bsps/bfin/include/libcpu/wdogRegs.h -ldflags: [] -links: [] -type: build -use-after: [] -use-before: [] diff --git a/spec/build/bsps/bfin/obj.yml b/spec/build/bsps/bfin/obj.yml deleted file mode 100644 index e1ad00120a..0000000000 --- a/spec/build/bsps/bfin/obj.yml +++ /dev/null @@ -1,21 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: objects -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: true -includes: [] -install: [] -links: [] -source: -- bsps/bfin/shared/dev/clock.c -- bsps/bfin/shared/dev/rtc.c -- bsps/bfin/shared/dev/spi.c -- bsps/bfin/shared/dev/sport.c -- bsps/bfin/shared/dev/timer.c -- bsps/bfin/shared/dev/twi.c -- bsps/bfin/shared/dev/uart.c -- bsps/bfin/shared/mmu.c -type: build diff --git a/spec/build/bsps/bfin/start.yml b/spec/build/bsps/bfin/start.yml deleted file mode 100644 index 557bf8faef..0000000000 --- a/spec/build/bsps/bfin/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/bfin/shared/start/start.S -target: start.o -type: build diff --git a/spec/build/cpukit/cpubfin.yml b/spec/build/cpukit/cpubfin.yml deleted file mode 100644 index b80135092f..0000000000 --- a/spec/build/cpukit/cpubfin.yml +++ /dev/null @@ -1,36 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -build-type: objects -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -cxxflags: [] -enabled-by: -- bfin -includes: [] -install: -- destination: ${BSP_INCLUDEDIR}/machine - source: - - cpukit/score/cpu/bfin/include/machine/elf_machdep.h -- destination: ${BSP_INCLUDEDIR}/rtems - source: - - cpukit/score/cpu/bfin/include/rtems/asm.h -- destination: ${BSP_INCLUDEDIR}/rtems/bfin - source: - - cpukit/score/cpu/bfin/include/rtems/bfin/bf52x.h - - cpukit/score/cpu/bfin/include/rtems/bfin/bf533.h - - cpukit/score/cpu/bfin/include/rtems/bfin/bfin.h -- destination: ${BSP_INCLUDEDIR}/rtems/score - source: - - cpukit/score/cpu/bfin/include/rtems/score/bfin.h - - cpukit/score/cpu/bfin/include/rtems/score/cpu.h - - cpukit/score/cpu/bfin/include/rtems/score/cpu_asm.h - - cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h -links: [] -source: -- cpukit/score/cpu/bfin/bfin-exception-frame-print.c -- cpukit/score/cpu/bfin/cpu.c -- cpukit/score/cpu/bfin/cpu_asm.S -- cpukit/score/cpu/no_cpu/cpucounterfrequency.c -- cpukit/score/cpu/no_cpu/cpucounterread.c -type: build diff --git a/spec/build/cpukit/librtemscpu.yml b/spec/build/cpukit/librtemscpu.yml index 4825d9326c..f9ba9cbc85 100644 --- a/spec/build/cpukit/librtemscpu.yml +++ b/spec/build/cpukit/librtemscpu.yml @@ -484,8 +484,6 @@ links: uid: cpuaarch64 - role: build-dependency uid: cpuarm -- role: build-dependency - uid: cpubfin - role: build-dependency uid: cpui386 - role: build-dependency