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arm: Honor cache for Cortex-M7 support

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This commit is contained in:
Sebastian Huber
2016-01-14 08:07:06 +01:00
parent 32521269dc
commit 819a6b35cc
1 changed files with 11 additions and 2 deletions
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13
cpukit/score/cpu/arm/armv7m-exception-handler-set.c
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@@ -5,10 +5,10 @@
*/ */
/* /*
* Copyright (c) 2011 Sebastian Huber. All rights reserved. * Copyright (c) 2011, 2016 Sebastian Huber. All rights reserved.
* *
* embedded brains GmbH * embedded brains GmbH
* Obere Lagerstr. 30 * Dornierstr. 4
* 82178 Puchheim * 82178 Puchheim
* Germany * Germany
* <rtems@embedded-brains.de> * <rtems@embedded-brains.de>
@@ -23,6 +23,7 @@
#endif #endif
#include <rtems/score/armv7m.h> #include <rtems/score/armv7m.h>
#include <rtems/rtems/cache.h>
#ifdef ARM_MULTILIB_ARCH_V7M #ifdef ARM_MULTILIB_ARCH_V7M
@@ -33,6 +34,14 @@ void _ARMV7M_Set_exception_handler(
{ {
if ( _ARMV7M_SCB->vtor [index] != handler ) { if ( _ARMV7M_SCB->vtor [index] != handler ) {
_ARMV7M_SCB->vtor [index] = handler; _ARMV7M_SCB->vtor [index] = handler;
rtems_cache_flush_multiple_data_lines(
&_ARMV7M_SCB->vtor [index],
sizeof(_ARMV7M_SCB->vtor [index])
);
rtems_cache_invalidate_multiple_instruction_lines(
&_ARMV7M_SCB->vtor [index],
sizeof(_ARMV7M_SCB->vtor [index])
);
} }
} }