powerpc: Change interrupt disable implemetation

Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().

At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
This commit is contained in:
Sebastian Huber
2014-02-17 09:23:59 +01:00
parent c2934b96e8
commit 801b5d8032
27 changed files with 46 additions and 90 deletions

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@@ -242,11 +242,7 @@ void bsp_start( void )
/* /*
* Initialize default raw exception handlers. See vectors/vectors_init.c * Initialize default raw exception handlers. See vectors/vectors_init.c
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
printk("CPU: %s\n", get_ppc_cpu_type_name(current_ppc_cpu)); printk("CPU: %s\n", get_ppc_cpu_type_name(current_ppc_cpu));

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@@ -323,11 +323,7 @@ ShowBATS();
/* /*
* Initialize default raw exception hanlders. * Initialize default raw exception hanlders.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
/* /*
* Init MMU block address translation to enable hardware * Init MMU block address translation to enable hardware

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@@ -170,7 +170,6 @@ void bsp_start(void)
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_cache_wb_check = 0; ppc_exc_cache_wb_check = 0;
ppc_exc_initialize( ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_interrupt_stack_start, (uintptr_t) bsp_interrupt_stack_start,
(uintptr_t) bsp_interrupt_stack_size (uintptr_t) bsp_interrupt_stack_size
); );

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@@ -136,7 +136,6 @@ void bsp_start( void)
ppc_exc_cache_wb_check = 0; ppc_exc_cache_wb_check = 0;
#endif #endif
ppc_exc_initialize( ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size() rtems_configuration_get_interrupt_stack_size()
); );

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@@ -206,7 +206,6 @@ void bsp_start( void )
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) intrStack_start, (uintptr_t) intrStack_start,
(uintptr_t) intrStack_size (uintptr_t) intrStack_size
); );

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@@ -114,7 +114,6 @@ void bsp_start(void)
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_initialize( ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) IntrStack_start, (uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start (uintptr_t) intrStack - (uintptr_t) IntrStack_start
); );

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@@ -108,7 +108,6 @@ void bsp_start(void)
/* Initialize exceptions */ /* Initialize exceptions */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
mpc55xx_exc_vector_base mpc55xx_exc_vector_base

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@@ -174,7 +174,6 @@ void bsp_start(void)
/* Initialize exception handler */ /* Initialize exception handler */
/* FIXME: Interrupt stack begin and size */ /* FIXME: Interrupt stack begin and size */
ppc_exc_initialize( ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) IntrStack_start, (uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start (uintptr_t) intrStack - (uintptr_t) IntrStack_start
); );

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@@ -270,11 +270,7 @@ VpdBufRec vpdData [] = {
/* /*
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
printk("CPU 0x%x - rev 0x%x\n", myCpu, myCpuRevision); printk("CPU 0x%x - rev 0x%x\n", myCpu, myCpuRevision);

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@@ -245,11 +245,7 @@ void bsp_start( void )
/* /*
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
/* /*
* Init MMU block address translation to enable hardware * Init MMU block address translation to enable hardware

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@@ -99,7 +99,6 @@ void bsp_start( void )
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
(void *) 0xfff00000 (void *) 0xfff00000

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@@ -94,11 +94,7 @@ void bsp_start( void )
/* /*
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
/* Install default handler for the decrementer exception */ /* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler); sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);

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@@ -110,7 +110,6 @@ void bsp_start(void)
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base bsp_exc_vector_base

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@@ -116,7 +116,6 @@ void qoriq_secondary_cpu_initialize(void)
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) second_cpu->interrupt_stack_low, (uintptr_t) second_cpu->interrupt_stack_low,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base bsp_exc_vector_base

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@@ -194,11 +194,7 @@ void bsp_start( void )
/* /*
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
msr_value = 0x2030; msr_value = 0x2030;
_CPU_MSR_SET( msr_value ); _CPU_MSR_SET( msr_value );

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@@ -232,11 +232,7 @@ void bsp_start( void )
/* /*
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize( ppc_exc_initialize(intrStackStart, intrStackSize);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
boardManufacturer = checkPrepBoardType(&residualCopy); boardManufacturer = checkPrepBoardType(&residualCopy);
if (boardManufacturer != PREP_Motorola) { if (boardManufacturer != PREP_Motorola) {

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@@ -68,7 +68,6 @@ void bsp_start(void)
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
bsp_exc_vector_base bsp_exc_vector_base

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@@ -183,11 +183,7 @@ void bsp_start( void)
rtems_counter_initialize_converter(bsp_time_base_frequency); rtems_counter_initialize_converter(bsp_time_base_frequency);
/* Initialize exception handler */ /* Initialize exception handler */
ppc_exc_initialize( ppc_exc_initialize(interrupt_stack_start, interrupt_stack_size);
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
interrupt_stack_start,
interrupt_stack_size
);
/* Initalize interrupt support */ /* Initalize interrupt support */
bsp_interrupt_initialize(); bsp_interrupt_initialize();

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@@ -95,7 +95,6 @@ void bsp_start( void )
* Initialize default raw exception handlers. * Initialize default raw exception handlers.
*/ */
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) bsp_section_work_begin, (uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size(), rtems_configuration_get_interrupt_stack_size(),
virtex_exc_vector_base virtex_exc_vector_base

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@@ -208,9 +208,7 @@ void bsp_start(void)
intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start); intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
intrStackSize = rtems_configuration_get_interrupt_stack_size(); intrStackSize = rtems_configuration_get_interrupt_stack_size();
ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT, ppc_exc_initialize(intrStackStart, intrStackSize);
intrStackStart,
intrStackSize);
/* Let the user know what parameters we were compiled with */ /* Let the user know what parameters we were compiled with */
printk(" Base/Start End Size\n" printk(" Base/Start End Size\n"

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@@ -228,9 +228,7 @@ void bsp_start(void)
intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start); intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start);
intrStackSize = rtems_configuration_get_interrupt_stack_size(); intrStackSize = rtems_configuration_get_interrupt_stack_size();
ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT, ppc_exc_initialize(intrStackStart, intrStackSize);
intrStackStart,
intrStackSize);
/* Let the user know what parameters we were compiled with */ /* Let the user know what parameters we were compiled with */
printk(" Base/Start End Size\n" printk(" Base/Start End Size\n"

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@@ -68,14 +68,6 @@ void boot_card(
{ {
rtems_interrupt_level bsp_isr_level; rtems_interrupt_level bsp_isr_level;
/*
* Special case for PowerPC: The interrupt disable mask is stored in SPRG0.
* It must be valid before we can use rtems_interrupt_disable().
*/
#ifdef PPC_INTERRUPT_DISABLE_MASK_DEFAULT
ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT );
#endif /* PPC_INTERRUPT_DISABLE_MASK_DEFAULT */
/* /*
* Make sure interrupts are disabled. * Make sure interrupts are disabled.
*/ */

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@@ -149,7 +149,6 @@ static void ppc_exc_fatal_error(void)
} }
void ppc_exc_initialize_with_vector_base( void ppc_exc_initialize_with_vector_base(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin, uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size, uintptr_t interrupt_stack_size,
void *vector_base void *vector_base
@@ -191,8 +190,6 @@ void ppc_exc_initialize_with_vector_base(
PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, interrupt_stack_pointer); PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG1, interrupt_stack_pointer);
PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, interrupt_stack_begin); PPC_SET_SPECIAL_PURPOSE_REGISTER(SPRG2, interrupt_stack_begin);
ppc_interrupt_set_disable_mask(interrupt_disable_mask);
#ifndef PPC_EXC_CONFIG_BOOKE_ONLY #ifndef PPC_EXC_CONFIG_BOOKE_ONLY
/* Use current MMU / RI settings when running C exception handlers */ /* Use current MMU / RI settings when running C exception handlers */

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@@ -361,7 +361,6 @@ rtems_status_code ppc_exc_make_prologue(
* @see ppc_exc_initialize(). * @see ppc_exc_initialize().
*/ */
void ppc_exc_initialize_with_vector_base( void ppc_exc_initialize_with_vector_base(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin, uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size, uintptr_t interrupt_stack_size,
void *vector_base void *vector_base
@@ -381,13 +380,11 @@ void ppc_exc_initialize_with_vector_base(
* - the minimal prologue creation failed. * - the minimal prologue creation failed.
*/ */
static inline void ppc_exc_initialize( static inline void ppc_exc_initialize(
uint32_t interrupt_disable_mask,
uintptr_t interrupt_stack_begin, uintptr_t interrupt_stack_begin,
uintptr_t interrupt_stack_size uintptr_t interrupt_stack_size
) )
{ {
ppc_exc_initialize_with_vector_base( ppc_exc_initialize_with_vector_base(
interrupt_disable_mask,
interrupt_stack_begin, interrupt_stack_begin,
interrupt_stack_size, interrupt_stack_size,
NULL NULL

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@@ -16,6 +16,7 @@ noinst_LIBRARIES = libscorecpu.a
libscorecpu_a_SOURCES = cpu.c libscorecpu_a_SOURCES = cpu.c
libscorecpu_a_SOURCES += ppc-context-volatile-clobber.S libscorecpu_a_SOURCES += ppc-context-volatile-clobber.S
libscorecpu_a_SOURCES += ppc-context-validate.S libscorecpu_a_SOURCES += ppc-context-validate.S
libscorecpu_a_SOURCES += ppc-isr-disable-mask.S
libscorecpu_a_SOURCES += ppc-isr-vector-install.c libscorecpu_a_SOURCES += ppc-isr-vector-install.c
libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)

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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/asm.h>
#include <rtems/score/cpu.h>
.global _PPC_INTERRUPT_DISABLE_MASK
.weak _PPC_INTERRUPT_DISABLE_MASK
.set _PPC_INTERRUPT_DISABLE_MASK, PPC_INTERRUPT_DISABLE_MASK_DEFAULT

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@@ -581,8 +581,8 @@ lidate */
/** /**
* @brief Default value for the interrupt disable mask. * @brief Default value for the interrupt disable mask.
* *
* The interrupt disable mask is stored in the SPRG0 (= special purpose * The interrupt disable mask is stored in the global symbol
* register 272). * _PPC_INTERRUPT_DISABLE_MASK.
*/ */
#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE #define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
@@ -603,25 +603,16 @@ extern "C" {
#define _CPU_MSR_SET( _msr_value ) \ #define _CPU_MSR_SET( _msr_value ) \
{ __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } { __asm__ volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
static inline void ppc_interrupt_set_disable_mask( uint32_t mask ) /**
{ * @brief A global symbol used to disable interrupts in the MSR.
__asm__ volatile ( *
"mtspr 272, %0" * A one bit means that this bit should be cleared.
: */
: "r" (mask) extern char _PPC_INTERRUPT_DISABLE_MASK[];
);
}
static inline uint32_t ppc_interrupt_get_disable_mask( void ) static inline uint32_t ppc_interrupt_get_disable_mask( void )
{ {
uint32_t mask; return (uint32_t) _PPC_INTERRUPT_DISABLE_MASK;
__asm__ volatile (
"mfspr %0, 272"
: "=r" (mask)
);
return mask;
} }
static inline uint32_t ppc_interrupt_disable( void ) static inline uint32_t ppc_interrupt_disable( void )
@@ -631,7 +622,8 @@ static inline uint32_t ppc_interrupt_disable( void )
__asm__ volatile ( __asm__ volatile (
"mfmsr %0;" "mfmsr %0;"
"mfspr %1, 272;" "lis %1, _PPC_INTERRUPT_DISABLE_MASK@h;"
"ori %1, %1, _PPC_INTERRUPT_DISABLE_MASK@l;"
"andc %1, %0, %1;" "andc %1, %0, %1;"
"mtmsr %1" "mtmsr %1"
: "=r" (level), "=r" (mask) : "=r" (level), "=r" (mask)