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bsp/gen83xx: Disable caches in bsp_restart()

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Sebastian Huber
2013-01-18 09:48:38 +01:00
parent 99d11970b6
commit 7f7b09ca2e
1 changed files with 23 additions and 1 deletions
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24
c/src/lib/libbsp/powerpc/gen83xx/startup/bsprestart.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved.
* *
* embedded brains GmbH * embedded brains GmbH
* Obere Lagerstr. 30 * Obere Lagerstr. 30
@@ -13,12 +13,34 @@
*/ */
#include <bsp.h> #include <bsp.h>
#include <bsp/u-boot.h>
#include <libcpu/powerpc-utility.h>
void bsp_restart(void *addr) void bsp_restart(void *addr)
{ {
rtems_interrupt_level level; rtems_interrupt_level level;
void (*start)(void) = addr; void (*start)(void) = addr;
#ifdef HAS_UBOOT
const void *mem_begin = (const void *) bsp_uboot_board_info.bi_memstart;
size_t mem_size = bsp_uboot_board_info.bi_memsize;
#else /* HAS_UBOOT */
const void *mem_begin = bsp_ram_start;
size_t mem_size = (size_t) bsp_ram_size;
#endif /* HAS_UBOOT */
uint32_t hid0;
rtems_interrupt_disable(level); rtems_interrupt_disable(level);
hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0);
if ((hid0 & HID0_DCE) != 0) {
rtems_cache_flush_multiple_data_lines(mem_begin, mem_size);
}
hid0 &= ~(HID0_DCE | HID0_ICE);
PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
(*start)(); (*start)();
} }