B.Robinson MIPS patch

c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c

@@ -0,0 +1,24 @@
+/*
+ *  $Id: interruptmask.c,v 1.0 2006/04/04 05:18:49
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+	uint32_t interrupt_mask;
+
+#ifdef TX49
+	interrupt_mask = 0x00000400;			/* Toshiba TX49 processors have a non-standard interrupt mask */
+#else
+	interrupt_mask = 0x0000fc00;
+#endif
+
+	return(interrupt_mask);
+}

c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c

@@ -24,17 +24,18 @@ static const char *cause_strings[32] =
   /*  5 */ "Address Store",
   /*  6 */ "Instruction Bus Error",
   /*  7 */ "Data Bus Error",
-  /*  9 */ "Syscall",
-  /* 10 */ "Breakpoint",
-  /* 11 */ "Reserved Instruction",
-  /* 12 */ "Coprocessor Unuseable",
-  /* 13 */ "Overflow",
-  /* 14 */ "Trap",
-  /* 15 */ "Instruction Virtual Coherency Error",
-  /* 16 */ "FP Exception",
+  /*  8 */ "Syscall",
+  /*  9 */ "Breakpoint",
+  /* 10 */ "Reserved Instruction",
+  /* 11 */ "Coprocessor Unuseable",
+  /* 12 */ "Overflow",
+  /* 13 */ "Trap",
+  /* 14 */ "Instruction Virtual Coherency Error",
+  /* 15 */ "FP Exception",
+  /* 16 */ "Reserved 16",
   /* 17 */ "Reserved 17",
-  /* 18 */ "Reserved 17",
-  /* 19 */ "Reserved 17",
+  /* 18 */ "Reserved 18",
+  /* 19 */ "Reserved 19",
   /* 20 */ "Reserved 20",
   /* 21 */ "Reserved 21",
   /* 22 */ "Reserved 22",