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2000-05-24 Joel Sherrill <joel@OARcorp.com>

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* mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c,
	r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c,
	tx39/include/tx3904.h: All exceptions were given low numbers and thus
	can be now be installed and processed in a uniform manner just like interrupts.
	Variances between various MIPS ISA levels are not accounted for at this time.
	* mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c,
	r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c,
	tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c,
	shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the
	shared maxvectors.c into a variety of CPU model specific versions to simplify
	the build process and reduce depdencies.  Deleted shared/interrupts/maxvectors.c
	and created various CPU model versions.
This commit is contained in:
Joel Sherrill
2001-05-24 19:54:22 +00:00
parent 6937dfd6aa
commit 7c05d2806c
14 changed files with 306 additions and 331 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libcpu/mips/shared/interrupts/Makefile.am
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@@ -6,7 +6,7 @@ AUTOMAKE_OPTIONS = foreign 1.4
PGM = $(ARCH)/interrupts.rel
C_FILES = installisrentries.c maxvectors.c
C_FILES = installisrentries.c vectorexceptions.c
S_FILES = isr_entries.S

47
c/src/lib/libcpu/mips/shared/interrupts/maxvectors.c
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@@ -1,47 +0,0 @@
/*
* This file contains the maximum number of vectors. This can not
* be determined without knowing the RTEMS CPU model.
*
* COPYRIGHT (c) 1989-2000.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/*
* The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
* on-CPU interrupt controller so that these four bits map to 16
* unique interrupts. So you have: 2 software interrupts, an NMI,
* and 16 others.
*/
#if defined(TX39)
#define MAX_VECTORS 19
#endif
/*
* The Synova Mongoose-V attached one of the eight interrupt bits
* to a Peripheral Function Interrupt Cause Register on-CPU.
* This results in: 2 software interrupts, 5 interrupts
* through the IP bits, and 32 more from the PFICR. Some of
* these are reserved but for simplicity in processing, we
* reserve slots for those bits anyway.
*
* gdm, 5/14, added 15 more slots so exceptions can be vectored as well.
*/
#if defined(MONGOOSEV)
#define MAX_VECTORS (38+10)
#endif
#ifndef MAX_VECTORS
#define MAX_VECTORS 8
#endif
unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;

115
c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c Normal file
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@@ -0,0 +1,115 @@
/*
* Common Code for Vectoring MIPS Exceptions
*
* The actual decoding of the cause register and vector number assignment
* is CPU model specific.
*
* $Id$
*/
#include <rtems.h>
#include <stdlib.h>
#include "iregdef.h"
#include "idtcpu.h"
#include <bspIo.h>
char *cause_strings[32] =
{
/* 0 */ "Int",
/* 1 */ "TLB Mods",
/* 2 */ "TLB Load",
/* 3 */ "TLB Store",
/* 4 */ "Address Load",
/* 5 */ "Address Store",
/* 6 */ "Instruction Bus Error",
/* 7 */ "Data Bus Error",
/* 9 */ "Syscall",
/* 10 */ "Breakpoint",
/* 11 */ "Reserved Instruction",
/* 12 */ "Coprocessor Unuseable",
/* 13 */ "Overflow",
/* 14 */ "Trap",
/* 15 */ "Instruction Virtual Coherency Error",
/* 16 */ "FP Exception",
/* 17 */ "Reserved 17",
/* 18 */ "Reserved 17",
/* 19 */ "Reserved 17",
/* 20 */ "Reserved 20",
/* 21 */ "Reserved 21",
/* 22 */ "Reserved 22",
/* 23 */ "Watch",
/* 24 */ "Reserved 24",
/* 25 */ "Reserved 25",
/* 26 */ "Reserved 26",
/* 27 */ "Reserved 27",
/* 28 */ "Reserved 28",
/* 29 */ "Reserved 29",
/* 30 */ "Reserved 30",
/* 31 */ "Data Virtual Coherency Error"
};
struct regdef
{
int offset;
char *name;
};
struct regdef dumpregs[]= {
{ R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" },
{ R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" },
{ R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" },
{ R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" },
{ R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" },
{ R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" },
{ R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" },
{ R_EPC,"R_EPC"}, { -1, NULL }
};
void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
{
unsigned int sr;
unsigned int cause;
int i, j;
mips_get_sr( sr );
mips_get_cause( cause );
printk( "Unhandled exception %d\n", exc );
printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause,
cause_strings[(cause >> 2) &0x1f] );
for(i=0; dumpregs[i].offset > -1; i++)
{
printk(" %s", dumpregs[i].name);
for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
printk(" %08X\n", frame->regs[dumpregs[i].offset] );
}
rtems_fatal_error_occurred(1);
}
#define CALL_EXC(_vector,_frame) \
do { \
if ( _ISR_Vector_table[_vector] ) \
(_ISR_Vector_table[_vector])(_vector,_frame); \
else \
mips_default_exception_code_handler( _vector, _frame ); \
} while(0)
/*
* There are constants defined for these but they should basically
* all be close to the same set.
*/
void mips_vector_exceptions( CPU_Interrupt_frame *frame )
{
unsigned32 cause;
unsigned32 exc;
mips_get_cause( cause );
exc = (cause >> 2) & 0x1f;
CALL_EXC( exc, frame );
}