forked from Imagelibrary/rtems
bsp/mpc5200: Change SDRAM initialization
Change SDRAM initialization according to application note AN3221.
This commit is contained in:
Sebastian Huber
@@ -146,9 +146,9 @@
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.set ADREN_CS1_EN, (1 << (31 - 14))
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.set ADREN_WSE, (1 << (31 - 31))
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.set CTRL_PRECHARGE, (1<<1)
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.set CTRL_REFRESH, (1<<2)
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.set CTRL_BA1, (1<<31)
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.set CTRL_PRECHARGE_ALL, (1 << (31 - 30))
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.set CTRL_REFRESH, (1 << (31 - 29))
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.set CTRL_MODE_EN, (1 << (31 - 0))
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.set CSCONF_CE, (1<<12)
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@@ -496,6 +496,8 @@ twiddle:
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#if defined(NEED_LOW_LEVEL_INIT)
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SDRAM_init:
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mflr r12
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#if defined(MPC5200_BOARD_BRS5L)
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/* set GPIO_WKUP7 pin low for 66MHz buffering */
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/* or high for 133MHz registered buffering */
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@@ -526,65 +528,116 @@ SDRAM_init:
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#define SDELAY_VAL 0x00000004
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/*
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* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4
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* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2
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*/
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#define CFG1_VAL 0xC4222600
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/* Refr.2No-Read delay=0x06, Write latency=0x0 */
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/* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
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/* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
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#define CFG2_VAL 0xCCC70004
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#if defined(MPC5200_BOARD_BRS5L)
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/* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
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/* Refresh counter=0xFFFF */
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#define CTRL_VAL 0xD1470000
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#else
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/* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
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/* Refresh counter=0xFFFF */
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#define CTRL_VAL 0xD04F0000
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#endif
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/* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
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#define MODE_VAL 0x008D0000
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/* SDRAM initialization according to application note AN3221 */
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/* SDRAM controller setup */
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LWI r3, SDELAY_VAL
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stw r3, SDELAY(r31)
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LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
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stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
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/* Refr.2No-Read delay=0x06, Write latency=0x0 */
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LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
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stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
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LWI r3, CFG1_VAL
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stw r3, CFG1(r31)
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#ifdef MPC5200_BOARD_BRS5L
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LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
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stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
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LWI r3, CFG2_VAL
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stw r3, CFG2(r31)
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LWI r11, CTRL_VAL
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stw r11, CTRL(r31)
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lwz r3, CTRL(r31)
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#else
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LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
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stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
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/* Perform a PRECHARGE ALL command */
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ori r3, r11, CTRL_PRECHARGE_ALL
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stw r3, CTRL(r31)
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lwz r3, CTRL(r31)
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/* Wait at least tRP time */
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li r3, 15
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bl ndelay
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#if defined(EMODE_VAL)
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/* Write EMODE register */
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LWI r3, EMODE_VAL
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stw r3, MOD(r31)
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/* Wait at least tMRD time */
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li r3, 10
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bl ndelay
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#endif
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lwz r30, CTRL(r31)
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/* Write MODE register */
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LWI r3, MODE_VAL
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stw r3, MOD(r31)
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SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
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stw r30, CTRL(r31)
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/* Wait at least tMRD time */
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li r3, 10
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bl ndelay
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/* Perform a PRECHARGE ALL command */
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ori r3, r11, CTRL_PRECHARGE_ALL
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stw r3, CTRL(r31)
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lwz r3, CTRL(r31)
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stw r30, CTRL(r31)
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/* Wait at least tRP time */
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li r3, 15
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bl ndelay
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/* Perform an AUTO REFRESH */
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ori r3, r11, CTRL_REFRESH
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stw r3, CTRL(r31)
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lwz r3, CTRL(r31)
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/* Wait at least tRFC time */
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li r3, 70
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bl ndelay
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lwz r30, CTRL(r31)
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/* Perform an AUTO REFRESH */
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ori r3, r11, CTRL_REFRESH
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stw r3, CTRL(r31)
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lwz r3, CTRL(r31)
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/* Wait at least tRFC time */
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li r3, 70
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bl ndelay
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SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
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stw r30, CTRL(r31)
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stw r30, CTRL(r31)
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LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
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stw r30, MOD(r31)
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lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
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CLRBITS r30, r29, CTRL_BA1
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stw r30, CTRL(r31)
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#if defined(SECOND_MODE_VAL)
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/* Write MODE register */
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LWI r3, SECOND_MODE_VAL
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stw r3, MOD(r31)
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#endif
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/* Disable MODE register access */
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lis r4, CTRL_MODE_EN@h
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andc r3, r11, r4
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stw r3, CTRL(r31)
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lwz r3, CTRL(r31)
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mtlr r12
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blr
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copy_image:
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mr r27, r28
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srwi r28, r28, 2
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@@ -901,3 +954,20 @@ XLB_init:
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stw r30, ARBDATTO(r31) /* Set ARBDATTO */
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blr
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ndelay:
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/*
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* The maximum core frequency is 396MHz.
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* We have (396MHz * 1024) / 10**9 == 405.
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*/
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mulli r3, r3, 405
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srwi. r3, r3, 10
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beqlr
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mtctr r3
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ndelay_loop:
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bdnz ndelay_loop
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blr
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