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Part of the automake VI patch from Ralf Corsepius <corsepiu@faw.uni-ulm.de>:

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> 4) rtems-rc-19990202-0.diff /reorg-score-cpu.sh
>
> reorg-score-cpu.sh reorganizes the cpu/<cpu>/* subdirectories in a
> similar manner than previous reorg scripts did. rtems-rc-19990202-0.diff
> contains the diffs after reorg-score-cpu.sh has been run on a
> rtems-19981215 snapshot + my patches up to rtems-rc-19990131-2.diff.
>
> This patch is rather nasty and may break something. However, I've tested
> it for about 10 different target/bsp pairs and believe to have shaken
> out most bugs.

I wonder about the following .h files that were not moved:

a29k/asm.h
a29k/cpu_asm.h
i386/asm.h
i960/asm.h
m68k/asm.h
m68k/m68302.h
m68k/m68360.h
m68k/qsm.h
m68k/sim.h
mips64orion/asm.h
mips64orion/cpu_asm.h
mips64orion/mips64orion.h
no_cpu/asm.h
no_cpu/cpu_asm.h
powerpc/asm.h
powerpc/mpc860.h
sh/asm.h
sparc/asm.h
sparc/erc32.h
This commit is contained in:
Joel Sherrill
1999-02-18 18:28:24 +00:00
parent 52b0d9dd52
commit 7908ba5b81
121 changed files with 30521 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
c/src/exec/score/cpu/a29k/rtems/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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c/src/exec/score/cpu/a29k/rtems/score/Makefile.in Normal file
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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h a29k.h a29ktypes.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

59
c/src/exec/score/cpu/a29k/rtems/score/a29k.h Normal file
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/* a29k.h
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
*/
/* @(#)a29k.h 10/21/96 1.3 */
#ifndef _INCLUDE_A29K_h
#define _INCLUDE_A29K_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "no cpu"
* family when executing in protected mode. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*/
#if defined(a29205)
#define CPU_MODEL_NAME "a29205"
#define A29K_HAS_FPU 0
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "AMD 29K"
/*
* Some bits in the CPS:
*/
#define TD 0x20000
#define DI 0x00002
#ifdef __cplusplus
}
#endif
#endif /* ! _INCLUDE_A29K_h */
/* end of include file */

57
c/src/exec/score/cpu/a29k/rtems/score/a29ktypes.h Normal file
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/* no_cputypes.h
*
* This include file contains type definitions pertaining to the Intel
* no_cpu processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __NO_CPU_TYPES_h
#define __NO_CPU_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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c/src/exec/score/cpu/a29k/rtems/score/cpu.h Normal file
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/* cpu.h
*
* This include file contains information pertaining to the AMD 29K
* processor.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)cpu.h 10/21/96 1.11 */
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/a29k.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/a29ktypes.h>
#endif
extern unsigned int a29k_disable( void );
extern void a29k_enable( unsigned int cookie );
extern unsigned int a29k_getops( void );
extern void a29k_getops_sup( void );
extern void a29k_disable_sup( void );
extern void a29k_enable_sup( void );
extern void a29k_disable_all( void );
extern void a29k_disable_all_sup( void );
extern void a29k_enable_all( void );
extern void a29k_enable_all_sup( void );
extern void a29k_halt( void );
extern void a29k_fatal_error( unsigned32 error );
extern void a29k_as70( void );
extern void a29k_super_mode( void );
extern void a29k_context_switch_sup(void);
extern void a29k_context_restore_sup(void);
extern void a29k_context_save_sup(void);
extern void a29k_sigdfl_sup(void);
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH TRUE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/*
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.
* If FALSE, then no installation is performed.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/*
* Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
* If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization.
*
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* If there is a FP coprocessor such as the i387 or mc68881, then
* the answer is TRUE.
*
* The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#if ( A29K_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#else
#define CPU_HARDWARE_FP FALSE
#endif
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
* must be provided and is the default IDLE thread body instead of
* _Internal_threads_Idle_thread_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
#define CPU_STACK_GROWS_UP FALSE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
#define CPU_STRUCTURE_ALIGNMENT
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*
*/
#error "Check these definitions!!!"
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
typedef struct {
unsigned32 signal;
unsigned32 gr1;
unsigned32 rab;
unsigned32 PC0;
unsigned32 PC1;
unsigned32 PC2;
unsigned32 CHA;
unsigned32 CHD;
unsigned32 CHC;
unsigned32 ALU;
unsigned32 OPS;
unsigned32 tav;
unsigned32 lr1;
unsigned32 rfb;
unsigned32 msp;
unsigned32 FPStat0;
unsigned32 FPStat1;
unsigned32 FPStat2;
unsigned32 IPA;
unsigned32 IPB;
unsigned32 IPC;
unsigned32 Q;
unsigned32 gr96;
unsigned32 gr97;
unsigned32 gr98;
unsigned32 gr99;
unsigned32 gr100;
unsigned32 gr101;
unsigned32 gr102;
unsigned32 gr103;
unsigned32 gr104;
unsigned32 gr105;
unsigned32 gr106;
unsigned32 gr107;
unsigned32 gr108;
unsigned32 gr109;
unsigned32 gr110;
unsigned32 gr111;
unsigned32 gr112;
unsigned32 gr113;
unsigned32 gr114;
unsigned32 gr115;
unsigned32 gr116;
unsigned32 gr117;
unsigned32 gr118;
unsigned32 gr119;
unsigned32 gr120;
unsigned32 gr121;
unsigned32 gr122;
unsigned32 gr123;
unsigned32 gr124;
unsigned32 local_count;
unsigned32 locals[128];
} Context_Control;
typedef struct {
double some_float_register;
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the XXX processor specific parameters.
*
* NOTE: The interrupt_stack_size field is required if
* CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
*
* The pretasking_hook, predriver_hook, and postdriver_hook,
* and the do_zero_of_workspace fields are required on ALL CPUs.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_system_initialization_stack;
unsigned32 some_other_cpu_dependent_info;
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
EXTERN Context_Control_fp _CPU_Null_fp_context;
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
EXTERN void *_CPU_Interrupt_stack_low;
EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* system initialization thread. Remember that in a multiprocessor
* system the system intialization thread becomes the MP server thread.
*/
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*/
#define CPU_STACK_MINIMUM_SIZE (8192)
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 4
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT 0
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _isr_cookie ) \
do{ _isr_cookie = a29k_disable(); }while(0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _isr_cookie ) \
do{ a29k_enable(_isr_cookie) ; }while(0)
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
do{ \
_CPU_ISR_Enable( _isr_cookie ); \
_CPU_ISR_Disable( _isr_cookie ); \
}while(0)
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*/
#define _CPU_ISR_Set_level( new_level ) \
do{ \
if ( new_level ) a29k_disable_all(); \
else a29k_enable_all(); \
}while(0);
/* end of ISR handler macros */
/* Context handler macros */
extern void _CPU_Context_save(
Context_Control *new_context
);
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \
unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \
unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \
_mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \
_reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \
_CPU_Context_save(_the_context); \
(_the_context)->msp = _mem_stack_tmp; /* gr125 */ \
(_the_context)->lr1 = \
(_the_context)->locals[1] = \
(_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \
(_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \
(_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \
(_the_context)->local_count = 1-1; \
(_the_context)->PC1 = _entry_point; \
(_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \
if (_isr) { (_the_context)->OPS |= (TD | DI); } \
else \
{ (_the_context)->OPS &= ~(TD | DI); } \
}while(0)
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) )
/*
* The purpose of this macro is to allow the initial pointer into
* a floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (char *) (_base) + (_offset) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
*/
#define _CPU_Context_Initialize_fp( _destination ) \
do { \
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
} while(0)
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*/
#define _CPU_Fatal_halt( _error ) \
a29k_fatal_error(_error)
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
(_output) = 0; /* do something to prevent warnings */ \
}
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)()
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Internal_threads_Idle_thread_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Internal_threads_Idle_thread_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: May be unnecessary to reload some registers.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
* This version will work on any processor, but if there is a better
* way for your CPU PLEASE use it. The most common way to do this is to:
*
* swap least significant two bytes with 16-bit rotate
* swap upper and lower 16-bits
* swap most significant two bytes with 16-bit rotate
*
* Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is
* that interrupts would probably have to be disabled to insure that
* an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code
* will be fetched incorrectly.
*/
#define CPU_swap_u32( value ) \
((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \
(((value >> 16)&0xff) << 8) | ((value>>24)&0xff)
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#ifdef __cplusplus
}
#endif
#endif

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/* no_cputypes.h
*
* This include file contains type definitions pertaining to the Intel
* no_cpu processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __NO_CPU_TYPES_h
#define __NO_CPU_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
BUILT_SOURCES = offsets.h
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h hppa.h cpu_asm.h hppatypes.h
H_FILES=$(H_PIECES:%=$(srcdir)/%) offsets.h
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
offsets.h: $(GENOFFSETS) cpu.h
$(RM) $@
$(GENOFFSETS) > $@
$(CHMOD) -w $@
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the HP
* PA-RISC processor (Level 1.1).
*
* COPYRIGHT (c) 1994 by Division Incorporated
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Note:
* This file is included by both C and assembler code ( -DASM )
*
* $Id$
*/
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/hppa.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/hppatypes.h>
#endif
/* conditional compilation parameters */
#define CPU_INLINE_ENABLE_DISPATCH FALSE
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* RTEMS manages an interrupt stack in software for the HPPA.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* HPPA has hardware FP, it is assumed to exist by GCC so all tasks
* may implicitly use it (especially for integer multiplies). Because
* the FP context is technically part of the basic integer context
* on this CPU, we cannot use the deferred FP context switch algorithm.
*/
#define CPU_HARDWARE_FP TRUE
#define CPU_ALL_TASKS_ARE_FP TRUE
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_USE_DEFERRED_FP_SWITCH FALSE
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_STACK_GROWS_UP TRUE
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32)))
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/* constants */
#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
/*
* PSW contstants
*/
#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I)
#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE)
#define CPU_PSW_DEFAULT CPU_PSW_BASE
#ifndef ASM
/*
* Contexts
*
* This means we have the following context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
*
* The PA-RISC is very fast so the expense of saving an extra register
* or two is not of great concern at the present. So we are not making
* a distinction between what is saved during a task switch and what is
* saved at each interrupt. Plus saving the entire context should make
* it easier to make gdb aware of RTEMS tasks.
*/
typedef struct {
unsigned32 flags; /* whatever */
unsigned32 gr1; /* scratch -- caller saves */
unsigned32 gr2; /* RP -- return pointer */
unsigned32 gr3; /* scratch -- callee saves */
unsigned32 gr4; /* scratch -- callee saves */
unsigned32 gr5; /* scratch -- callee saves */
unsigned32 gr6; /* scratch -- callee saves */
unsigned32 gr7; /* scratch -- callee saves */
unsigned32 gr8; /* scratch -- callee saves */
unsigned32 gr9; /* scratch -- callee saves */
unsigned32 gr10; /* scratch -- callee saves */
unsigned32 gr11; /* scratch -- callee saves */
unsigned32 gr12; /* scratch -- callee saves */
unsigned32 gr13; /* scratch -- callee saves */
unsigned32 gr14; /* scratch -- callee saves */
unsigned32 gr15; /* scratch -- callee saves */
unsigned32 gr16; /* scratch -- callee saves */
unsigned32 gr17; /* scratch -- callee saves */
unsigned32 gr18; /* scratch -- callee saves */
unsigned32 gr19; /* scratch -- caller saves */
unsigned32 gr20; /* scratch -- caller saves */
unsigned32 gr21; /* scratch -- caller saves */
unsigned32 gr22; /* scratch -- caller saves */
unsigned32 gr23; /* argument 3 */
unsigned32 gr24; /* argument 2 */
unsigned32 gr25; /* argument 1 */
unsigned32 gr26; /* argument 0 */
unsigned32 gr27; /* DP -- global data pointer */
unsigned32 gr28; /* return values -- caller saves */
unsigned32 gr29; /* return values -- caller saves */
unsigned32 sp; /* gr30 */
unsigned32 gr31;
/* Various control registers */
unsigned32 sar; /* cr11 */
unsigned32 ipsw; /* cr22; full 32 bits of psw */
unsigned32 iir; /* cr19; interrupt instruction register */
unsigned32 ior; /* cr21; interrupt offset register */
unsigned32 isr; /* cr20; interrupt space register (not used) */
unsigned32 pcoqfront; /* cr18; front que offset */
unsigned32 pcoqback; /* cr18; back que offset */
unsigned32 pcsqfront; /* cr17; front que space (not used) */
unsigned32 pcsqback; /* cr17; back que space (not used) */
unsigned32 itimer; /* cr16; itimer value */
} Context_Control;
/* Must be double word aligned.
* This will be ok since our allocator returns 8 byte aligned chunks
*/
typedef struct {
double fr0; /* status */
double fr1; /* exception information */
double fr2; /* exception information */
double fr3; /* exception information */
double fr4; /* argument */
double fr5; /* argument */
double fr6; /* argument */
double fr7; /* argument */
double fr8; /* scratch -- caller saves */
double fr9; /* scratch -- caller saves */
double fr10; /* scratch -- caller saves */
double fr11; /* scratch -- caller saves */
double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */
double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */
double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */
} Context_Control_fp;
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt.
*/
typedef struct {
Context_Control Integer;
Context_Control_fp Floating_Point;
} CPU_Interrupt_frame;
/*
* Our interrupt handlers take a 2nd argument:
* a pointer to a CPU_Interrupt_frame
* So we use our own prototype instead of rtems_isr_entry
*/
typedef void ( *hppa_rtems_isr_entry )(
unsigned32,
CPU_Interrupt_frame *
);
/*
* The following table contains the information required to configure
* the HPPA specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void * );
/* end of fields required on all CPUs */
hppa_rtems_isr_entry spurious_handler;
unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */
} rtems_cpu_table;
/* variables */
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
SCORE_EXTERN unsigned32 _CPU_Default_gr27;
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
#endif /* ! ASM */
/*
* context sizes
*/
#ifndef ASM
#define CPU_CONTEXT_SIZE sizeof( Context_Control )
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
#endif
/*
* size of a frame on the stack
*/
#define CPU_FRAME_SIZE (16 * 4)
/*
* (Optional) # of bytes for libmisc/stackchk to check
* If not specifed, then it defaults to something reasonable
* for most architectures.
*/
#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2)
/*
* extra stack required by the MPCI receive server thread
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* HPPA has 32 traps, then 32 external interrupts
* Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
* The BSP is aware of the external interrupts and possibly more.
*
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS)
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Don't be chintzy here; we don't want to debug these problems
* Some of the tests eat almost 4k.
* Plus, the HPPA always allocates chunks of 64 bytes for stack
* growth.
*/
#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
/*
* HPPA double's must be on 8 byte boundary
*/
#define CPU_ALIGNMENT 8
/*
* just follow the basic HPPA alignment for the heap and partition
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* HPPA stack is best when 64 byte aligned.
*/
#define CPU_STACK_ALIGNMENT 64
#ifndef ASM
/* macros */
/*
* ISR handler macros
*
* These macros perform the following functions:
* + disable all maskable CPU interrupts
* + restore previous interrupt level (enable)
* + temporarily restore interrupts (flash)
* + set a particular level
*/
/* Disable interrupts; returning previous psw bits in _isr_level */
#define _CPU_ISR_Disable( _isr_level ) \
do { \
HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \
if (_isr_level & HPPA_PSW_I) _isr_level = 0; \
else _isr_level = 1; \
} while(0)
/* Enable interrupts to previous level from _CPU_ISR_Disable
* does not change 'level' */
#define _CPU_ISR_Enable( _isr_level ) \
{ \
register int _ignore; \
if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
}
/* restore, then disable interrupts; does not change level */
#define _CPU_ISR_Flash( _isr_level ) \
{ \
if (_isr_level == 0) \
{ \
register int _ignore; \
HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
} \
}
/*
* Interrupt task levels
*
* Future scheme proposal
* level will be an index into a array.
* Each entry of array will be the interrupt bits
* enabled for that level. There will be 32 bits of external
* interrupts (to be placed in EIEM) and some (optional) bsp
* specific bits
*
* For pixel flow this *may* mean something like:
* level 0: all interrupts enabled (external + rhino)
* level 1: rhino disabled
* level 2: all io interrupts disabled (timer still enabled)
* level 7: *ALL* disabled (timer disabled)
*/
/* set interrupts on or off; does not return new level */
#define _CPU_ISR_Set_level( new_level ) \
{ \
volatile int ignore; \
if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
}
/* return current level */
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/*
* Context handler macros
*
* These macros perform the following functions:
* + initialize a context area
* + restart the current thread
* + calculate the initial pointer into a FP context area
* + initialize an FP context area
*
* HPPA port adds two macros which hide the "indirectness" of the
* pointer passed the save/restore FP context assembly routines.
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_new_level, _entry_point, _is_fp ) \
do { \
unsigned32 _stack; \
\
(_the_context)->flags = 0xfeedf00d; \
(_the_context)->pcoqfront = (unsigned32)(_entry_point); \
(_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \
(_the_context)->pcsqfront = 0; \
(_the_context)->pcsqback = 0; \
if ( (_new_level) ) \
(_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
else \
(_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
\
_stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
_stack &= ~(CPU_STACK_ALIGNMENT - 1); \
if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
_stack += CPU_FRAME_SIZE; \
\
(_the_context)->sp = (_stack); \
(_the_context)->gr27 = _CPU_Default_gr27; \
} while (0)
#define _CPU_Context_Restart_self( _the_context ) \
do { \
_CPU_Context_restore( (_the_context) ); \
} while (0)
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
#define _CPU_Context_Initialize_fp( _destination ) \
do { \
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
} while(0)
#define _CPU_Context_save_fp( _fp_context ) \
_CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
#define _CPU_Context_restore_fp( _fp_context ) \
_CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
/* end of Context handler macros */
/*
* Fatal Error manager macros
*
* These macros perform the following functions:
* + disable interrupts and halt the CPU
*/
void hppa_cpu_halt(unsigned32 the_error);
#define _CPU_Fatal_halt( _error ) \
hppa_cpu_halt(_error)
/* end of Fatal Error manager macros */
/*
* Bitfield handler macros
*
* These macros perform the following functions:
* + scan for the highest numbered (MSB) set in a 16 bit bitfield
*
* NOTE:
*
* The HPPA does not have a scan instruction. This functionality
* is implemented in software.
*/
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
int hppa_rtems_ffs(unsigned int value);
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
_output = hppa_rtems_ffs(_value)
/* end of Bitfield handler macros */
/*
* Priority handler macros
*
* These macros perform the following functions:
* + return a mask with the bit for this major/minor portion of
* of thread priority set.
* + translate the bit number returned by "Bitfield_find_first_bit"
* into an index into the thread ready chain bit maps
*
* Note: 255 is the lowest priority
*/
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner and avoid stack conflicts.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Save_float_context
*
* This routine saves the floating point context passed to it.
*
* NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
* which dereferences the pointer before calling this.
*/
void _CPU_Save_float_context(
Context_Control_fp *fp_context
);
/*
* _CPU_Restore_float_context
*
* This routine restores the floating point context passed to it.
*
* NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
* which dereferences the pointer before calling this.
*/
void _CPU_Restore_float_context(
Context_Control_fp *fp_context
);
/*
* The raw interrupt handler for external interrupts
*/
extern void _Generic_ISR_Handler(
void
);
/* The following routine swaps the endian format of an unsigned int.
* It must be static so it can be referenced indirectly.
*/
static inline unsigned int
CPU_swap_u32(unsigned32 value)
{
unsigned32 swapped;
HPPA_ASM_SWAPBYTES(value, swapped);
return( swapped );
}
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#endif /* ! ASM */
#ifdef __cplusplus
}
#endif
#endif /* ! __CPU_h */

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/*
* Copyright (c) 1990,1991 The University of Utah and
* the Center for Software Science (CSS). All rights reserved.
*
* Permission to use, copy, modify and distribute this software is hereby
* granted provided that (1) source code retains these copyright, permission,
* and disclaimer notices, and (2) redistributions including binaries
* reproduce the notices in supporting documentation, and (3) all advertising
* materials mentioning features or use of this software display the following
* acknowledgement: ``This product includes software developed by the Center
* for Software Science at the University of Utah.''
*
* THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF
* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* CSS requests users of this software to return to css-dist@cs.utah.edu any
* improvements that they make and grant CSS redistribution rights.
*
* Utah $Hdr: asm.h 1.6 91/12/03$
*
* $Id$
*/
/*
* Hardware Space Registers
*/
sr0 .reg %sr0
sr1 .reg %sr1
sr2 .reg %sr2
sr3 .reg %sr3
sr4 .reg %sr4
sr5 .reg %sr5
sr6 .reg %sr6
sr7 .reg %sr7
/*
* Control register aliases
*/
rctr .reg %cr0
pidr1 .reg %cr8
pidr2 .reg %cr9
ccr .reg %cr10
sar .reg %cr11
pidr3 .reg %cr12
pidr4 .reg %cr13
iva .reg %cr14
eiem .reg %cr15
itmr .reg %cr16
pcsq .reg %cr17
pcoq .reg %cr18
iir .reg %cr19
isr .reg %cr20
ior .reg %cr21
ipsw .reg %cr22
eirr .reg %cr23
/*
* Calling Convention
*/
rp .reg %r2
arg3 .reg %r23
arg2 .reg %r24
arg1 .reg %r25
arg0 .reg %r26
dp .reg %r27
ret0 .reg %r28
ret1 .reg %r29
sl .reg %r29
sp .reg %r30

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/*
* Description:
*
* Definitions for HP PA Risc
* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
*
* COPYRIGHT (c) 1994 by Division Incorporated
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Note:
* This file is included by both C and assembler code ( -DASM )
*
* $Id$
*/
#ifndef _INCLUDE_HPPA_H
#define _INCLUDE_HPPA_H
#ifdef ASM
#include <rtems/score/targopts.h>
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/*
* This section contains the information required to build
* RTEMS for a particular member of the Hewlett Packard
* PA-RISC family. It does this by setting variables to
* indicate which implementation dependent features are
* present in a particular member of the family.
*/
#if defined(hppa7100)
#define CPU_MODEL_NAME "hppa 7100"
#elif defined(hppa7200)
#define CPU_MODEL_NAME "hppa 7200"
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#if !defined(CPU_NAME)
#define CPU_NAME "HP PA-RISC 1.1"
#endif
/*
* Processor Status Word (PSW) Masks
*/
#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
#define HPPA_PSW_r2 0x20000000 /* reserved */
#define HPPA_PSW_r3 0x10000000 /* reserved */
#define HPPA_PSW_r4 0x08000000 /* reserved */
#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
#define HPPA_PSW_r24 0x00000080 /* reserved */
#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
/* Low-Priority Machine Check */
/* Interruption Enable */
/*
* HPPA traps and interrupts
* basic layout. Note numbers do not denote priority
*
* 0-31 basic traps and interrupts defined by HPPA architecture
* 0-31 32 external interrupts
* 32-... bsp defined
*/
#define HPPA_TRAP_NON_EXISTENT 0
/* group 1 */
#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
/* group 2 */
#define HPPA_TRAP_POWER_FAIL 2
#define HPPA_TRAP_RECOVERY_COUNTER 3
#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
#define HPPA_TRAP_PERFORMANCE_MONITOR 29
/* group 3 */
#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
#define HPPA_TRAP_INSTRUCTION_DEBUG 30
#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
#define HPPA_TRAP_BREAK_INSTRUCTION 9
#define HPPA_TRAP_PRIVILEGED_OPERATION 10
#define HPPA_TRAP_PRIVILEGED_REGISTER 11
#define HPPA_TRAP_OVERFLOW 12
#define HPPA_TRAP_CONDITIONAL 13
#define HPPA_TRAP_ASSIST_EXCEPTION 14
#define HPPA_TRAP_DATA_TLB_MISS 15
#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
#define HPPA_TRAP_DATA_MEMORY_BREAK 19
#define HPPA_TRAP_TLB_DIRTY_BIT 20
#define HPPA_TRAP_PAGE_REFERENCE 21
#define HPPA_TRAP_DATA_DEBUG 31
#define HPPA_TRAP_ASSIST_EMULATION 22
/* group 4 */
#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
#define HPPA_TRAP_TAKEN_BRANCH 25
#define HPPA_INTERNAL_TRAPS 32
/* External Interrupts via interrupt 4 */
#define HPPA_INTERRUPT_EXTERNAL_0 0
#define HPPA_INTERRUPT_EXTERNAL_1 1
#define HPPA_INTERRUPT_EXTERNAL_2 2
#define HPPA_INTERRUPT_EXTERNAL_3 3
#define HPPA_INTERRUPT_EXTERNAL_4 4
#define HPPA_INTERRUPT_EXTERNAL_5 5
#define HPPA_INTERRUPT_EXTERNAL_6 6
#define HPPA_INTERRUPT_EXTERNAL_7 7
#define HPPA_INTERRUPT_EXTERNAL_8 8
#define HPPA_INTERRUPT_EXTERNAL_9 9
#define HPPA_INTERRUPT_EXTERNAL_10 10
#define HPPA_INTERRUPT_EXTERNAL_11 11
#define HPPA_INTERRUPT_EXTERNAL_12 12
#define HPPA_INTERRUPT_EXTERNAL_13 13
#define HPPA_INTERRUPT_EXTERNAL_14 14
#define HPPA_INTERRUPT_EXTERNAL_15 15
#define HPPA_INTERRUPT_EXTERNAL_16 16
#define HPPA_INTERRUPT_EXTERNAL_17 17
#define HPPA_INTERRUPT_EXTERNAL_18 18
#define HPPA_INTERRUPT_EXTERNAL_19 19
#define HPPA_INTERRUPT_EXTERNAL_20 20
#define HPPA_INTERRUPT_EXTERNAL_21 21
#define HPPA_INTERRUPT_EXTERNAL_22 22
#define HPPA_INTERRUPT_EXTERNAL_23 23
#define HPPA_INTERRUPT_EXTERNAL_24 24
#define HPPA_INTERRUPT_EXTERNAL_25 25
#define HPPA_INTERRUPT_EXTERNAL_26 26
#define HPPA_INTERRUPT_EXTERNAL_27 27
#define HPPA_INTERRUPT_EXTERNAL_28 28
#define HPPA_INTERRUPT_EXTERNAL_29 29
#define HPPA_INTERRUPT_EXTERNAL_30 30
#define HPPA_INTERRUPT_EXTERNAL_31 31
#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
#define HPPA_EXTERNAL_INTERRUPTS 32
/* BSP defined interrupts begin here */
#define HPPA_INTERRUPT_MAX 32
/*
* Cache characteristics
*/
#define HPPA_CACHELINE_SIZE 32
#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
/*
* page size characteristics
*/
#define HPPA_PAGE_SIZE 4096
#define HPPA_PAGE_MASK (0xfffff000)
/*
* TLB characteristics
*
* Flags and Access Control layout for using TLB protection insertion
*
* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |?|?|T|D|B|type |PL1|Pl2|U| access id |?|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
*/
/*
* Access rights (type + PL1 + PL2)
*/
#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
/*
* Floating point status register definitions
*/
#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
#define HPPA_FPSTATUS_RM_SHIFT 9
#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
#define HPPA_FPSTATUS_CQ_SHIFT 13
#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
/*
* Inline macros for misc. interesting opcodes
*/
/* generate a global label */
#define HPPA_ASM_LABEL(label) \
asm(".export " label ", ! .label " label);
/* Return From Interrupt RFI */
#define HPPA_ASM_RFI() asm volatile ("rfi")
/* Set System Mask SSM i,t */
#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
: "=r" (gr) \
: "i" (i))
/* Reset System Mask RSM i,t */
#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
: "=r" (gr) \
: "i" (i))
/* Move To System Mask MTSM r */
#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
: : "r" (gr))
/* Load Space Identifier LDSID (s,b),t */
#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (grb))
/*
* Gcc extended asm doesn't really allow for treatment of space registers
* as "registers", so we have to use "i" format.
* Unfortunately this means that the "=" constraint is not available.
*/
/* Move To Space Register MTSP r,sr */
#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
: : "i" (sr), \
"r" (gr))
/* Move From Space Register MFSP sr,t */
#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
: "=r" (gr) \
: "i" (sr))
/* Move To Control register MTCTL r,t */
#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
: : "i" (cr), \
"r" (gr))
/* Move From Control register MFCTL r,t */
#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
: "=r" (gr) \
: "i" (cr))
/* Synchronize caches SYNC */
#define HPPA_ASM_SYNC() asm volatile ("sync")
/* Probe Read Access PROBER (s,b),r,t */
#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
asm volatile ("prober (%1,%2),%3,%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (groff), \
"r" (gracc))
/* Probe Read Access Immediate PROBERI (s,b),i,t*/
#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
asm volatile ("proberi (%1,%2),%3,%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (groff), \
"i" (iacc))
/* Probe Write Access PROBEW (s,b),r,t */
#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
asm volatile ("probew (%1,%2),%3,%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (groff), \
"r" (gracc))
/* Probe Write Access Immediate PROBEWI (s,b),i,t */
#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
asm volatile ("probewi (%1,%2),%3,%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (groff), \
"i" (iacc))
/* Load Physical Address LPA x(s,b),t */
#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
: "=r" (grt) \
: "i" (sr), \
"r" (grb))
/* Load Coherence Index LCI x(s,b),t */
/* AKA: Load Hash Address LHA x(s,b),t */
#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
: "=r" (grt) \
: "r" (grx),\
"i" (sr), \
"r" (grb))
#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
/* Purge Data Tlb PDTLB x(s,b) */
#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Purge Instruction Tlb PITLB x(s,b) */
#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Purge Data Tlb Entry PDTLBE x(s,b) */
#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Purge Instruction Tlb Entry PITLBE x(s,b) */
#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Insert Data TLB Address IDTLBA r,(s,b) */
#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
: : "r" (gr), \
"i" (sr), \
"r" (grb))
/* Insert Instruction TLB Address IITLBA r,(s,b) */
#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
: : "r" (gr), \
"i" (sr), \
"r" (grb))
/* Insert Data TLB Protection IDTLBP r,(s,b) */
#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
: : "r" (gr), \
"i" (sr), \
"r" (grb))
/* Insert Instruction TLB Protection IITLBP r,(s,b) */
#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
: : "r" (gr), \
"i" (sr), \
"r" (grb))
/* Purge Data Cache PDC x(s,b) */
#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Flush Data Cache FDC x(s,b) */
#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Flush Instruction Cache FDC x(s,b) */
#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Flush Data Cache Entry FDCE x(s,b) */
#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Flush Instruction Cache Entry FICE x(s,b) */
#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
: : "r" (grx), \
"i" (sr), \
"r" (grb))
/* Break BREAK i5,i13 */
#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
: : "i" (i5), \
"i" (i13))
/* Load and Clear Word Short LDCWS d(s,b),t */
#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
: "=r" (grt) \
: "i" (i), \
"i" (sr), \
"r" (grb))
/* Load and Clear Word Indexed LDCWX x(s,b),t */
#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
: "=r" (grt) \
: "r" (grx), \
"i" (sr), \
"r" (grb))
/* Load Word Absolute Short LDWAS d(b),t */
/* NOTE: "short" here means "short displacement" */
#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
: "=r" (gr) \
: "i" (disp), \
"r" (grbase))
/* Store Word Absolute Short STWAS r,d(b) */
/* NOTE: "short" here means "short displacement" */
#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
: : "r" (gr), \
"i" (disp), \
"r" (grbase))
/*
* Swap bytes
* REFERENCE: PA72000 TRM -- Appendix C
*/
#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
" shd %1,%1,16,%0 \n\
dep %0,15,8,%0 \n\
shd %1,%0,8,%0" \
: "=r" (swapped) \
: "r" (value) \
)
/* 72000 Diagnose instructions follow
* These macros assume gas knows about these instructions.
* gas2.2.u1 did not.
* I added them to my copy and installed it locally.
*
* There are *very* special requirements for these guys
* ref: TRM 6.1.3 Programming Constraints
*
* The macros below handle the following rules
*
* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
* Must never be nullified (hence the leading nop)
* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
* Instruction preceeding GR_SHDW must not set any of the GR's saved
*
* The macros do *NOT* deal with the following problems
* doubled DIAGNOSE instructions must not straddle a page boundary
* if code translation enabled. (since 2nd could trap on ITLB)
* If you care about DHIT and DPE bits of DR0, then
* No store instruction in the 2 insn window before RDD
*/
/* Move To CPU/DIAG register MTCPU r,t */
#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
" mtcpu %1,%0 \n" \
" mtcpu %1,%0" \
: : "i" (dr), \
"r" (gr))
/* Move From CPU/DIAG register MFCPU r,t */
#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
" mfcpu %1,%0\n" \
" mfcpu %1,%0" \
: "=r" (gr) \
: "i" (dr))
/* Transfer of Control Enable TOC_EN */
#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
" tocen")
/* Transfer of Control Disable TOC_DIS */
#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
" tocdis")
/* Shadow Registers to General Register SHDW_GR */
#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
" shdwgr" \
::: "r1" "r8" "r9" "r16" \
"r17" "r24" "r25")
/* General Registers to Shadow Register GR_SHDW */
#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
" grshdw \n" \
" grshdw")
/*
* Definitions of special registers for use by the above macros.
*/
/* Hardware Space Registers */
#define HPPA_SR0 0
#define HPPA_SR1 1
#define HPPA_SR2 2
#define HPPA_SR3 3
#define HPPA_SR4 4
#define HPPA_SR5 5
#define HPPA_SR6 6
#define HPPA_SR7 7
/* Hardware Control Registers */
#define HPPA_CR0 0
#define HPPA_RCTR 0 /* Recovery Counter Register */
#define HPPA_CR8 8 /* Protection ID 1 */
#define HPPA_PIDR1 8
#define HPPA_CR9 9 /* Protection ID 2 */
#define HPPA_PIDR2 9
#define HPPA_CR10 10
#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
#define HPPA_CR11 11
#define HPPA_SAR 11 /* Shift Amount Register */
#define HPPA_CR12 12
#define HPPA_PIDR3 12 /* Protection ID 3 */
#define HPPA_CR13 13
#define HPPA_PIDR4 13 /* Protection ID 4 */
#define HPPA_CR14 14
#define HPPA_IVA 14 /* Interrupt Vector Address */
#define HPPA_CR15 15
#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
#define HPPA_CR16 16
#define HPPA_ITMR 16 /* Interval Timer */
#define HPPA_CR17 17
#define HPPA_PCSQ 17 /* Program Counter Space queue */
#define HPPA_CR18 18
#define HPPA_PCOQ 18 /* Program Counter Offset queue */
#define HPPA_CR19 19
#define HPPA_IIR 19 /* Interruption Instruction Register */
#define HPPA_CR20 20
#define HPPA_ISR 20 /* Interruption Space Register */
#define HPPA_CR21 21
#define HPPA_IOR 21 /* Interruption Offset Register */
#define HPPA_CR22 22
#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
#define HPPA_CR23 23
#define HPPA_EIRR 23 /* External Interrupt Request */
#define HPPA_CR24 24
#define HPPA_PPDA 24 /* Physcial Page Directory Address */
#define HPPA_TR0 24 /* Temporary register 0 */
#define HPPA_CR25 25
#define HPPA_HTA 25 /* Hash Table Address */
#define HPPA_TR1 25 /* Temporary register 1 */
#define HPPA_CR26 26
#define HPPA_TR2 26 /* Temporary register 2 */
#define HPPA_CR27 27
#define HPPA_TR3 27 /* Temporary register 3 */
#define HPPA_CR28 28
#define HPPA_TR4 28 /* Temporary register 4 */
#define HPPA_CR29 29
#define HPPA_TR5 29 /* Temporary register 5 */
#define HPPA_CR30 30
#define HPPA_TR6 30 /* Temporary register 6 */
#define HPPA_CR31 31
#define HPPA_CPUID 31 /* MP identifier */
/*
* Diagnose registers
*/
#define HPPA_DR0 0
#define HPPA_DR1 1
#define HPPA_DR8 8
#define HPPA_DR24 24
#define HPPA_DR25 25
/*
* Tear apart a break instruction to find its type.
*/
#define HPPA_BREAK5(x) ((x) & 0x1F)
#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
/* assemble a break instruction */
#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13))
/*
* this won't work in ASM or non-GNU compilers
*/
#if !defined(ASM) && defined(__GNUC__)
/*
* static inline utility functions to get at control registers
*/
#define EMIT_GET_CONTROL(name, reg) \
static __inline__ unsigned int \
get_ ## name (void) \
{ \
unsigned int value; \
HPPA_ASM_MFCTL(reg, value); \
return value; \
}
#define EMIT_SET_CONTROL(name, reg) \
static __inline__ void \
set_ ## name (unsigned int new_value) \
{ \
HPPA_ASM_MTCTL(new_value, reg); \
}
#define EMIT_CONTROLS(name, reg) \
EMIT_GET_CONTROL(name, reg) \
EMIT_SET_CONTROL(name, reg)
EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
#endif /* ASM and GNU */
/*
* If and How to invoke the debugger (a ROM debugger generally)
*/
#define CPU_INVOKE_DEBUGGER \
do { \
HPPA_ASM_BREAK(1,1); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* ! _INCLUDE_HPPA_H */

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/* hppatypes.h
*
* This include file contains type definitions pertaining to the Hewlett
* Packard PA-RISC processor family.
*
* $Id$
*/
#ifndef _INCLUDE_HPPATYPES_H
#define _INCLUDE_HPPATYPES_H
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* 8-bit unsigned integer */
typedef unsigned short unsigned16; /* 16-bit unsigned integer */
typedef unsigned int unsigned32; /* 32-bit unsigned integer */
typedef unsigned long long unsigned64; /* 64-bit unsigned integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif /* _INCLUDE_HPPATYPES_H */
/* end of include file */

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/* hppatypes.h
*
* This include file contains type definitions pertaining to the Hewlett
* Packard PA-RISC processor family.
*
* $Id$
*/
#ifndef _INCLUDE_HPPATYPES_H
#define _INCLUDE_HPPATYPES_H
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* 8-bit unsigned integer */
typedef unsigned short unsigned16; /* 16-bit unsigned integer */
typedef unsigned int unsigned32; /* 32-bit unsigned integer */
typedef unsigned long long unsigned64; /* 64-bit unsigned integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif /* _INCLUDE_HPPATYPES_H */
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES =
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h i386.h i386types.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the Intel
* i386 processor.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/i386.h> /* pick up machine definitions */
#include <libcpu/cpu.h>
#ifndef ASM
#include <rtems/score/i386types.h>
#endif
/* conditional compilation parameters */
#define CPU_INLINE_ENABLE_DISPATCH TRUE
#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
/*
* i386 has an RTEMS allocated and managed interrupt stack.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP, some have an FPU such as the i387
* for the i386, others have it built in (i486DX, Pentium).
*/
#if ( I386_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE /* i387 for i386 */
#else
#define CPU_HARDWARE_FP FALSE
#endif
#define CPU_ALL_TASKS_ARE_FP FALSE
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
#define CPU_STACK_GROWS_UP FALSE
#define CPU_STRUCTURE_ALIGNMENT
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Thread_Idle_body
* must be provided and is the default IDLE thread body instead of
* _CPU_Thread_Idle_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN FALSE
#define CPU_LITTLE_ENDIAN TRUE
/* structures */
/*
* Basic integer context for the i386 family.
*/
typedef struct {
unsigned32 eflags; /* extended flags register */
void *esp; /* extended stack pointer register */
void *ebp; /* extended base pointer register */
unsigned32 ebx; /* extended bx register */
unsigned32 esi; /* extended source index register */
unsigned32 edi; /* extended destination index flags register */
} Context_Control;
/*
* FP context save area for the i387 numeric coprocessors.
*/
typedef struct {
unsigned8 fp_save_area[108]; /* context size area for I80387 */
/* 28 bytes for environment */
} Context_Control_fp;
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of execptions.
*
* idtIndex is either the interrupt number or the trap/exception number.
* faultCode is the code pushed by the processor on some exceptions.
*/
typedef struct {
unsigned32 edi;
unsigned32 esi;
unsigned32 ebp;
unsigned32 esp0;
unsigned32 ebx;
unsigned32 edx;
unsigned32 ecx;
unsigned32 eax;
unsigned32 idtIndex;
unsigned32 faultCode;
unsigned32 eip;
unsigned32 cs;
unsigned32 eflags;
} CPU_Exception_frame;
typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
extern cpuExcHandlerType _currentExcHandler;
extern void rtems_exception_init_mngt();
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt
* that will lead to re-enter the kernel to signal the thread.
*/
typedef CPU_Exception_frame CPU_Interrupt_frame;
typedef enum {
I386_EXCEPTION_DIVIDE_BY_ZERO = 0,
I386_EXCEPTION_DEBUG = 1,
I386_EXCEPTION_NMI = 2,
I386_EXCEPTION_BREAKPOINT = 3,
I386_EXCEPTION_OVERFLOW = 4,
I386_EXCEPTION_BOUND = 5,
I386_EXCEPTION_ILLEGAL_INSTR = 6,
I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
I386_EXCEPTION_DOUBLE_FAULT = 8,
I386_EXCEPTION_I386_COPROC_SEG_ERR = 9,
I386_EXCEPTION_INVALID_TSS = 10,
I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
I386_EXCEPTION_STACK_SEGMENT_FAULT = 12,
I386_EXCEPTION_GENERAL_PROT_ERR = 13,
I386_EXCEPTION_PAGE_FAULT = 14,
I386_EXCEPTION_INTEL_RES15 = 15,
I386_EXCEPTION_FLOAT_ERROR = 16,
I386_EXCEPTION_ALIGN_CHECK = 17,
I386_EXCEPTION_MACHINE_CHECK = 18,
I386_EXCEPTION_ENTER_RDBG = 50 /* to enter manually RDBG */
} Intel_symbolic_exception_name;
/*
* The following table contains the information required to configure
* the i386 specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
unsigned32 interrupt_table_segment;
void *interrupt_table_offset;
} rtems_cpu_table;
/*
* context size area for floating point
*
* NOTE: This is out of place on the i386 to avoid a forward reference.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/* variables */
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/* constants */
/*
* This defines the number of levels and the mask used to pick those
* bits out of a thread mode.
*/
#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
/*
* extra stack required by the MPCI receive server thread
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
/*
* i386 family supports 256 distinct vectors.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Minimum size of a thread's stack.
*/
#define CPU_STACK_MINIMUM_SIZE 1024
/*
* i386 is pretty tolerant of alignment. Just put things on 4 byte boundaries.
*/
#define CPU_ALIGNMENT 4
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* On i386 thread stacks require no further alignment after allocation
* from the Workspace.
*/
#define CPU_STACK_ALIGNMENT 0
/* macros */
/*
* ISR handler macros
*
* These macros perform the following functions:
* + disable all maskable CPU interrupts
* + restore previous interrupt level (enable)
* + temporarily restore interrupts (flash)
* + set a particular level
*/
#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
#define _CPU_ISR_Flash( _level ) i386_flash_interrupts( _level )
#define _CPU_ISR_Set_level( _new_level ) \
{ \
if ( _new_level ) asm volatile ( "cli" ); \
else asm volatile ( "sti" ); \
}
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/*
* Context handler macros
*
* These macros perform the following functions:
* + initialize a context area
* + restart the current thread
* + calculate the initial pointer into a FP context area
* + initialize an FP context area
*/
#define CPU_EFLAGS_INTERRUPTS_ON 0x00003202
#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
do { \
unsigned32 _stack; \
\
if ( (_isr) ) (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_OFF; \
else (_the_context)->eflags = CPU_EFLAGS_INTERRUPTS_ON; \
\
_stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
\
*((proc_ptr *)(_stack)) = (_entry_point); \
(_the_context)->ebp = (void *) _stack; \
(_the_context)->esp = (void *) _stack; \
} while (0)
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
#define _CPU_Context_Initialize_fp( _fp_area ) \
{ \
unsigned32 *_source = (unsigned32 *) &_CPU_Null_fp_context; \
unsigned32 *_destination = *(_fp_area); \
unsigned32 _index; \
\
for ( _index=0 ; _index < CPU_CONTEXT_FP_SIZE/4 ; _index++ ) \
*_destination++ = *_source++; \
}
/* end of Context handler macros */
/*
* Fatal Error manager macros
*
* These macros perform the following functions:
* + disable interrupts and halt the CPU
*/
#define _CPU_Fatal_halt( _error ) \
{ \
asm volatile ( "cli ; \
movl %0,%%eax ; \
hlt" \
: "=r" ((_error)) : "0" ((_error)) \
); \
}
/* end of Fatal Error manager macros */
/*
* Bitfield handler macros
*
* These macros perform the following functions:
* + scan for the highest numbered (MSB) set in a 16 bit bitfield
*/
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
register unsigned16 __value_in_register = (_value); \
\
_output = 0; \
\
asm volatile ( "bsfw %0,%1 " \
: "=r" (__value_in_register), "=r" (_output) \
: "0" (__value_in_register), "1" (_output) \
); \
}
/* end of Bitfield handler macros */
/*
* Priority handler macros
*
* These macros perform the following functions:
* + return a mask with the bit for this major/minor portion of
* of thread priority set.
* + translate the bit number returned by "Bitfield_find_first_bit"
* into an index into the thread ready chain bit maps
*/
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Thread_Idle_body
*
* Use the halt instruction of low power mode of a particular i386 model.
*/
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
void _CPU_Thread_Idle_body( void );
#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner and avoid stack conflicts.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* i386.h
*
* This include file contains information pertaining to the Intel
* i386 processor.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i386_h
#define __i386_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section contains the information required to build
* RTEMS for a particular member of the Intel i386
* family when executing in protected mode. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*
* Currently recognized:
* i386_fp (i386 DX or SX w/i387)
* i386_nofp (i386 DX or SX w/o i387)
* i486dx
* i486sx
* pentium
*
* CPU Model Feature Flags:
*
* I386_HAS_BSWAP: Defined to "1" if the instruction for endian swapping
* (bswap) should be used. This instruction appears to
* be present in all i486's and above.
*
* I386_HAS_FPU: Defined to "1" if the CPU has an FPU.
*
*/
#if defined(i386_fp)
#define CPU_MODEL_NAME "i386 with i387"
#define I386_HAS_BSWAP 0
#elif defined(i386_nofp)
#define CPU_MODEL_NAME "i386 w/o i387"
#define I386_HAS_FPU 0
#define I386_HAS_BSWAP 0
#elif defined(i486dx)
#define CPU_MODEL_NAME "i486dx"
#elif defined(i486sx)
#define CPU_MODEL_NAME "i486sx"
#define I386_HAS_FPU 0
#elif defined(pentium)
#define CPU_MODEL_NAME "Pentium"
#else
#error "Unsupported CPU Model"
#endif
/*
* Set default values for CPU model feature flags
*
* NOTE: These settings are chosen to reflect most of the family members.
*/
#ifndef I386_HAS_FPU
#define I386_HAS_FPU 1
#endif
#ifndef I386_HAS_BSWAP
#define I386_HAS_BSWAP 1
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "Intel i386"
#ifndef ASM
/*
* The following routine swaps the endian format of an unsigned int.
* It must be static so it can be referenced indirectly.
*/
static inline unsigned int i386_swap_U32(
unsigned int value
)
{
unsigned long lout;
#if (I386_HAS_BSWAP == 0)
asm volatile( "rorw $8,%%ax;"
"rorl $16,%0;"
"rorw $8,%%ax" : "=a" (lout) : "0" (value) );
#else
__asm__ volatile( "bswap %0" : "=r" (lout) : "0" (value));
#endif
return( lout );
}
static inline unsigned int i386_swap_U16(
unsigned int value
)
{
unsigned short sout;
__asm__ volatile( "rorw $8,%0" : "=r" (sout) : "0" (value));
return (sout);
}
/* routines */
/*
* i386_Logical_to_physical
*
* Converts logical address to physical address.
*/
void *i386_Logical_to_physical(
unsigned short segment,
void *address
);
/*
* i386_Physical_to_logical
*
* Converts physical address to logical address.
*/
void *i386_Physical_to_logical(
unsigned short segment,
void *address
);
/*
* "Simpler" names for a lot of the things defined in this file
*/
/* segment access routines */
#define get_cs() i386_get_cs()
#define get_ds() i386_get_ds()
#define get_es() i386_get_es()
#define get_ss() i386_get_ss()
#define get_fs() i386_get_fs()
#define get_gs() i386_get_gs()
#define CPU_swap_u32( _value ) i386_swap_U32( _value )
#define CPU_swap_u16( _value ) i386_swap_U16( _value )
/* i80x86 I/O instructions */
#define outport_byte( _port, _value ) i386_outport_byte( _port, _value )
#define outport_word( _port, _value ) i386_outport_word( _port, _value )
#define outport_long( _port, _value ) i386_outport_long( _port, _value )
#define inport_byte( _port, _value ) i386_inport_byte( _port, _value )
#define inport_word( _port, _value ) i386_inport_word( _port, _value )
#define inport_long( _port, _value ) i386_inport_long( _port, _value )
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* i386types.h
*
* This include file contains type definitions pertaining to the Intel
* i386 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i386_TYPES_h
#define __i386_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void i386_isr;
typedef i386_isr ( *i386_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* i386types.h
*
* This include file contains type definitions pertaining to the Intel
* i386 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i386_TYPES_h
#define __i386_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void i386_isr;
typedef i386_isr ( *i386_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h i960.h i960types.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the Intel
* i960 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#pragma align 4 /* for GNU C structure alignment */
#include <rtems/score/i960.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/i960types.h>
#endif
#define CPU_INLINE_ENABLE_DISPATCH FALSE
#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
/*
* Use the i960's hardware interrupt stack support and have the
* interrupt manager allocate the memory for it.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP (SA/KA/CA/CF), others have it built in
* (KB/MC/MX). There does not appear to be an external coprocessor
* for this family.
*/
#if ( I960_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#error "Floating point support for i960 family has been implemented!!!"
#else
#define CPU_HARDWARE_FP FALSE
#endif
#define CPU_ALL_TASKS_ARE_FP FALSE
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_STACK_GROWS_UP TRUE
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/* structures */
/*
* Basic integer context for the i960 family.
*/
typedef struct {
void *r0_pfp; /* (r0) Previous Frame Pointer */
void *r1_sp; /* (r1) Stack Pointer */
unsigned32 pc; /* (pc) Processor Control */
void *g8; /* (g8) Global Register 8 */
void *g9; /* (g9) Global Register 9 */
void *g10; /* (g10) Global Register 10 */
void *g11; /* (g11) Global Register 11 */
void *g12; /* (g12) Global Register 12 */
void *g13; /* (g13) Global Register 13 */
unsigned32 g14; /* (g14) Global Register 14 */
void *g15_fp; /* (g15) Frame Pointer */
} Context_Control;
/*
* FP context save area for the i960 Numeric Extension
*/
typedef struct {
unsigned32 fp0_1; /* (fp0) first word */
unsigned32 fp0_2; /* (fp0) second word */
unsigned32 fp0_3; /* (fp0) third word */
unsigned32 fp1_1; /* (fp1) first word */
unsigned32 fp1_2; /* (fp1) second word */
unsigned32 fp1_3; /* (fp1) third word */
unsigned32 fp2_1; /* (fp2) first word */
unsigned32 fp2_2; /* (fp2) second word */
unsigned32 fp2_3; /* (fp2) third word */
unsigned32 fp3_1; /* (fp3) first word */
unsigned32 fp3_2; /* (fp3) second word */
unsigned32 fp3_3; /* (fp3) third word */
} Context_Control_fp;
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt.
*/
typedef struct {
unsigned32 TBD; /* XXX Fix for this CPU */
} CPU_Interrupt_frame;
/*
* Call frame for the i960 family.
*/
typedef struct {
void *r0_pfp; /* (r0) Previous Frame Pointer */
void *r1_sp; /* (r1) Stack Pointer */
void *r2_rip; /* (r2) Return Instruction Pointer */
void *r3; /* (r3) Local Register 3 */
void *r4; /* (r4) Local Register 4 */
void *r5; /* (r5) Local Register 5 */
void *r6; /* (r6) Local Register 6 */
void *r7; /* (r7) Local Register 7 */
void *r8; /* (r8) Local Register 8 */
void *r9; /* (r9) Local Register 9 */
void *r10; /* (r10) Local Register 10 */
void *r11; /* (r11) Local Register 11 */
void *r12; /* (r12) Local Register 12 */
void *r13; /* (r13) Local Register 13 */
void *r14; /* (r14) Local Register 14 */
void *r15; /* (r15) Local Register 15 */
/* XXX Looks like sometimes there is FP stuff here (MC manual)? */
} CPU_Call_frame;
/*
* The following table contains the information required to configure
* the i960 specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
i960ca_PRCB *Prcb;
#endif
} rtems_cpu_table;
/* variables */
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/* constants */
/*
* This defines the number of levels and the mask used to pick those
* bits out of a thread mode.
*/
#define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */
/*
* context size area for floating point
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* extra stack required by the MPCI receive server thread
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
/*
* i960 family supports 256 distinct vectors.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Minimum size of a thread's stack.
*
* NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
*/
#define CPU_STACK_MINIMUM_SIZE 2048
/*
* i960 is pretty tolerant of alignment. Just put things on 4 byte boundaries.
*/
#define CPU_ALIGNMENT 4
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* i960ca stack requires 16 byte alignment
*
* NOTE: This factor may need to be family member dependent.
*/
#define CPU_STACK_ALIGNMENT 16
/* macros */
/*
* ISR handler macros
*
* These macros perform the following functions:
* + disable all maskable CPU interrupts
* + restore previous interrupt level (enable)
* + temporarily restore interrupts (flash)
* + set a particular level
*/
#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
#define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level )
#define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level )
#define _CPU_ISR_Set_level( newlevel ) \
{ \
unsigned32 _mask = 0; \
unsigned32 _level = (newlevel); \
\
__asm__ volatile ( "ldconst 0x1f0000,%0; \
modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \
: "0" (_mask), "1" (_level) \
); \
}
unsigned32 _CPU_ISR_Get_level( void );
/* ISR handler section macros */
/*
* Context handler macros
*
* These macros perform the following functions:
* + initialize a context area
* + restart the current thread
* + calculate the initial pointer into a FP context area
* + initialize an FP context area
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry, _is_fp ) \
{ CPU_Call_frame *_texit_frame; \
unsigned32 _mask; \
unsigned32 _base_pc; \
unsigned32 _stack_tmp; \
void *_stack; \
\
_stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
_stack = (void *) _stack_tmp; \
\
__asm__ volatile ( "flushreg" : : ); /* flush register cache */ \
\
(_the_context)->r0_pfp = _stack; \
(_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
(_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \
__asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
"modpc 0,0,%1 ; " \
"andnot %0,%1,%1 ; " \
: "=d" (_mask), "=d" (_base_pc) : ); \
(_the_context)->pc = _base_pc | ((_isr) << 16); \
(_the_context)->g14 = 0; \
\
_texit_frame = (CPU_Call_frame *)_stack; \
_texit_frame->r0_pfp = NULL; \
_texit_frame->r1_sp = (_the_context)->g15_fp; \
_texit_frame->r2_rip = (_entry); \
}
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
#define _CPU_Context_Fp_start( _base, _offset ) NULL
#define _CPU_Context_Initialize_fp( _fp_area )
/* end of Context handler macros */
/*
* Fatal Error manager macros
*
* These macros perform the following functions:
* + disable interrupts and halt the CPU
*/
#define _CPU_Fatal_halt( _errorcode ) \
{ unsigned32 _mask, _level; \
unsigned32 _error = (_errorcode); \
\
__asm__ volatile ( "ldconst 0x1f0000,%0 ; \
mov %0,%1 ; \
modpc 0,%0,%1 ; \
mov %2,g0 ; \
self: b self " \
: "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
}
/* end of Fatal Error Manager macros */
/*
* Bitfield handler macros
*
* These macros perform the following functions:
* + scan for the highest numbered (MSB) set in a 16 bit bitfield
*/
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ unsigned32 _search = (_value); \
\
(_output) = 0; /* to prevent warnings */ \
__asm__ volatile ( "scanbit %0,%1 " \
: "=d" (_search), "=d" (_output) \
: "0" (_search), "1" (_output) ); \
}
/* end of Bitfield handler macros */
/*
* Priority handler macros
*
* These macros perform the following functions:
* + return a mask with the bit for this major/minor portion of
* of thread priority set.
* + translate the bit number returned by "Bitfield_find_first_bit"
* into an index into the thread ready chain bit maps
*/
#define _CPU_Priority_Mask( _bit_number ) \
( 0x8000 >> (_bit_number) )
#define _CPU_Priority_bits_index( _priority ) \
( 15 - (_priority) )
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner and avoid stack conflicts.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* i960.h
*
* This include file contains information pertaining to the Intel
* i960 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i960_h
#define __i960_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the Intel i960
* family. It does this by setting variables to indicate
* which implementation dependent features are present
* in a particular member of the family.
*
* NOTE: For now i960 is really the i960ca. eventually need
* to put in at least support for FPU.
*/
#if defined(__i960CA__)
#define CPU_MODEL_NAME "i960ca"
#define I960_HAS_FPU 0
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "Intel i960"
#ifndef ASM
/*
* XXX should have an ifdef here and have stuff for the other
* XXX family members...
*/
#if defined(__i960CA__)
/* i960CA control structures */
/* Intel i960CA Control Table */
typedef struct {
/* Control Group 0 */
unsigned int ipb0; /* IP breakpoint 0 */
unsigned int ipb1; /* IP breakpoint 1 */
unsigned int dab0; /* data address breakpoint 0 */
unsigned int dab1; /* data address breakpoint 1 */
/* Control Group 1 */
unsigned int imap0; /* interrupt map 0 */
unsigned int imap1; /* interrupt map 1 */
unsigned int imap2; /* interrupt map 2 */
unsigned int icon; /* interrupt control */
/* Control Group 2 */
unsigned int mcon0; /* memory region 0 configuration */
unsigned int mcon1; /* memory region 1 configuration */
unsigned int mcon2; /* memory region 2 configuration */
unsigned int mcon3; /* memory region 3 configuration */
/* Control Group 3 */
unsigned int mcon4; /* memory region 4 configuration */
unsigned int mcon5; /* memory region 5 configuration */
unsigned int mcon6; /* memory region 6 configuration */
unsigned int mcon7; /* memory region 7 configuration */
/* Control Group 4 */
unsigned int mcon8; /* memory region 8 configuration */
unsigned int mcon9; /* memory region 9 configuration */
unsigned int mcon10; /* memory region 10 configuration */
unsigned int mcon11; /* memory region 11 configuration */
/* Control Group 5 */
unsigned int mcon12; /* memory region 12 configuration */
unsigned int mcon13; /* memory region 13 configuration */
unsigned int mcon14; /* memory region 14 configuration */
unsigned int mcon15; /* memory region 15 configuration */
/* Control Group 6 */
unsigned int bpcon; /* breakpoint control */
unsigned int tc; /* trace control */
unsigned int bcon; /* bus configuration control */
unsigned int reserved; /* reserved */
} i960ca_control_table;
/* Intel i960CA Processor Control Block */
typedef struct {
unsigned int *fault_tbl; /* fault table base address */
i960ca_control_table
*control_tbl; /* control table base address */
unsigned int initial_ac; /* AC register initial value */
unsigned int fault_config; /* fault configuration word */
void **intr_tbl; /* interrupt table base address */
void *sys_proc_tbl; /* system procedure table
base address */
unsigned int reserved; /* reserved */
unsigned int *intr_stack; /* interrupt stack pointer */
unsigned int ins_cache_cfg; /* instruction cache
configuration word */
unsigned int reg_cache_cfg; /* register cache configuration word */
} i960ca_PRCB;
#endif
/*
* Interrupt Level Routines
*/
#define i960_disable_interrupts( oldlevel ) \
{ (oldlevel) = 0x1f0000; \
asm volatile ( "modpc 0,%1,%1" \
: "=d" ((oldlevel)) \
: "0" ((oldlevel)) ); \
}
#define i960_enable_interrupts( oldlevel ) \
{ unsigned int _mask = 0x1f0000; \
asm volatile ( "modpc 0,%0,%1" \
: "=d" (_mask), "=d" ((oldlevel)) \
: "0" (_mask), "1" ((oldlevel)) ); \
}
#define i960_flash_interrupts( oldlevel ) \
{ unsigned int _mask = 0x1f0000; \
asm volatile ( "modpc 0,%0,%1 ; \
mov %0,%1 ; \
modpc 0,%0,%1" \
: "=d" (_mask), "=d" ((oldlevel)) \
: "0" (_mask), "1" ((oldlevel)) ); \
}
#define i960_get_interrupt_level( _level ) \
{ \
i960_disable_interrupts( _level ); \
i960_enable_interrupts( _level ); \
(_level) = ((_level) & 0x1f0000) >> 16; \
} while ( 0 )
#define i960_atomic_modify( mask, addr, prev ) \
{ register unsigned int _mask = (mask); \
register unsigned int *_addr = (unsigned int *)(addr); \
asm volatile( "atmod %0,%1,%1" \
: "=d" (_addr), "=d" (_mask) \
: "0" (_addr), "1" (_mask) ); \
(prev) = _mask; \
}
#define atomic_modify( _mask, _address, _previous ) \
i960_atomic_modify( _mask, _address, _previous )
#define i960_enable_tracing() \
{ register unsigned int _pc = 0x1; \
asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
}
#define i960_unmask_intr( xint ) \
{ register unsigned int _mask= (1<<(xint)); \
asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
}
#define i960_mask_intr( xint ) \
{ register unsigned int _mask= (1<<(xint)); \
asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
}
#define i960_clear_intr( xint ) \
{ register unsigned int _xint=(xint); \
asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
bbs %0,sf0, loop_til_cleared" \
: "=d" (_xint) : "0" (_xint) ); \
}
#define i960_reload_ctl_group( group ) \
{ register int _cmd = ((group)|0x400) ; \
asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
}
#define i960_cause_intr( intr ) \
{ register int _intr = (intr); \
asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
}
#define i960_soft_reset( prcb ) \
{ register i960ca_PRCB *_prcb = (prcb); \
register unsigned int *_next=0; \
register unsigned int _cmd = 0x30000; \
asm volatile( "lda next,%1; \
sysctl %0,%1,%2; \
next: mov g0,g0" \
: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
: "0" (_cmd), "1" (_next), "2" (_prcb) ); \
}
static inline unsigned int i960_pend_intrs()
{ register unsigned int _intr=0;
asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
return ( _intr );
}
static inline unsigned int i960_mask_intrs()
{ register unsigned int _intr=0;
asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
return( _intr );
}
static inline unsigned int i960_get_fp()
{ register unsigned int _fp=0;
asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
return ( _fp );
}
/*
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
* This version is based on code presented in Vol. 4, No. 4 of
* Insight 960. It is certainly something you wouldn't think
* of on your own.
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
register unsigned int to_swap = value;
register unsigned int temp = 0xFF00FF00;
register unsigned int swapped = 0;
/* to_swap swapped */
asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */
"modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */
"rotate 8,%2,%2" /* 0x12345678 0x78563412 */
: "=r" (to_swap), "=r" (temp), "=r" (swapped)
: "0" (to_swap), "1" (temp), "2" (swapped)
);
return( swapped );
}
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* i960types.h
*
* This include file contains type definitions pertaining to the Intel
* i960 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i960_TYPES_h
#define __i960_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned32 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void i960_isr;
typedef void ( *i960_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* i960types.h
*
* This include file contains type definitions pertaining to the Intel
* i960 processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __i960_TYPES_h
#define __i960_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned32 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void i960_isr;
typedef void ( *i960_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h m68k.h m68ktypes.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the Motorola
* m68xxx processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/m68k.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/m68ktypes.h>
#endif
/* conditional compilation parameters */
#define CPU_INLINE_ENABLE_DISPATCH TRUE
#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE
/*
* Use the m68k's hardware interrupt stack support and have the
* interrupt manager allocate the memory for it.
*/
#if ( M68K_HAS_SEPARATE_STACKS == 1)
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
#else
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
#endif
#define CPU_ALLOCATE_INTERRUPT_STACK 1
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Some family members have no FP, some have an FPU such as the
* MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
*
* NOTE: If on a CPU without hardware FP, then one can use software
* emulation. The gcc software FP emulation code has data which
* must be contexted switched on a per task basis.
*/
#if ( M68K_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#define CPU_SOFTWARE_FP FALSE
#else
#define CPU_HARDWARE_FP FALSE
#if defined(__GCC__)
#define CPU_SOFTWARE_FP TRUE
#else
#define CPU_SOFTWARE_FP FALSE
#endif
#endif
/*
* All tasks are not by default floating point tasks on this CPU.
* The IDLE task does not have a floating point context on this CPU.
* It is safe to use the deferred floating point context switch
* algorithm on this CPU.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_STACK_GROWS_UP FALSE
#define CPU_STRUCTURE_ALIGNMENT
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
#ifndef ASM
/* structures */
/*
* Basic integer context for the m68k family.
*/
typedef struct {
unsigned32 sr; /* (sr) status register */
unsigned32 d2; /* (d2) data register 2 */
unsigned32 d3; /* (d3) data register 3 */
unsigned32 d4; /* (d4) data register 4 */
unsigned32 d5; /* (d5) data register 5 */
unsigned32 d6; /* (d6) data register 6 */
unsigned32 d7; /* (d7) data register 7 */
void *a2; /* (a2) address register 2 */
void *a3; /* (a3) address register 3 */
void *a4; /* (a4) address register 4 */
void *a5; /* (a5) address register 5 */
void *a6; /* (a6) address register 6 */
void *a7_msp; /* (a7) master stack pointer */
} Context_Control;
/*
* Floating point context ares
*/
#if (CPU_SOFTWARE_FP == TRUE)
/*
* This is the same as gcc's view of the software FP condition code
* register _fpCCR. The implementation of the emulation code is
* in the gcc-VERSION/config/m68k directory. This structure is
* correct as of gcc 2.7.2.2.
*/
typedef struct {
unsigned16 _exception_bits;
unsigned16 _trap_enable_bits;
unsigned16 _sticky_bits;
unsigned16 _rounding_mode;
unsigned16 _format;
unsigned16 _last_operation;
union {
float sf;
double df;
} _operand1;
union {
float sf;
double df;
} _operand2;
} Context_Control_fp;
#else
/*
* FP context save area for the M68881/M68882 numeric coprocessors.
*/
typedef struct {
unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */
/* 96 bytes for FMOVEM FP0-7 */
/* 12 bytes for FMOVEM CREGS */
/* 4 bytes for non-null flag */
} Context_Control_fp;
#endif
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt.
*/
typedef struct {
unsigned32 TBD; /* XXX Fix for this CPU */
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the m68k specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
m68k_isr *interrupt_vector_table;
} rtems_cpu_table;
/* variables */
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
extern char _VBR[];
#if ( M68K_HAS_VBR == 0 )
/*
* Table of ISR handler entries that resides in RAM. The FORMAT/ID is
* pushed onto the stack. This is not is the same order as VBR processors.
* The ISR handler takes the format and uses it for dispatching the user
* handler.
*
* FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
*
*/
typedef struct {
unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */
unsigned16 format_id;
unsigned16 jmp; /* jmp _ISR_Handlers */
unsigned32 isr_handler;
} _CPU_ISR_handler_entry;
#define M68K_MOVE_A7 0x3F3C
#define M68K_JMP 0x4EF9
/* points to jsr-exception-table in targets wo/ VBR register */
SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
#endif /* M68K_HAS_VBR */
#endif /* ASM */
/* constants */
/*
* This defines the number of levels and the mask used to pick those
* bits out of a thread mode.
*/
#define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */
/*
* context size area for floating point
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* extra stack required by the MPCI receive server thread
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
/*
* m68k family supports 256 distinct vectors.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Minimum size of a thread's stack.
*/
#define CPU_STACK_MINIMUM_SIZE 2048
/*
* m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries.
*/
#define CPU_ALIGNMENT 4
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* On m68k thread stacks require no further alignment after allocation
* from the Workspace.
*/
#define CPU_STACK_ALIGNMENT 0
#ifndef ASM
/* macros */
/*
* ISR handler macros
*
* These macros perform the following functions:
* + disable all maskable CPU interrupts
* + restore previous interrupt level (enable)
* + temporarily restore interrupts (flash)
* + set a particular level
*/
#define _CPU_ISR_Disable( _level ) \
m68k_disable_interrupts( _level )
#define _CPU_ISR_Enable( _level ) \
m68k_enable_interrupts( _level )
#define _CPU_ISR_Flash( _level ) \
m68k_flash_interrupts( _level )
#define _CPU_ISR_Set_level( _newlevel ) \
m68k_set_interrupt_level( _newlevel )
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/*
* Context handler macros
*
* These macros perform the following functions:
* + initialize a context area
* + restart the current thread
* + calculate the initial pointer into a FP context area
* + initialize an FP context area
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
do { \
unsigned32 _stack; \
\
(_the_context)->sr = 0x3000 | ((_isr) << 8); \
_stack = (unsigned32)(_stack_base) + (_size) - 4; \
(_the_context)->a7_msp = (void *)_stack; \
*(void **)_stack = (void *)(_entry_point); \
} while ( 0 )
#define _CPU_Context_Restart_self( _the_context ) \
{ asm volatile( "movew %0,%%sr ; " \
"moval %1,%%a7 ; " \
"rts" \
: "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
: "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
}
/*
* Floating Point Context Area Support routines
*/
#if (CPU_SOFTWARE_FP == TRUE)
/*
* This software FP implementation is only for GCC.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
((void *) _Addresses_Add_offset( (_base), (_offset) ) )
#define _CPU_Context_Initialize_fp( _fp_area ) \
{ \
Context_Control_fp *_fp; \
_fp = *(Context_Control_fp **)_fp_area; \
_fp->_exception_bits = 0; \
_fp->_trap_enable_bits = 0; \
_fp->_sticky_bits = 0; \
_fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \
_fp->_format = 0; /* NIL */ \
_fp->_last_operation = 0; /* NOOP */ \
_fp->_operand1.df = 0; \
_fp->_operand2.df = 0; \
}
#else
#define _CPU_Context_Fp_start( _base, _offset ) \
((void *) \
_Addresses_Add_offset( \
(_base), \
(_offset) + CPU_CONTEXT_FP_SIZE - 4 \
) \
)
#define _CPU_Context_Initialize_fp( _fp_area ) \
{ unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
\
*(--(_fp_context)) = 0; \
*(_fp_area) = (unsigned8 *)(_fp_context); \
}
#endif
/* end of Context handler macros */
/*
* Fatal Error manager macros
*
* These macros perform the following functions:
* + disable interrupts and halt the CPU
*/
#if ( M68K_COLDFIRE_ARCH == 1 )
#define _CPU_Fatal_halt( _error ) \
{ asm volatile( "move.w %%sr,%%d0\n\t" \
"or.l %2,%%d0\n\t" \
"move.w %%d0,%%sr\n\t" \
"move.l %1,%%d0\n\t" \
"move.l #0xDEADBEEF,%%d1\n\t" \
"halt" \
: "=g" (_error) \
: "0" (_error), "d"(0x0700) \
: "d0", "d1" ); \
}
#else
#define _CPU_Fatal_halt( _error ) \
{ asm volatile( "movl %0,%%d0; " \
"orw #0x0700,%%sr; " \
"stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
}
#endif
/* end of Fatal Error manager macros */
/*
* Bitfield handler macros
*
* These macros perform the following functions:
* + scan for the highest numbered (MSB) set in a 16 bit bitfield
*
* NOTE:
*
* It appears that on the M68020 bitfield are always 32 bits wide
* when in a register. This code forces the bitfield to be in
* memory (it really always is anyway). This allows us to
* have a real 16 bit wide bitfield which operates "correctly."
*/
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
#if ( M68K_HAS_BFFFO == 1 )
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
#else
/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
_CPU_Priority_bits_index is not needed), handles the 0 case, and
does not molest _value -- jsg */
#if ( M68K_COLDFIRE_ARCH == 1 )
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
extern const unsigned char __BFFFOtable[256]; \
register int dumby; \
\
asm volatile ( \
" clr.l %1\n" \
" move.w %2,%1\n" \
" lsr.l #8,%1\n" \
" beq.s 1f\n" \
" move.b (%3,%1),%0\n" \
" bra.s 0f\n" \
"1: move.w %2,%1\n" \
" move.b (%3,%1),%0\n" \
" addq.l #8,%0\n" \
"0: and.l #0xff,%0\n" \
: "=&d" ((_output)), "=&d" ((dumby)) \
: "d" ((_value)), "ao" ((__BFFFOtable)) \
: "cc" ) ; \
}
#elif ( M68K_HAS_EXTB_L == 1 )
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
extern const unsigned char __BFFFOtable[256]; \
register int dumby; \
\
asm volatile ( " move.w %2,%1\n" \
" lsr.w #8,%1\n" \
" beq.s 1f\n" \
" move.b (%3,%1.w),%0\n" \
" extb.l %0\n" \
" bra.s 0f\n" \
"1: moveq.l #8,%0\n" \
" add.b (%3,%2.w),%0\n" \
"0:\n" \
: "=&d" ((_output)), "=&d" ((dumby)) \
: "d" ((_value)), "ao" ((__BFFFOtable)) \
: "cc" ) ; \
}
#else
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
extern const unsigned char __BFFFOtable[256]; \
register int dumby; \
\
asm volatile ( " move.w %2,%1\n" \
" lsr.w #8,%1\n" \
" beq.s 1f\n" \
" move.b (%3,%1.w),%0\n" \
" and.l #0x000000ff,%0\n"\
" bra.s 0f\n" \
"1: moveq.l #8,%0\n" \
" add.b (%3,%2.w),%0\n" \
"0:\n" \
: "=&d" ((_output)), "=&d" ((dumby)) \
: "d" ((_value)), "ao" ((__BFFFOtable)) \
: "cc" ) ; \
}
#endif
#endif
/* end of Bitfield handler macros */
/*
* Priority handler macros
*
* These macros perform the following functions:
* + return a mask with the bit for this major/minor portion of
* of thread priority set.
* + translate the bit number returned by "Bitfield_find_first_bit"
* into an index into the thread ready chain bit maps
*/
#define _CPU_Priority_Mask( _bit_number ) \
( 0x8000 >> (_bit_number) )
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
#if (M68K_HAS_FPSP_PACKAGE == 1)
/*
* Hooks for the Floating Point Support Package (FPSP) provided by Motorola
*
* NOTES:
*
* Motorola 68k family CPU's before the 68040 used a coprocessor
* (68881 or 68882) to handle floating point. The 68040 has internal
* floating point support -- but *not* the complete support provided by
* the 68881 or 68882. The leftover functions are taken care of by the
* M68040 Floating Point Support Package. Quoting from the MC68040
* Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
*
* "When used with the M68040FPSP, the MC68040 FPU is fully
* compliant with IEEE floating-point standards."
*
* M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
* is invoked early in the application code to insure that proper FP
* behavior is installed. This is not left to the BSP to call, since
* this would force all applications using that BSP to use FPSP which
* is not necessarily desirable.
*
* There is a similar package for the 68060 but RTEMS does not yet
* support the 68060.
*/
void M68KFPSPInstallExceptionHandlers (void);
SCORE_EXTERN int (*_FPSP_install_raw_handler)(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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c/src/exec/score/cpu/m68k/rtems/score/m68k.h Normal file
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/* m68k.h
*
* This include file contains information pertaining to the Motorola
* m68xxx processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __M68k_h
#define __M68k_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section contains the information required to build
* RTEMS for a particular member of the Motorola MC68xxx
* family. It does this by setting variables to indicate
* which implementation dependent features are present in
* a particular member of the family.
*
* Currently recognized:
* -m68000
* -m68000 -msoft-float
* -m68020
* -m68020 -msoft-float
* -m68030
* -m68040 -msoft-float
* -m68040
* -m68040 -msoft-float
* -m68060
* -m68060 -msoft-float
* -m68302 (no FP) (deprecated, use -m68000)
* -m68332 (no FP) (deprecated, use -mcpu32)
* -mcpu32 (no FP)
* -m5200 (no FP)
*
* As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
* the CPU32 and CPU32+. The option -mcpu32 generates code which can
* be run on either core. RTEMS distinguishes between these two cores
* because they have different alignment rules which impact performance.
* If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
* be defined in your custom file (see make/custom/gen68360.cfg for an
* example of how to do this. If gcc ever distinguishes between these
* two cores, then RTEMS__mcpu32p__ usage will be replaced with the
* appropriate compiler defined predefine.
*
* Here is some information on the 040 variants (courtesy of Doug McBride,
* mcbride@rodin.colorado.edu):
*
* "The 68040 is a superset of the 68EC040 and the 68LC040. The
* 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the
* 68EC040 have renamed the DLE pin as JS0 which must be tied to
* Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The
* 68EC040 has access control units instead of memory management units.
* The 68EC040 should not have the PFLUSH or PTEST instructions executed
* (cause an indeterminate result). The 68EC040 and 68LC040 do not
* implement the DLE or multiplexed bus modes. The 68EC040 does not
* implement the output buffer impedance selection mode of operation."
*
* M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
* 68010, 68302, 68306, 68307). This instruction is available on the 68020
* up and the cpu32 based models.
*
* M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
* data access (68020, 68030, 68040, 68060, CPU32+).
*
* NOTE:
* Eventually it would be nice to evaluate doing a lot of this section
* by having each model specify which core it uses and then go from there.
*/
#if defined(__mc68020__)
#define CPU_MODEL_NAME "m68020"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 1
#define M68K_HAS_BFFFO 1
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
# if defined (__HAVE_68881__)
# define M68K_HAS_FPU 1
# define M68K_HAS_FPSP_PACKAGE 0
# else
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
#elif defined(__mc68030__)
#define CPU_MODEL_NAME "m68030"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 1
#define M68K_HAS_BFFFO 1
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
# if defined (__HAVE_68881__)
# define M68K_HAS_FPU 1
# define M68K_HAS_FPSP_PACKAGE 0
# else
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
#elif defined(__mc68040__)
#define CPU_MODEL_NAME "m68040"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 1
#define M68K_HAS_BFFFO 1
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
# if defined (__HAVE_68881__)
# define M68K_HAS_FPU 1
# define M68K_HAS_FPSP_PACKAGE 1
# else
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
#elif defined(__mc68060__)
#define CPU_MODEL_NAME "m68060"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_BFFFO 1
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
# if defined (__HAVE_68881__)
# define M68K_HAS_FPU 1
# define M68K_HAS_FPSP_PACKAGE 1
# else
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
#elif defined(__mc68302__)
#define CPU_MODEL_NAME "m68302"
#define M68K_HAS_VBR 0
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_BFFFO 0
#define M68K_HAS_PREINDEXING 0
#define M68K_HAS_EXTB_L 0
#define M68K_HAS_MISALIGNED 0
#define M68K_HAS_FPU 0
#define M68K_HAS_FPSP_PACKAGE 0
/* gcc and egcs do not distinguish between CPU32 and CPU32+ */
#elif defined(RTEMS__mcpu32p__)
#define CPU_MODEL_NAME "mcpu32+"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_BFFFO 0
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
#define M68K_HAS_FPU 0
#define M68K_HAS_FPSP_PACKAGE 0
#elif defined(__mcpu32__)
#define CPU_MODEL_NAME "mcpu32"
#define M68K_HAS_VBR 1
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_BFFFO 0
#define M68K_HAS_PREINDEXING 1
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 0
#define M68K_HAS_FPU 0
#define M68K_HAS_FPSP_PACKAGE 0
#elif defined(__mcf5200__)
/* Motorola ColdFire V2 core - RISC/68020 hybrid */
#define CPU_MODEL_NAME "m5200"
#define M68K_HAS_VBR 1
#define M68K_HAS_BFFFO 0
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_PREINDEXING 0
#define M68K_HAS_EXTB_L 1
#define M68K_HAS_MISALIGNED 1
#define M68K_HAS_FPU 0
#define M68K_HAS_FPSP_PACKAGE 0
#define M68K_COLDFIRE_ARCH 1
#elif defined(__mc68000__)
#define CPU_MODEL_NAME "m68000"
#define M68K_HAS_VBR 0
#define M68K_HAS_SEPARATE_STACKS 0
#define M68K_HAS_BFFFO 0
#define M68K_HAS_PREINDEXING 0
#define M68K_HAS_EXTB_L 0
#define M68K_HAS_MISALIGNED 0
# if defined (__HAVE_68881__)
# define M68K_HAS_FPU 1
# define M68K_HAS_FPSP_PACKAGE 0
# else
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
#else
#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
#endif
/*
* If the above did not specify a ColdFire architecture, then set
* this flag to indicate that it is not a ColdFire CPU.
*/
#if !defined(M68K_COLDFIRE_ARCH)
#define M68K_COLDFIRE_ARCH 0
#endif
/*
* Define the name of the CPU family.
*/
#if ( M68K_COLDFIRE_ARCH == 1 )
#define CPU_NAME "Motorola ColdFire"
#else
#define CPU_NAME "Motorola MC68xxx"
#endif
#ifndef ASM
#if ( M68K_COLDFIRE_ARCH == 1 )
#define m68k_disable_interrupts( _level ) \
do { register unsigned32 _tmpsr = 0x0700; \
asm volatile ( "move.w %%sr,%0\n\t" \
"or.l %0,%1\n\t" \
"move.w %1,%%sr" \
: "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
} while( 0 )
#else
#define m68k_disable_interrupts( _level ) \
asm volatile ( "move.w %%sr,%0\n\t" \
"or.w #0x0700,%%sr" \
: "=d" (_level))
#endif
#define m68k_enable_interrupts( _level ) \
asm volatile ( "move.w %0,%%sr " : : "d" (_level));
#if ( M68K_COLDFIRE_ARCH == 1 )
#define m68k_flash_interrupts( _level ) \
do { register unsigned32 _tmpsr = 0x0700; \
asm volatile ( "move.w %2,%%sr\n\t" \
"or.l %2,%1\n\t" \
"move.w %1,%%sr" \
: "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
} while( 0 )
#else
#define m68k_flash_interrupts( _level ) \
asm volatile ( "move.w %0,%%sr\n\t" \
"or.w #0x0700,%%sr" \
: : "d" (_level))
#endif
#define m68k_get_interrupt_level( _level ) \
do { \
register unsigned32 _tmpsr; \
\
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_level = (_tmpsr & 0x0700) >> 8; \
} while (0)
#define m68k_set_interrupt_level( _newlevel ) \
do { \
register unsigned32 _tmpsr; \
\
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
} while (0)
#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
#define m68k_get_vbr( vbr ) \
asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
#define m68k_set_vbr( vbr ) \
asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
#elif ( M68K_COLDFIRE_ARCH == 1 )
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
#define m68k_set_vbr( _vbr ) \
asm volatile ("move.l %%a7,%%d1 \n\t" \
"move.l %0,%%a7\n\t" \
"movec %%a7,%%vbr\n\t" \
"move.l %%d1,%%a7\n\t" \
: : "d" (_vbr) : "d1" );
#else
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
#define m68k_set_vbr( _vbr )
#endif
/*
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*/
static inline unsigned int m68k_swap_u32(
unsigned int value
)
{
unsigned int swapped = value;
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
return( swapped );
}
static inline unsigned int m68k_swap_u16(
unsigned int value
)
{
unsigned short swapped = value;
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
return( swapped );
}
/* XXX this is only valid for some m68k family members and should be fixed */
#define m68k_enable_caching() \
{ register unsigned32 _ctl=0x01; \
asm volatile ( "movec %0,%%cacr" \
: "=d" (_ctl) : "0" (_ctl) ); \
}
#define CPU_swap_u32( value ) m68k_swap_u32( value )
#define CPU_swap_u16( value ) m68k_swap_u16( value )
#endif /* !ASM */
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* m68ktypes.h
*
* This include file contains type definitions pertaining to the Motorola
* m68xxx processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __M68k_TYPES_h
#define __M68k_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void m68k_isr;
typedef void ( *m68k_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* m68ktypes.h
*
* This include file contains type definitions pertaining to the Motorola
* m68xxx processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __M68k_TYPES_h
#define __M68k_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void m68k_isr;
typedef void ( *m68k_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu memcpy
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h m68302.h m68360.h qsm.h sim.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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/* cpu.h
*
* This include file contains information pertaining to the IDT 4650
* processor.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)cpu.h 08/29/96 1.7 */
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/mips64orion.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/mipstypes.h>
#endif
extern int mips_disable_interrupts( void );
extern void mips_enable_interrupts( int _level );
extern int mips_disable_global_interrupts( void );
extern void mips_enable_global_interrupts( void );
extern void mips_fatal_error ( int error );
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH TRUE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/*
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.
* If FALSE, then no installation is performed.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/*
* Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
* If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization.
*
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* If there is a FP coprocessor such as the i387 or mc68881, then
* the answer is TRUE.
*
* The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#if ( MIPS64ORION_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#else
#define CPU_HARDWARE_FP FALSE
#endif
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
* must be provided and is the default IDLE thread body instead of
* _Internal_threads_Idle_thread_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
/* we can use the low power wait instruction for the IDLE thread */
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
/* our stack grows down */
#define CPU_STACK_GROWS_UP FALSE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
/* our cache line size is 16 bytes */
#if __GNUC__
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
#else
#define CPU_STRUCTURE_ALIGNMENT
#endif
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
typedef struct {
unsigned64 s0;
unsigned64 s1;
unsigned64 s2;
unsigned64 s3;
unsigned64 s4;
unsigned64 s5;
unsigned64 s6;
unsigned64 s7;
unsigned64 sp;
unsigned64 fp;
unsigned64 ra;
unsigned64 c0_sr;
unsigned64 c0_epc;
} Context_Control;
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
typedef struct {
unsigned32 fp0;
unsigned32 fp1;
unsigned32 fp2;
unsigned32 fp3;
unsigned32 fp4;
unsigned32 fp5;
unsigned32 fp6;
unsigned32 fp7;
unsigned32 fp8;
unsigned32 fp9;
unsigned32 fp10;
unsigned32 fp11;
unsigned32 fp12;
unsigned32 fp13;
unsigned32 fp14;
unsigned32 fp15;
unsigned32 fp16;
unsigned32 fp17;
unsigned32 fp18;
unsigned32 fp19;
unsigned32 fp20;
unsigned32 fp21;
unsigned32 fp22;
unsigned32 fp23;
unsigned32 fp24;
unsigned32 fp25;
unsigned32 fp26;
unsigned32 fp27;
unsigned32 fp28;
unsigned32 fp29;
unsigned32 fp30;
unsigned32 fp31;
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the mips processor specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
unsigned32 some_other_cpu_dependent_info;
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* system initialization thread. Remember that in a multiprocessor
* system the system intialization thread becomes the MP server thread.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*/
#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32))
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 8
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _int_level ) \
do{ \
_int_level = mips_disable_interrupts(); \
}while(0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _level ) \
do{ \
mips_enable_interrupts(_level); \
}while(0)
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _xlevel ) \
do{ \
int _scratch; \
_CPU_ISR_Enable( _xlevel ); \
_CPU_ISR_Disable( _scratch ); \
}while(0)
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*/
extern void _CPU_ISR_Set_level( unsigned32 _new_level );
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
{ \
unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
(_the_context)->ra = (unsigned64)_entry_point; \
(_the_context)->c0_sr = 0; \
}
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/*
* The purpose of this macro is to allow the initial pointer into
* A floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ \
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
}
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*/
#define _CPU_Fatal_halt( _error ) \
{ \
mips_disable_global_interrupts(); \
mips_fatal_error(_error); \
}
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
(_output) = 0; /* do something to prevent warnings */ \
}
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Internal_threads_Idle_thread_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Thread_Idle_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: May be unnecessary to reload some registers.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
* This version will work on any processor, but if there is a better
* way for your CPU PLEASE use it. The most common way to do this is to:
*
* swap least significant two bytes with 16-bit rotate
* swap upper and lower 16-bits
* swap most significant two bytes with 16-bit rotate
*
* Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is
* that interrupts would probably have to be disabled to insure that
* an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code
* will be fetched incorrectly.
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
unsigned32 byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
/*
* Miscellaneous prototypes
*
* NOTE: The names should have mips64orion in them.
*/
void disable_int( unsigned32 mask );
void enable_int( unsigned32 mask );
#ifdef __cplusplus
}
#endif
#endif

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/* mipstypes.h
*
* This include file contains type definitions pertaining to the IDT 4650
* processor family.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)mipstypes.h 08/20/96 1.4 */
#ifndef __MIPS_TYPES_h
#define __MIPS_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void mips_isr;
typedef void ( *mips_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* mipstypes.h
*
* This include file contains type definitions pertaining to the IDT 4650
* processor family.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)mipstypes.h 08/20/96 1.4 */
#ifndef __MIPS_TYPES_h
#define __MIPS_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void mips_isr;
typedef void ( *mips_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h mips68orion.h mipstypes.h idtcpu.h iregdef.h idtmon.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the IDT 4650
* processor.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)cpu.h 08/29/96 1.7 */
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/mips64orion.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/mipstypes.h>
#endif
extern int mips_disable_interrupts( void );
extern void mips_enable_interrupts( int _level );
extern int mips_disable_global_interrupts( void );
extern void mips_enable_global_interrupts( void );
extern void mips_fatal_error ( int error );
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH TRUE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/*
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.
* If FALSE, then no installation is performed.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/*
* Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
* If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization.
*
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* If there is a FP coprocessor such as the i387 or mc68881, then
* the answer is TRUE.
*
* The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#if ( MIPS64ORION_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#else
#define CPU_HARDWARE_FP FALSE
#endif
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
* must be provided and is the default IDLE thread body instead of
* _Internal_threads_Idle_thread_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
/* we can use the low power wait instruction for the IDLE thread */
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
/* our stack grows down */
#define CPU_STACK_GROWS_UP FALSE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
/* our cache line size is 16 bytes */
#if __GNUC__
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
#else
#define CPU_STRUCTURE_ALIGNMENT
#endif
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
typedef struct {
unsigned64 s0;
unsigned64 s1;
unsigned64 s2;
unsigned64 s3;
unsigned64 s4;
unsigned64 s5;
unsigned64 s6;
unsigned64 s7;
unsigned64 sp;
unsigned64 fp;
unsigned64 ra;
unsigned64 c0_sr;
unsigned64 c0_epc;
} Context_Control;
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
typedef struct {
unsigned32 fp0;
unsigned32 fp1;
unsigned32 fp2;
unsigned32 fp3;
unsigned32 fp4;
unsigned32 fp5;
unsigned32 fp6;
unsigned32 fp7;
unsigned32 fp8;
unsigned32 fp9;
unsigned32 fp10;
unsigned32 fp11;
unsigned32 fp12;
unsigned32 fp13;
unsigned32 fp14;
unsigned32 fp15;
unsigned32 fp16;
unsigned32 fp17;
unsigned32 fp18;
unsigned32 fp19;
unsigned32 fp20;
unsigned32 fp21;
unsigned32 fp22;
unsigned32 fp23;
unsigned32 fp24;
unsigned32 fp25;
unsigned32 fp26;
unsigned32 fp27;
unsigned32 fp28;
unsigned32 fp29;
unsigned32 fp30;
unsigned32 fp31;
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the mips processor specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
unsigned32 some_other_cpu_dependent_info;
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* system initialization thread. Remember that in a multiprocessor
* system the system intialization thread becomes the MP server thread.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*/
#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32))
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 8
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _int_level ) \
do{ \
_int_level = mips_disable_interrupts(); \
}while(0)
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _level ) \
do{ \
mips_enable_interrupts(_level); \
}while(0)
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _xlevel ) \
do{ \
int _scratch; \
_CPU_ISR_Enable( _xlevel ); \
_CPU_ISR_Disable( _scratch ); \
}while(0)
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*/
extern void _CPU_ISR_Set_level( unsigned32 _new_level );
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
{ \
unsigned32 _stack_tmp = (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
(_the_context)->ra = (unsigned64)_entry_point; \
(_the_context)->c0_sr = 0; \
}
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/*
* The purpose of this macro is to allow the initial pointer into
* A floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ \
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
}
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*/
#define _CPU_Fatal_halt( _error ) \
{ \
mips_disable_global_interrupts(); \
mips_fatal_error(_error); \
}
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
(_output) = 0; /* do something to prevent warnings */ \
}
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Internal_threads_Idle_thread_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Thread_Idle_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: May be unnecessary to reload some registers.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
* This version will work on any processor, but if there is a better
* way for your CPU PLEASE use it. The most common way to do this is to:
*
* swap least significant two bytes with 16-bit rotate
* swap upper and lower 16-bits
* swap most significant two bytes with 16-bit rotate
*
* Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is
* that interrupts would probably have to be disabled to insure that
* an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code
* will be fetched incorrectly.
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
unsigned32 byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
/*
* Miscellaneous prototypes
*
* NOTE: The names should have mips64orion in them.
*/
void disable_int( unsigned32 mask );
void enable_int( unsigned32 mask );
#ifdef __cplusplus
}
#endif
#endif

440
c/src/exec/score/cpu/mips64orion/rtems/score/idtcpu.h Normal file
View File

@@ -0,0 +1,440 @@
/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
/*
** idtcpu.h -- cpu related defines
*/
#ifndef _IDTCPU_H__
#define _IDTCPU_H__
/*
* 950313: Ketan added Register definition for XContext reg.
* added define for WAIT instruction.
* 950421: Ketan added Register definition for Config reg (R3081)
*/
/*
** memory configuration and mapping
*/
#define K0BASE 0x80000000
#define K0SIZE 0x20000000
#define K1BASE 0xa0000000
#define K1SIZE 0x20000000
#define K2BASE 0xc0000000
#define K2SIZE 0x20000000
#if defined(CPU_R4000)
#define KSBASE 0xe0000000
#define KSSIZE 0x20000000
#endif
#define KUBASE 0
#define KUSIZE 0x80000000
/*
** Exception Vectors
*/
#if defined(CPU_R3000)
#define UT_VEC K0BASE /* utlbmiss vector */
#define E_VEC (K0BASE+0x80) /* exception vevtor */
#endif
#if defined(CPU_R4000)
#define T_VEC (K0BASE+0x000) /* tlbmiss vector */
#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
#define C_VEC (K0BASE+0x100) /* cache error vector */
#define E_VEC (K0BASE+0x180) /* exception vector */
#endif
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
/*
** Address conversion macros
*/
#ifdef CLANGUAGE
#define CAST(as) (as)
#else
#define CAST(as)
#endif
#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */
#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */
/*
** Cache size constants
*/
#define MINCACHE 0x200 /* 512 For 3041. */
#define MAXCACHE 0x40000 /* 256*1024 256k */
#if defined(CPU_R4000)
/* R4000 configuration register definitions */
#define CFG_CM 0x80000000 /* Master-Checker mode */
#define CFG_ECMASK 0x70000000 /* System Clock Ratio */
#define CFG_ECBY2 0x00000000 /* divide by 2 */
#define CFG_ECBY3 0x10000000 /* divide by 3 */
#define CFG_ECBY4 0x20000000 /* divide by 4 */
#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */
#define CFG_EPD 0x00000000 /* D */
#define CFG_EPDDX 0x01000000 /* DDX */
#define CFG_EPDDXX 0x02000000 /* DDXX */
#define CFG_EPDXDX 0x03000000 /* DXDX */
#define CFG_EPDDXXX 0x04000000 /* DDXXX */
#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */
#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */
#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */
#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */
#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */
#define CFG_SBSHIFT 22
#define CFG_SB4 0x00000000 /* 4 words */
#define CFG_SB8 0x00400000 /* 8 words */
#define CFG_SB16 0x00800000 /* 16 words */
#define CFG_SB32 0x00c00000 /* 32 words */
#define CFG_SS 0x00200000 /* Split secondary cache */
#define CFG_SW 0x00100000 /* Secondary cache port width */
#define CFG_EWMASK 0x000c0000 /* System port width */
#define CFG_EWSHIFT 18
#define CFG_EW64 0x00000000 /* 64 bit */
#define CFG_EW32 0x00010000 /* 32 bit */
#define CFG_SC 0x00020000 /* Secondary cache absent */
#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */
#define CFG_BE 0x00008000 /* Big Endian */
#define CFG_EM 0x00004000 /* ECC mode enable */
#define CFG_EB 0x00002000 /* Block ordering */
#define CFG_ICMASK 0x00000e00 /* Instruction cache size */
#define CFG_ICSHIFT 9
#define CFG_DCMASK 0x000001c0 /* Data cache size */
#define CFG_DCSHIFT 6
#define CFG_IB 0x00000020 /* Instruction cache block size */
#define CFG_DB 0x00000010 /* Data cache block size */
#define CFG_CU 0x00000008 /* Update on Store Conditional */
#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
/*
* R4000 primary cache mode
*/
#define CFG_C_UNCACHED 2
#define CFG_C_NONCOHERENT 3
#define CFG_C_COHERENTXCL 4
#define CFG_C_COHERENTXCLW 5
#define CFG_C_COHERENTUPD 6
/*
* R4000 cache operations (should be in assembler...?)
*/
#define Index_Invalidate_I 0x0 /* 0 0 */
#define Index_Writeback_Inv_D 0x1 /* 0 1 */
#define Index_Invalidate_SI 0x2 /* 0 2 */
#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
#define Index_Load_Tag_I 0x4 /* 1 0 */
#define Index_Load_Tag_D 0x5 /* 1 1 */
#define Index_Load_Tag_SI 0x6 /* 1 2 */
#define Index_Load_Tag_SD 0x7 /* 1 3 */
#define Index_Store_Tag_I 0x8 /* 2 0 */
#define Index_Store_Tag_D 0x9 /* 2 1 */
#define Index_Store_Tag_SI 0xA /* 2 2 */
#define Index_Store_Tag_SD 0xB /* 2 3 */
#define Create_Dirty_Exc_D 0xD /* 3 1 */
#define Create_Dirty_Exc_SD 0xF /* 3 3 */
#define Hit_Invalidate_I 0x10 /* 4 0 */
#define Hit_Invalidate_D 0x11 /* 4 1 */
#define Hit_Invalidate_SI 0x12 /* 4 2 */
#define Hit_Invalidate_SD 0x13 /* 4 3 */
#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
#define Fill_I 0x14 /* 5 0 */
#define Hit_Writeback_D 0x19 /* 6 1 */
#define Hit_Writeback_SD 0x1B /* 6 3 */
#define Hit_Writeback_I 0x18 /* 6 0 */
#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
#ifndef WAIT
#define WAIT .word 0x42000020
#endif WAIT
#ifndef wait
#define wait .word 0x42000020
#endif wait
#endif
/*
** TLB resource defines
*/
#if defined(CPU_R3000)
#define N_TLB_ENTRIES 64
#define TLB_PGSIZE 0x1000
#define RANDBASE 8
#define TLBLO_PFNMASK 0xfffff000
#define TLBLO_PFNSHIFT 12
#define TLBLO_N 0x800 /* non-cacheable */
#define TLBLO_D 0x400 /* writeable */
#define TLBLO_V 0x200 /* valid bit */
#define TLBLO_G 0x100 /* global access bit */
#define TLBHI_VPNMASK 0xfffff000
#define TLBHI_VPNSHIFT 12
#define TLBHI_PIDMASK 0xfc0
#define TLBHI_PIDSHIFT 6
#define TLBHI_NPID 64
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x00003f00
#define TLBINX_INXSHIFT 8
#define TLBRAND_RANDMASK 0x00003f00
#define TLBRAND_RANDSHIFT 8
#define TLBCTXT_BASEMASK 0xffe00000
#define TLBCTXT_BASESHIFT 21
#define TLBCTXT_VPNMASK 0x001ffffc
#define TLBCTXT_VPNSHIFT 2
#endif
#if defined(CPU_R4000)
#define N_TLB_ENTRIES 48
#define TLBHI_VPN2MASK 0xffffe000
#define TLBHI_PIDMASK 0x000000ff
#define TLBHI_NPID 256
#define TLBLO_PFNMASK 0x3fffffc0
#define TLBLO_PFNSHIFT 6
#define TLBLO_D 0x00000004 /* writeable */
#define TLBLO_V 0x00000002 /* valid bit */
#define TLBLO_G 0x00000001 /* global access bit */
#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */
#define TLBLO_CSHIFT 3
#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
#define TLBINX_PROBE 0x80000000
#define TLBINX_INXMASK 0x0000003f
#define TLBRAND_RANDMASK 0x0000003f
#define TLBCTXT_BASEMASK 0xff800000
#define TLBCTXT_BASESHIFT 23
#define TLBCTXT_VPN2MASK 0x007ffff0
#define TLBCTXT_VPN2SHIFT 4
#define TLBPGMASK_MASK 0x01ffe000
#endif
#if defined(CPU_R3000)
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_BEV 0x00400000 /* use boot exception vectors */
/* Cache control bits */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_PE 0x00100000 /* cache parity error */
#define SR_CM 0x00080000 /* cache miss */
#define SR_PZ 0x00040000 /* cache parity zero */
#define SR_SWC 0x00020000 /* swap cache */
#define SR_ISC 0x00010000 /* Isolate data cache */
/*
** status register interrupt masks and bits
*/
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IMASKSHIFT 8
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
#endif
#if defined(CPU_R4000)
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
#define SR_RP 0x08000000 /* Reduced power operation */
#define SR_FR 0x04000000 /* Additional floating point registers */
#define SR_RE 0x02000000 /* Reverse endian in user mode */
#define SR_BEV 0x00400000 /* Use boot exception vectors */
#define SR_TS 0x00200000 /* TLB shutdown */
#define SR_SR 0x00100000 /* Soft reset */
#define SR_CH 0x00040000 /* Cache hit */
#define SR_CE 0x00020000 /* Use cache ECC */
#define SR_DE 0x00010000 /* Disable cache exceptions */
/*
** status register interrupt masks and bits
*/
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
#define SR_IMASK8 0x00000000 /* mask level 8 */
#define SR_IMASK7 0x00008000 /* mask level 7 */
#define SR_IMASK6 0x0000c000 /* mask level 6 */
#define SR_IMASK5 0x0000e000 /* mask level 5 */
#define SR_IMASK4 0x0000f000 /* mask level 4 */
#define SR_IMASK3 0x0000f800 /* mask level 3 */
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
#define SR_IMASKSHIFT 8
#define SR_IBIT8 0x00008000 /* bit level 8 */
#define SR_IBIT7 0x00004000 /* bit level 7 */
#define SR_IBIT6 0x00002000 /* bit level 6 */
#define SR_IBIT5 0x00001000 /* bit level 5 */
#define SR_IBIT4 0x00000800 /* bit level 4 */
#define SR_IBIT3 0x00000400 /* bit level 3 */
#define SR_IBIT2 0x00000200 /* bit level 2 */
#define SR_IBIT1 0x00000100 /* bit level 1 */
#define SR_KSMASK 0x00000018 /* Kernel mode mask */
#define SR_KSUSER 0x00000010 /* User mode */
#define SR_KSSUPER 0x00000008 /* Supervisor mode */
#define SR_KSKERNEL 0x00000000 /* Kernel mode */
#define SR_ERL 0x00000004 /* Error level */
#define SR_EXL 0x00000002 /* Exception level */
#define SR_IE 0x00000001 /* Interrupts enabled */
#endif
/*
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
#define CAUSE_IPSHIFT 8
#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
#define CAUSE_EXCSHIFT 2
#ifndef XDS
/*
** Coprocessor 0 registers
*/
#define C0_INX $0 /* tlb index */
#define C0_RAND $1 /* tlb random */
#if defined(CPU_R3000)
#define C0_TLBLO $2 /* tlb entry low */
#endif
#if defined(CPU_R4000)
#define C0_TLBLO0 $2 /* tlb entry low 0 */
#define C0_TLBLO1 $3 /* tlb entry low 1 */
#endif
#define C0_CTXT $4 /* tlb context */
#if defined(CPU_R4000)
#define C0_PAGEMASK $5 /* tlb page mask */
#define C0_WIRED $6 /* number of wired tlb entries */
#endif
#define C0_BADVADDR $8 /* bad virtual address */
#if defined(CPU_R4000)
#define C0_COUNT $9 /* cycle count */
#endif
#define C0_TLBHI $10 /* tlb entry hi */
#if defined(CPU_R4000)
#define C0_COMPARE $11 /* cyccle count comparator */
#endif
#define C0_SR $12 /* status register */
#define C0_CAUSE $13 /* exception cause */
#define C0_EPC $14 /* exception pc */
#define C0_PRID $15 /* revision identifier */
#if defined(CPU_R3000)
#define C0_CONFIG $3 /* configuration register R3081*/
#endif
#if defined(CPU_R4000)
#define C0_CONFIG $16 /* configuration register */
#define C0_LLADDR $17 /* linked load address */
#define C0_WATCHLO $18 /* watchpoint trap register */
#define C0_WATCHHI $19 /* watchpoint trap register */
#define C0_XCTXT $20 /* extended tlb context */
#define C0_ECC $26 /* secondary cache ECC control */
#define C0_CACHEERR $27 /* cache error status */
#define C0_TAGLO $28 /* cache tag lo */
#define C0_TAGHI $29 /* cache tag hi */
#define C0_ERRPC $30 /* cache error pc */
#endif
#endif XDS
#ifdef R4650
#define IWATCH $18
#define DWATCH $19
#define IBASE $0
#define IBOUND $1
#define DBASE $2
#define DBOUND $3
#define CALG $17
#endif
#endif /* _IDTCPU_H__ */

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/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
/*
** idtmon.h - General header file for the IDT Prom Monitor
**
** Copyright 1989 Integrated Device Technology, Inc.
** All Rights Reserved.
**
** June 1989 - D.Cahoon
*/
#ifndef __IDTMON_H__
#define __IDTMON_H__
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
/*
** M_BUSWIDTH
** Memory bus width (including bank interleaving) in bytes
** used when doing memory sizing to prevent bus capacitance
** reporting ghost memory locations
*/
#if defined(CPU_R3000)
#define M_BUSWIDTH 8 /* 32bit memory bank interleaved */
#endif
#if defined(CPU_R4000)
#define M_BUSWIDTH 16 /* 64 bit memory bank interleaved */
#endif
/*
** this is the default value for the number of bytes to add in calculating
** the checksums in the checksum command
*/
#define CHK_SUM_CNT 0x20000 /* number of bytes to calc chksum for */
/*
** Monitor modes
*/
#define MODE_MONITOR 5 /* IDT Prom Monitor is executing */
#define MODE_USER 0xa /* USER is executing */
/*
** memory reference widths
*/
#define SW_BYTE 1
#define SW_HALFWORD 2
#define SW_WORD 4
#define SW_TRIBYTEL 12
#define SW_TRIBYTER 20
#ifdef CPU_R4000
/*
** definitions for select_cache call
*/
#define DCACHE 0
#define ICACHE 1
#define SCACHE 2
#endif
#ifndef ASM
typedef struct {
unsigned int mem_size;
unsigned int icache_size;
unsigned int dcache_size;
#ifdef CPU_R4000
unsigned int scache_size;
#endif
} mem_config;
#endif
/*
** general equates for diagnostics and boolean functions
*/
#define PASS 0
#define FAIL 1
#ifndef TRUE
#define TRUE 1
#endif TRUE
#ifndef NULL
#define NULL 0
#endif NULL
#ifndef FALSE
#define FALSE 0
#endif FALSE
/*
** portablility equates
*/
#ifndef BOOL
#define BOOL unsigned int
#endif BOOL
#ifndef GLOBAL
#define GLOBAL /**/
#endif GLOBAL
#ifndef MLOCAL
#define MLOCAL static
#endif MLOCAL
#ifdef XDS
#define CONST const
#else
#define CONST
#endif XDS
#define u_char unsigned char
#define u_short unsigned short
#define u_int unsigned int
/*
** assembly instructions for compatability between xds and mips
*/
#ifndef XDS
#define sllv sll
#define srlv srl
#endif XDS
/*
** debugger macros for assembly language routines. Allows the
** programmer to set up the necessary stack frame info
** required by debuggers to do stack traces.
*/
#ifndef XDS
#define FRAME(name,frm_reg,offset,ret_reg) \
.globl name; \
.ent name; \
name:; \
.frame frm_reg,offset,ret_reg
#define ENDFRAME(name) \
.end name
#else
#define FRAME(name,frm_reg,offset,ret_reg) \
.globl _##name;\
_##name:
#define ENDFRAME(name)
#endif XDS
#endif /* __IDTMON_H__ */

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/*
Based upon IDT provided code with the following release:
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
/*
** iregdef.h - IDT R3000 register structure header file
**
** Copyright 1989 Integrated Device Technology, Inc
** All Rights Reserved
**
*/
#ifndef __IREGDEF_H__
#define __IREGDEF_H__
/*
* 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
* added Register definition for XContext reg.
* Look towards end of this file.
*/
/*
** register names
*/
#define r0 $0
#define r1 $1
#define r2 $2
#define r3 $3
#define r4 $4
#define r5 $5
#define r6 $6
#define r7 $7
#define r8 $8
#define r9 $9
#define r10 $10
#define r11 $11
#define r12 $12
#define r13 $13
#define r14 $14
#define r15 $15
#define r16 $16
#define r17 $17
#define r18 $18
#define r19 $19
#define r20 $20
#define r21 $21
#define r22 $22
#define r23 $23
#define r24 $24
#define r25 $25
#define r26 $26
#define r27 $27
#define r28 $28
#define r29 $29
#define r30 $30
#define r31 $31
#define fp0 $f0
#define fp1 $f1
#define fp2 $f2
#define fp3 $f3
#define fp4 $f4
#define fp5 $f5
#define fp6 $f6
#define fp7 $f7
#define fp8 $f8
#define fp9 $f9
#define fp10 $f10
#define fp11 $f11
#define fp12 $f12
#define fp13 $f13
#define fp14 $f14
#define fp15 $f15
#define fp16 $f16
#define fp17 $f17
#define fp18 $f18
#define fp19 $f19
#define fp20 $f20
#define fp21 $f21
#define fp22 $f22
#define fp23 $f23
#define fp24 $f24
#define fp25 $f25
#define fp26 $f26
#define fp27 $f27
#define fp28 $f28
#define fp29 $f29
#define fp30 $f30
#define fp31 $f31
#define fcr0 $0
#define fcr30 $30
#define fcr31 $31
#define zero $0 /* wired zero */
#define AT $at /* assembler temp */
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers a0-a3 */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved t0-t9 */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* callee saved s0-s8 */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define k0 $26 /* kernel usage */
#define k1 $27 /* kernel usage */
#define gp $28 /* sdata pointer */
#define sp $29 /* stack pointer */
#define s8 $30 /* yet another saved reg for the callee */
#define fp $30 /* frame pointer - this is being phased out by MIPS */
#define ra $31 /* return address */
/*
** relative position of registers in save reg area
*/
#define R_R0 0
#define R_R1 1
#define R_R2 2
#define R_R3 3
#define R_R4 4
#define R_R5 5
#define R_R6 6
#define R_R7 7
#define R_R8 8
#define R_R9 9
#define R_R10 10
#define R_R11 11
#define R_R12 12
#define R_R13 13
#define R_R14 14
#define R_R15 15
#define R_R16 16
#define R_R17 17
#define R_R18 18
#define R_R19 19
#define R_R20 20
#define R_R21 21
#define R_R22 22
#define R_R23 23
#define R_R24 24
#define R_R25 25
#define R_R26 26
#define R_R27 27
#define R_R28 28
#define R_R29 29
#define R_R30 30
#define R_R31 31
#define R_F0 32
#define R_F1 33
#define R_F2 34
#define R_F3 35
#define R_F4 36
#define R_F5 37
#define R_F6 38
#define R_F7 39
#define R_F8 40
#define R_F9 41
#define R_F10 42
#define R_F11 43
#define R_F12 44
#define R_F13 45
#define R_F14 46
#define R_F15 47
#define R_F16 48
#define R_F17 49
#define R_F18 50
#define R_F19 51
#define R_F20 52
#define R_F21 53
#define R_F22 54
#define R_F23 55
#define R_F24 56
#define R_F25 57
#define R_F26 58
#define R_F27 59
#define R_F28 60
#define R_F29 61
#define R_F30 62
#define R_F31 63
#define NCLIENTREGS 64
#define R_EPC 64
#define R_MDHI 65
#define R_MDLO 66
#define R_SR 67
#define R_CAUSE 68
#define R_TLBHI 69
#if defined(CPU_R3000)
#define R_TLBLO 70
#endif
#if defined(CPU_R4000)
#define R_TLBLO0 70
#endif
#define R_BADVADDR 71
#define R_INX 72
#define R_RAND 73
#define R_CTXT 74
#define R_EXCTYPE 75
#define R_MODE 76
#define R_PRID 77
#define R_FCSR 78
#define R_FEIR 79
#if defined(CPU_R3000)
#define NREGS 80
#endif
#if defined(CPU_R4000)
#define R_TLBLO1 80
#define R_PAGEMASK 81
#define R_WIRED 82
#define R_COUNT 83
#define R_COMPARE 84
#define R_CONFIG 85
#define R_LLADDR 86
#define R_WATCHLO 87
#define R_WATCHHI 88
#define R_ECC 89
#define R_CACHEERR 90
#define R_TAGLO 91
#define R_TAGHI 92
#define R_ERRPC 93
#define R_XCTXT 94 /* Ketan added from SIM64bit */
#define NREGS 95
#endif
/*
** For those who like to think in terms of the compiler names for the regs
*/
#define R_ZERO R_R0
#define R_AT R_R1
#define R_V0 R_R2
#define R_V1 R_R3
#define R_A0 R_R4
#define R_A1 R_R5
#define R_A2 R_R6
#define R_A3 R_R7
#define R_T0 R_R8
#define R_T1 R_R9
#define R_T2 R_R10
#define R_T3 R_R11
#define R_T4 R_R12
#define R_T5 R_R13
#define R_T6 R_R14
#define R_T7 R_R15
#define R_S0 R_R16
#define R_S1 R_R17
#define R_S2 R_R18
#define R_S3 R_R19
#define R_S4 R_R20
#define R_S5 R_R21
#define R_S6 R_R22
#define R_S7 R_R23
#define R_T8 R_R24
#define R_T9 R_R25
#define R_K0 R_R26
#define R_K1 R_R27
#define R_GP R_R28
#define R_SP R_R29
#define R_FP R_R30
#define R_RA R_R31
/* Ketan added the following */
#ifdef CPU_R3000
#define sreg sw
#define lreg lw
#define rmfc0 mfc0
#define rmtc0 mtc0
#define R_SZ 4
#endif CPU_R3000
#ifdef CPU_R4000
#if __mips < 3
#define sreg sw
#define lreg lw
#define rmfc0 mfc0
#define rmtc0 mtc0
#define R_SZ 4
#else
#define sreg sd
#define lreg ld
#define rmfc0 dmfc0
#define rmtc0 dmtc0
#define R_SZ 8
#endif
#endif CPU_R4000
/* Ketan till here */
#endif /* __IREGDEF_H__ */

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/* mipstypes.h
*
* This include file contains type definitions pertaining to the IDT 4650
* processor family.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)mipstypes.h 08/20/96 1.4 */
#ifndef __MIPS_TYPES_h
#define __MIPS_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void mips_isr;
typedef void ( *mips_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* mipstypes.h
*
* This include file contains type definitions pertaining to the IDT 4650
* processor family.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
/* @(#)mipstypes.h 08/20/96 1.4 */
#ifndef __MIPS_TYPES_h
#define __MIPS_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void mips_isr;
typedef void ( *mips_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu rtems
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h cpu_asm.h mips64orion.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h no_cpu.h no_cputypes.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* cpu.h
*
* This include file contains information pertaining to the XXX
* processor.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_h
#define __CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/no_cpu.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/no_cputypes.h>
#endif
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH FALSE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
/*
* Does this CPU have hardware support for a dedicated interrupt stack?
*
* If TRUE, then it must be installed during initialization.
* If FALSE, then no installation is performed.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
/*
* Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
*
* If TRUE, then the memory is allocated during initialization.
* If FALSE, then the memory is allocated during initialization.
*
* This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
* or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
*/
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* If there is a FP coprocessor such as the i387 or mc68881, then
* the answer is TRUE.
*
* The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#if ( NO_CPU_HAS_FPU == 1 )
#define CPU_HARDWARE_FP TRUE
#else
#define CPU_HARDWARE_FP FALSE
#endif
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP TRUE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Thread_Idle_body
* must be provided and is the default IDLE thread body instead of
* _CPU_Thread_Idle_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
#define CPU_STACK_GROWS_UP TRUE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
#define CPU_STRUCTURE_ALIGNMENT
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
typedef struct {
unsigned32 some_integer_register;
unsigned32 some_system_register;
} Context_Control;
typedef struct {
double some_float_register;
} Context_Control_fp;
typedef struct {
unsigned32 special_interrupt_register;
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the XXX processor specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
unsigned32 some_other_cpu_dependent_info;
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* MPCI receive server thread. Remember that in a multiprocessor
* system this thread must exist and be able to process all directives.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*/
#define CPU_STACK_MINIMUM_SIZE (1024*4)
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 8
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT 0
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _isr_cookie ) \
{ \
(_isr_cookie) = 0; /* do something to prevent warnings */ \
}
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _isr_cookie ) \
{ \
}
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _isr_cookie ) \
{ \
}
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*
* The get routine usually must be implemented as a subroutine.
*/
#define _CPU_ISR_Set_level( new_level ) \
{ \
}
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \
{ \
}
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/*
* The purpose of this macro is to allow the initial pointer into
* a floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ \
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
}
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* halts/stops the CPU.
*/
#define _CPU_Fatal_halt( _error ) \
{ \
}
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
(_output) = 0; /* do something to prevent warnings */ \
}
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Thread_Idle_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Thread_Idle_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: May be unnecessary to reload some registers.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
/* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*
* This version will work on any processor, but if there is a better
* way for your CPU PLEASE use it. The most common way to do this is to:
*
* swap least significant two bytes with 16-bit rotate
* swap upper and lower 16-bits
* swap most significant two bytes with 16-bit rotate
*
* Some CPUs have special instructions which swap a 32-bit quantity in
* a single instruction (e.g. i486). It is probably best to avoid
* an "endian swapping control bit" in the CPU. One good reason is
* that interrupts would probably have to be disabled to insure that
* an interrupt does not try to access the same "chunk" with the wrong
* endian. Another good reason is that on some CPUs, the endian bit
* endianness for ALL fetches -- both code and data -- so the code
* will be fetched incorrectly.
*/
static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
unsigned32 byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}
#define CPU_swap_u16( value ) \
(((value&0xff) << 8) | ((value >> 8)&0xff))
#ifdef __cplusplus
}
#endif
#endif

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/* no_cpu.h
*
* This file is an example (i.e. "no CPU") of the file which is
* created for each CPU family port of RTEMS.
*
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*
*/
#ifndef _INCLUDE_NO_CPU_h
#define _INCLUDE_NO_CPU_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "no cpu"
* family when executing in protected mode. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*/
#if defined(no_cpu)
#define CPU_MODEL_NAME "no_cpu"
#define NOCPU_HAS_FPU 1
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "NO CPU"
#ifdef __cplusplus
}
#endif
#endif /* ! _INCLUDE_NO_CPU_h */
/* end of include file */

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/* no_cputypes.h
*
* This include file contains type definitions pertaining to the Intel
* no_cpu processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __NO_CPU_TYPES_h
#define __NO_CPU_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* no_cputypes.h
*
* This include file contains type definitions pertaining to the Intel
* no_cpu processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __NO_CPU_TYPES_h
#define __NO_CPU_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu cpu_asm rtems
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h cpu_asm.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES =
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h ppc.h ppctypes.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu ppccache
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h mpc860.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems # irq_stub
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h shtypes.h sh.h sh_io.h cpu_isps.h iosh7030.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

875
c/src/exec/score/cpu/sh/rtems/score/cpu.h Normal file
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@@ -0,0 +1,875 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _SH_CPU_h
#define _SH_CPU_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/sh.h> /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/shtypes.h>
#endif
/* conditional compilation parameters */
/*
* Should the calls to _Thread_Enable_dispatch be inlined?
*
* If TRUE, then they are inlined.
* If FALSE, then a subroutine call is made.
*
* Basically this is an example of the classic trade-off of size
* versus speed. Inlining the call (TRUE) typically increases the
* size of RTEMS while speeding up the enabling of dispatching.
* [NOTE: In general, the _Thread_Dispatch_disable_level will
* only be 0 or 1 unless you are in an interrupt handler and that
* interrupt handler invokes the executive.] When not inlined
* something calls _Thread_Enable_dispatch which in turns calls
* _Thread_Dispatch. If the enable dispatch is inlined, then
* one subroutine call is avoided entirely.]
*/
#define CPU_INLINE_ENABLE_DISPATCH FALSE
/*
* Should the body of the search loops in _Thread_queue_Enqueue_priority
* be unrolled one time? In unrolled each iteration of the loop examines
* two "nodes" on the chain being searched. Otherwise, only one node
* is examined per iteration.
*
* If TRUE, then the loops are unrolled.
* If FALSE, then the loops are not unrolled.
*
* The primary factor in making this decision is the cost of disabling
* and enabling interrupts (_ISR_Flash) versus the cost of rest of the
* body of the loop. On some CPUs, the flash is more expensive than
* one iteration of the loop body. In this case, it might be desirable
* to unroll the loop. It is important to note that on some CPUs, this
* code is the longest interrupt disable period in RTEMS. So it is
* necessary to strike a balance when setting this parameter.
*/
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
* If FALSE, nothing is done.
*
* If the CPU supports a dedicated interrupt stack in hardware,
* then it is generally the responsibility of the BSP to allocate it
* and set it up.
*
* If the CPU does not support a dedicated interrupt stack, then
* the porter has two options: (1) execute interrupts on the
* stack of the interrupted task, and (2) have RTEMS manage a dedicated
* interrupt stack.
*
* If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
*
* Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
* CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
* possible that both are FALSE for a particular CPU. Although it
* is unclear what that would imply about the interrupt processing
* procedure on that CPU.
*/
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
/*
* We define the interrupt stack in the linker script
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
/*
* Does the CPU have hardware floating point?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
*
* We currently support sh1 only, which has no FPU, other SHes have an FPU
*
* The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
* It indicates whether or not this CPU model has FP support. For
* example, it would be possible to have an i386_nofp CPU model
* which set this to false to indicate that you have an i386 without
* an i387 and wish to leave floating point support out of RTEMS.
*/
#define CPU_HARDWARE_FP FALSE
/*
* Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
*
* If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
* If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
*
* So far, the only CPU in which this option has been used is the
* HP PA-RISC. The HP C compiler and gcc both implicitly use the
* floating point registers to perform integer multiplies. If
* a function which you would not think utilize the FP unit DOES,
* then one can not easily predict which tasks will use the FP hardware.
* In this case, this option should be TRUE.
*
* If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
*/
#define CPU_ALL_TASKS_ARE_FP FALSE
/*
* Should the IDLE task have a floating point context?
*
* If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
* and it has a floating point context which is switched in and out.
* If FALSE, then the IDLE task does not have a floating point context.
*
* Setting this to TRUE negatively impacts the time required to preempt
* the IDLE task from an interrupt because the floating point context
* must be saved as part of the preemption.
*/
#define CPU_IDLE_TASK_IS_FP FALSE
/*
* Should the saving of the floating point registers be deferred
* until a context switch is made to another different floating point
* task?
*
* If TRUE, then the floating point context will not be stored until
* necessary. It will remain in the floating point registers and not
* disturned until another floating point task is switched to.
*
* If FALSE, then the floating point context is saved when a floating
* point task is switched out and restored when the next floating point
* task is restored. The state of the floating point registers between
* those two operations is not specified.
*
* If the floating point context does NOT have to be saved as part of
* interrupt dispatching, then it should be safe to set this to TRUE.
*
* Setting this flag to TRUE results in using a different algorithm
* for deciding when to save and restore the floating point context.
* The deferred FP switch algorithm minimizes the number of times
* the FP context is saved and restored. The FP context is not saved
* until a context switch is made to another, different FP task.
* Thus in a system with only one FP task, the FP context will never
* be saved or restored.
*/
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
/*
* Does this port provide a CPU dependent IDLE task implementation?
*
* If TRUE, then the routine _CPU_Thread_Idle_body
* must be provided and is the default IDLE thread body instead of
* _CPU_Thread_Idle_body.
*
* If FALSE, then use the generic IDLE thread body if the BSP does
* not provide one.
*
* This is intended to allow for supporting processors which have
* a low power or idle mode. When the IDLE thread is executed, then
* the CPU can be powered down.
*
* The order of precedence for selecting the IDLE thread body is:
*
* 1. BSP provided
* 2. CPU dependent (if provided)
* 3. generic (if no BSP and no CPU dependent)
*/
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
/*
* Does the stack grow up (toward higher addresses) or down
* (toward lower addresses)?
*
* If TRUE, then the grows upward.
* If FALSE, then the grows toward smaller addresses.
*/
#define CPU_STACK_GROWS_UP FALSE
/*
* The following is the variable attribute used to force alignment
* of critical RTEMS structures. On some processors it may make
* sense to have these aligned on tighter boundaries than
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The placement of this macro in the declaration of the variables
* is based on the syntactically requirements of the GNU C
* "__attribute__" extension. For example with GNU C, use
* the following to force a structures to a 32 byte boundary.
*
* __attribute__ ((aligned (32)))
*
* NOTE: Currently only the Priority Bit Map table uses this feature.
* To benefit from using this, the data must be heavily
* used so it will stay in the cache and used frequently enough
* in the executive to justify turning this on.
*/
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned(16)))
/*
* Define what is required to specify how the network to host conversion
* routines are handled.
*
* NOTE: SHes can be big or little endian, the default is big endian
*/
#define CPU_CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
/* __LITTLE_ENDIAN__ is defined if -ml is given to gcc */
#if defined(__LITTLE_ENDIAN__)
#define CPU_BIG_ENDIAN FALSE
#define CPU_LITTLE_ENDIAN TRUE
#else
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
#endif
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
*/
#define CPU_MODES_INTERRUPT_MASK 0x0000000f
/*
* Processor defined structures
*
* Examples structures include the descriptor tables from the i386
* and the processor control structure on the i960ca.
*/
/* may need to put some structures here. */
/*
* Contexts
*
* Generally there are 2 types of context to save.
* 1. Interrupt registers to save
* 2. Task level registers to save
*
* This means we have the following 3 context items:
* 1. task level context stuff:: Context_Control
* 2. floating point task stuff:: Context_Control_fp
* 3. special interrupt level context :: Context_Control_interrupt
*
* On some processors, it is cost-effective to save only the callee
* preserved registers during a task context switch. This means
* that the ISR code needs to save those registers which do not
* persist across function calls. It is not mandatory to make this
* distinctions between the caller/callee saves registers for the
* purpose of minimizing context saved during task switch and on interrupts.
* If the cost of saving extra registers is minimal, simplicity is the
* choice. Save the same context on interrupt entry as for tasks in
* this case.
*
* Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
* care should be used in designing the context area.
*
* On some CPUs with hardware floating point support, the Context_Control_fp
* structure will not be used or it simply consist of an array of a
* fixed number of bytes. This is done when the floating point context
* is dumped by a "FP save context" type instruction and the format
* is not really defined by the CPU. In this case, there is no need
* to figure out the exact format -- only the size. Of course, although
* this is enough information for RTEMS, it is probably not enough for
* a debugger such as gdb. But that is another problem.
*/
typedef struct {
unsigned32 *r15; /* stack pointer */
unsigned32 macl;
unsigned32 mach;
unsigned32 *pr;
unsigned32 *r14; /* frame pointer/call saved */
unsigned32 r13; /* call saved */
unsigned32 r12; /* call saved */
unsigned32 r11; /* call saved */
unsigned32 r10; /* call saved */
unsigned32 r9; /* call saved */
unsigned32 r8; /* call saved */
unsigned32 *r7; /* arg in */
unsigned32 *r6; /* arg in */
#if 0
unsigned32 *r5; /* arg in */
unsigned32 *r4; /* arg in */
#endif
unsigned32 *r3; /* scratch */
unsigned32 *r2; /* scratch */
unsigned32 *r1; /* scratch */
unsigned32 *r0; /* arg return */
unsigned32 gbr;
unsigned32 sr;
} Context_Control;
typedef struct {
} Context_Control_fp;
typedef struct {
} CPU_Interrupt_frame;
/*
* The following table contains the information required to configure
* the SH processor specific parameters.
*/
typedef struct {
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
} rtems_cpu_table;
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
* _CPU_Initialize and copied into the task's FP context area during
* _CPU_Context_Initialize.
*/
/*
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
*/
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* With some compilation systems, it is difficult if not impossible to
* call a high-level language routine from assembly language. This
* is especially true of commercial Ada compilers and name mangling
* C++ ones. This variable can be optionally defined by the CPU porter
* and contains the address of the routine _Thread_Dispatch. This
* can make it easier to invoke that routine at the end of the interrupt
* sequence (if a dispatch is necessary).
*/
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*/
/* XXX: if needed, put more variables here */
/*
* The size of the floating point context area. On some CPUs this
* will not be a "sizeof" because the format of the floating point
* area is not defined -- only the size is. This is usually on
* CPUs with a "floating point save context" instruction.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
/*
* Amount of extra stack (above minimum stack size) required by
* MPCI receive server thread. Remember that in a multiprocessor
* system this thread must exist and be able to process all directives.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
* by RTEMS.
*/
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
/*
* Should be large enough to run all RTEMS tests. This insures
* that a "reasonable" small application should not have any problems.
*
* We have been able to run the sptests with this value, but have not
* been able to run the tmtest suite.
*/
#define CPU_STACK_MINIMUM_SIZE 4096
/*
* CPU's worst alignment requirement for data types on a byte boundary. This
* alignment does not take into account the requirements for the stack.
*/
#define CPU_ALIGNMENT 4
/*
* This number corresponds to the byte alignment requirement for the
* heap handler. This alignment requirement may be stricter than that
* for the data types alignment specified by CPU_ALIGNMENT. It is
* common for the heap to follow the same alignment requirement as
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
* then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for memory
* buffers allocated by the partition manager. This alignment requirement
* may be stricter than that for the data types alignment specified by
* CPU_ALIGNMENT. It is common for the partition to follow the same
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
* enough for the partition, then this should be set to CPU_ALIGNMENT.
*
* NOTE: This does not have to be a power of 2. It does have to
* be greater or equal to than CPU_ALIGNMENT.
*/
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
/*
* This number corresponds to the byte alignment requirement for the
* stack. This alignment requirement may be stricter than that for the
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
* is strict enough for the stack, then this should be set to 0.
*
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
*/
#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
/* ISR handler macros */
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
*/
#define _CPU_ISR_Disable( _level) \
sh_disable_interrupts( _level )
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of an RTEMS critical section. The parameter
* _level is not modified.
*/
#define _CPU_ISR_Enable( _level) \
sh_enable_interrupts( _level)
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define _CPU_ISR_Flash( _level) \
sh_flash_interrupts( _level)
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a generic fashion are undefined. Someday,
* it would be nice if these were "mapped" by the application
* via a callout. For example, m68k has 8 levels 0 - 7, levels
* 8 - 255 would be available for bsp/application specific meaning.
* This could be used to manage a programmable interrupt controller
* via the rtems_task_mode directive.
*/
#define _CPU_ISR_Set_level( _newlevel) \
sh_set_interrupt_level(_newlevel)
unsigned32 _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
/*
* Initialize the context to a state suitable for starting a
* task after a context restore operation. Generally, this
* involves:
*
* - setting a starting address
* - preparing the stack
* - preparing the stack and frame pointers
* - setting the proper interrupt level in the context
* - initializing the floating point context
*
* This routine generally does not set any unnecessary register
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
* NOTE: This is_fp parameter is TRUE if the thread is to be a floating
* point thread. This is typically only used on CPUs where the
* FPU may be easily disabled by software such as on the SPARC
* where the PSR contains an enable FPU bit.
*/
/*
* FIXME: defined as a function for debugging - should be a macro
*/
SCORE_EXTERN void _CPU_Context_Initialize(
Context_Control *_the_context,
void *_stack_base,
unsigned32 _size,
unsigned32 _isr,
void (*_entry_point)(void),
int _is_fp );
/*
* This routine is responsible for somehow restarting the currently
* executing task. If you are lucky, then all that is necessary
* is restoring the context. Otherwise, there will need to be
* a special assembly routine which does something special in this
* case. Context_Restore should work most of the time. It will
* not work if restarting self conflicts with the stack frame
* assumptions of restoring a context.
*/
#define _CPU_Context_Restart_self( _the_context ) \
_CPU_Context_restore( (_the_context) );
/*
* The purpose of this macro is to allow the initial pointer into
* a floating point context area (used to save the floating point
* context) to be at an arbitrary place in the floating point
* context area.
*
* This is necessary because some FP units are designed to have
* their context saved as a stack which grows into lower addresses.
* Other FP units can be saved by simply moving registers into offsets
* from the base of the context area. Finally some FP units provide
* a "dump context" instruction which could fill in from high to low
* or low to high based on the whim of the CPU designers.
*/
#define _CPU_Context_Fp_start( _base, _offset ) \
( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
/*
* This routine initializes the FP context area passed to it to.
* There are a few standard ways in which to initialize the
* floating point context. The code included for this macro assumes
* that this is a CPU in which a "initial" FP context was saved into
* _CPU_Null_fp_context and it simply copies it to the destination
* context passed to it.
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
* SH has no FPU !!!!!!!!!!!!
*/
#define _CPU_Context_Initialize_fp( _destination ) \
{ }
/* end of Context handler macros */
/* Fatal Error manager macros */
/*
* FIXME: Trap32 ???
*
* This routine copies _error into a known place -- typically a stack
* location or a register, optionally disables interrupts, and
* invokes a Trap32 Instruction which returns to the breakpoint
* routine of cmon.
*/
#ifdef BSP_FATAL_HALT
/* we manage the fatal error in the board support package */
void bsp_fatal_halt( unsigned32 _error);
#define _CPU_Fatal_halt( _error ) bsp_fatal_halt( _error)
#else
#define _CPU_Fatal_halt( _error)\
{ \
asm volatile("mov.l %0,r0"::"m" (_error)); \
asm volatile("trapa #34"); \
}
#endif
/* end of Fatal Error manager macros */
/* Bitfield handler macros */
/*
* This routine sets _output to the bit number of the first bit
* set in _value. _value is of CPU dependent type Priority_Bit_map_control.
* This type may be either 16 or 32 bits wide although only the 16
* least significant bits will be used.
*
* There are a number of variables in using a "find first bit" type
* instruction.
*
* (1) What happens when run on a value of zero?
* (2) Bits may be numbered from MSB to LSB or vice-versa.
* (3) The numbering may be zero or one based.
* (4) The "find first bit" instruction may search from MSB or LSB.
*
* RTEMS guarantees that (1) will never happen so it is not a concern.
* (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
* _CPU_Priority_bits_index(). These three form a set of routines
* which must logically operate together. Bits in the _value are
* set and cleared based on masks built by _CPU_Priority_mask().
* The basic major and minor values calculated by _Priority_Major()
* and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
* to properly range between the values returned by the "find first bit"
* instruction. This makes it possible for _Priority_Get_highest() to
* calculate the major and directly index into the minor table.
* This mapping is necessary to ensure that 0 (a high priority major/minor)
* is the first bit found.
*
* This entire "find first bit" and mapping process depends heavily
* on the manner in which a priority is broken into a major and minor
* components with the major being the 4 MSB of a priority and minor
* the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
* priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
* to the lowest priority.
*
* If your CPU does not have a "find first bit" instruction, then
* there are ways to make do without it. Here are a handful of ways
* to implement this in software:
*
* - a series of 16 bit test instructions
* - a "binary search using if's"
* - _number = 0
* if _value > 0x00ff
* _value >>=8
* _number = 8;
*
* if _value > 0x0000f
* _value >=8
* _number += 4
*
* _number += bit_set_table[ _value ]
*
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*/
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
extern unsigned8 _bit_set_table[];
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
{ \
_output = 0;\
if(_value > 0x00ff) \
{ _value >>= 8; _output = 8; } \
if(_value > 0x000f) \
{ _output += 4; _value >>= 4; } \
_output += _bit_set_table[ _value]; }
#endif
/* end of Bitfield handler macros */
/*
* This routine builds the mask which corresponds to the bit fields
* as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_Mask( _bit_number ) \
( 1 << (_bit_number) )
#endif
/*
* This routine translates the bit numbers returned by
* _CPU_Bitfield_Find_first_bit() into something suitable for use as
* a major or minor component of a priority. See the discussion
* for that routine.
*/
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
#define _CPU_Priority_bits_index( _priority ) \
(_priority)
#endif
/* end of Priority handler macros */
/* functions */
/*
* _CPU_Initialize
*
* This routine performs CPU dependent initialization.
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_ISR_install_vector
*
* This routine installs an interrupt vector.
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
/*
* _CPU_Install_interrupt_stack
*
* This routine installs the hardware interrupt stack pointer.
*
* NOTE: It needs only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
* is TRUE.
*/
void _CPU_Install_interrupt_stack( void );
/*
* _CPU_Thread_Idle_body
*
* This routine is the CPU dependent IDLE thread body.
*
* NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
* is TRUE.
*/
void _CPU_Thread_Idle_body( void );
/*
* _CPU_Context_switch
*
* This routine switches from the run context to the heir context.
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
);
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*/
void _CPU_Context_restore(
Context_Control *new_context
);
/*
* _CPU_Context_save_fp
*
* This routine saves the floating point context passed to it.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
);
/*
* _CPU_Context_restore_fp
*
* This routine restores the floating point context passed to it.
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
);
#ifdef __cplusplus
}
#endif
#endif

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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/shtypes.h>
extern void __ISR_Handler( unsigned32 vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif

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c/src/exec/score/cpu/sh/rtems/score/iosh7030.h Normal file
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffff5F /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

223
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffff5F /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/shtypes.h>
extern void __ISR_Handler( unsigned32 vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif

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/* sh.h
*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _sh_h
#define _sh_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "SH" family.
*
* It does this by setting variables to indicate which implementation
* dependent features are present in a particular member of the family.
*/
#if defined(sh7032)
#define CPU_MODEL_NAME "SH 7032"
#define SH_HAS_FPU 0
/*
* If the following macro is set to 0 there will be no software irq stack
*/
#define SH_HAS_SEPARATE_STACKS 1
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "Hitachi SH"
#ifndef ASM
/*
* Mask for disabling interrupts
*/
#define SH_IRQDIS_VALUE 0xf0
#define sh_disable_interrupts( _level ) \
asm volatile ( \
"stc sr,%0\n\t" \
"ldc %1,sr\n\t"\
: "=r" (_level ) \
: "r" (SH_IRQDIS_VALUE) );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
"nop\n\t" \
:: "r" (_level) );
/*
* This temporarily restores the interrupt to _level before immediately
* disabling them again. This is used to divide long RTEMS critical
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
"ldc %1,sr\n\t" \
"nop\n\t" \
"ldc %0,sr\n\t" \
"nop\n\t" \
: : "r" (SH_IRQDIS_VALUE), "r" (_level) );
#define sh_get_interrupt_level( _level ) \
{ \
register unsigned32 _tmpsr ; \
\
asm volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
_level = (_tmpsr & 0xf0) >> 4 ; \
}
#define sh_set_interrupt_level( _newlevel ) \
{ \
register unsigned32 _tmpsr; \
\
asm volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
_tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
asm volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
}
/*
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*/
static inline unsigned int sh_swap_u32(
unsigned int value
)
{
register unsigned int swapped;
asm volatile (
"swap.b %1,%0; "
"swap.w %0,%0; "
"swap.b %0,%0"
: "=r" (swapped)
: "r" (value) );
return( swapped );
}
static inline unsigned int sh_swap_u16(
unsigned int value
)
{
register unsigned int swapped ;
asm volatile ( "swap.b %1,%0" : "=r" (swapped) : "r" (value) );
return( swapped );
}
#define CPU_swap_u32( value ) sh_swap_u32( value )
#define CPU_swap_u16( value ) sh_swap_u16( value )
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*
* Since we don't have a real time clock, this is a very rough
* approximation, assuming that each cycle of the delay loop takes
* approx. 4 machine cycles.
*
* e.g.: MHZ = 20 => 5e-8 secs per instruction
* => 4 * 5e-8 secs per delay loop
*/
#define sh_delay( microseconds ) \
{ register unsigned int _delay = (microseconds) * (MHZ / 4 ); \
asm volatile ( \
"0: add #-1,%0\n \
nop\n \
cmp/pl %0\n \
bt 0b\
nop" \
:: "r" (_delay) ); \
}
#define CPU_delay( microseconds ) sh_delay( microseconds )
extern unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio );
#endif /* !ASM */
#ifdef __cplusplus
}
#endif
#endif

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/*
* These are some macros to access memory mapped devices
* on the SH7000-architecture.
*
* Inspired from the linux kernel's include/asm/io.h
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1996-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef _asm_io_h
#define _asm_io_h
#define readb(addr) (*(volatile unsigned char *) (addr))
#define readw(addr) (*(volatile unsigned short *) (addr))
#define readl(addr) (*(volatile unsigned int *) (addr))
#define read8(addr) (*(volatile unsigned8 *) (addr))
#define read16(addr) (*(volatile unsigned16 *) (addr))
#define read32(addr) (*(volatile unsigned32 *) (addr))
#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
#define write8(b,addr) ((*(volatile unsigned8 *) (addr)) = (b))
#define write16(b,addr) ((*(volatile unsigned16 *) (addr)) = (b))
#define write32(b,addr) ((*(volatile unsigned32 *) (addr)) = (b))
#define inb(addr) readb(addr)
#define outb(b,addr) writeb(b,addr)
#endif

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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_TYPES_h
#define __CPU_SH_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned16 boolean; /* Boolean value, external */
/* data bus has 16 bits */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void sh_isr;
typedef void ( *sh_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif

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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_SH_TYPES_h
#define __CPU_SH_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned16 boolean; /* Boolean value, external */
/* data bus has 16 bits */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void sh_isr;
typedef void ( *sh_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu cpu_asm cpu_isps rtems
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES =
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h sparctypes.h sparc.h
H_FILES=$(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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c/src/exec/score/cpu/sparc/rtems/score/sparc.h Normal file
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/* sparc.h
*
* This include file contains information pertaining to the SPARC
* processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
*/
#ifndef _INCLUDE_SPARC_h
#define _INCLUDE_SPARC_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "sparc" family. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*
* Currently recognized feature flags:
*
* + SPARC_HAS_FPU
* 0 - no HW FPU
* 1 - has HW FPU (assumed to be compatible w/90C602)
*
* + SPARC_HAS_BITSCAN
* 0 - does not have scan instructions
* 1 - has scan instruction (not currently implemented)
*
* + SPARC_NUMBER_OF_REGISTER_WINDOWS
* 8 is the most common number supported by SPARC implementations.
* SPARC_PSR_CWP_MASK is derived from this value.
*
* + SPARC_HAS_LOW_POWER_MODE
* 0 - does not have low power mode support (or not supported)
* 1 - has low power mode and thus a CPU model dependent idle task.
*
*/
#if defined(erc32)
#define CPU_MODEL_NAME "erc32"
#define SPARC_HAS_FPU 1
#define SPARC_HAS_BITSCAN 0
#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
#define SPARC_HAS_LOW_POWER_MODE 1
#else
#error "Unsupported CPU Model"
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "SPARC"
/*
* Miscellaneous constants
*/
/*
* PSR masks and starting bit positions
*
* NOTE: Reserved bits are ignored.
*/
#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */
#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */
#else
#error "Unsupported number of register windows for this cpu"
#endif
#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
#ifndef ASM
/*
* Standard nop
*/
#define nop() \
do { \
asm volatile ( "nop" ); \
} while ( 0 )
/*
* Get and set the PSR
*/
#define sparc_get_psr( _psr ) \
do { \
(_psr) = 0; \
asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
} while ( 0 )
#define sparc_set_psr( _psr ) \
do { \
asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
nop(); \
nop(); \
nop(); \
} while ( 0 )
/*
* Get and set the TBR
*/
#define sparc_get_tbr( _tbr ) \
do { \
(_tbr) = 0; /* to avoid unitialized warnings */ \
asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
#define sparc_set_tbr( _tbr ) \
do { \
asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
} while ( 0 )
/*
* Get and set the WIM
*/
#define sparc_get_wim( _wim ) \
do { \
asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
} while ( 0 )
#define sparc_set_wim( _wim ) \
do { \
asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \
nop(); \
nop(); \
nop(); \
} while ( 0 )
/*
* Get and set the Y
*/
#define sparc_get_y( _y ) \
do { \
asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
#define sparc_set_y( _y ) \
do { \
asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
/*
* Manipulate the interrupt level in the psr
*
*/
#define sparc_disable_interrupts( _level ) \
do { \
register unsigned int _newlevel; \
\
sparc_get_psr( _level ); \
(_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
sparc_set_psr( _newlevel ); \
} while ( 0 )
#define sparc_enable_interrupts( _level ) \
do { \
unsigned int _tmp; \
\
sparc_get_psr( _tmp ); \
_tmp &= ~SPARC_PSR_PIL_MASK; \
_tmp |= (_level) & SPARC_PSR_PIL_MASK; \
sparc_set_psr( _tmp ); \
} while ( 0 )
#define sparc_flash_interrupts( _level ) \
do { \
register unsigned32 _ignored = 0; \
\
sparc_enable_interrupts( (_level) ); \
sparc_disable_interrupts( _ignored ); \
} while ( 0 )
#define sparc_set_interrupt_level( _new_level ) \
do { \
register unsigned32 _new_psr_level = 0; \
\
sparc_get_psr( _new_psr_level ); \
_new_psr_level &= ~SPARC_PSR_PIL_MASK; \
_new_psr_level |= \
(((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
sparc_set_psr( _new_psr_level ); \
} while ( 0 )
#define sparc_get_interrupt_level( _level ) \
do { \
register unsigned32 _psr_level = 0; \
\
sparc_get_psr( _psr_level ); \
(_level) = \
(_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
} while ( 0 )
#endif
#ifdef __cplusplus
}
#endif
#endif /* ! _INCLUDE_SPARC_h */
/* end of include file */

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/* sparctypes.h
*
* This include file contains type definitions pertaining to the
* SPARC processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
*/
#ifndef __SPARC_TYPES_h
#define __SPARC_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void sparc_isr;
typedef void ( *sparc_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* sparctypes.h
*
* This include file contains type definitions pertaining to the
* SPARC processor family.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
*/
#ifndef __SPARC_TYPES_h
#define __SPARC_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void sparc_isr;
typedef void ( *sparc_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES = asm.h erc32.h
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES = cpu_asm rtems
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/directory.cfg
SUB_DIRS = score

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#
# $Id$
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
BUILT_SOURCES = unixsize.h
# C source names, if any, go here -- minus the .c
C_PIECES=
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES=cpu.h unixtypes.h unix.h
H_FILES=$(H_PIECES:%=$(srcdir)/%) unixsize.h
# Assembly source names, if any, go here -- minus the .S
S_PIECES=
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES +=
CPPFLAGS +=
CFLAGS +=
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
unixsize.h: $(GENSIZE) cpu.h
$(RM) $@
$(GENSIZE) > $@
$(CHMOD) -w $@
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS +=
CLOBBER_ADDITIONS += $(BUILT_SOURCES)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
all: install-headers
install-headers: ${H_FILES}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)/rtems/score
preinstall: install-headers

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/* unixtypes.h
*
* This include file contains type definitions which are appropriate
* for a typical modern UNIX box using GNU C for the RTEMS simulator.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __UNIX_TYPES_h
#define __UNIX_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* some C++ compilers (eg: HP's) don't do 'signed' or 'volatile'
*/
#if defined(__cplusplus) && !defined(__GNUC__)
#define signed
#define volatile
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
/*
* some C++ compilers (eg: HP's) don't do 'long long'
*/
#if defined(__GNUC__)
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef signed long long signed64; /* 64 bit signed integer */
#endif
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void unix_isr;
typedef unix_isr ( *unix_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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/* unix.h
*
* This include file contains the definitions required by RTEMS
* which are typical for a modern UNIX computer using GCC.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __UNIX_h
#define __UNIX_h
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "unix"
* family when executing in protected mode. It does
* this by setting variables to indicate which implementation
* dependent features are present in a particular member
* of the family.
*/
#if defined(hpux)
#define CPU_MODEL_NAME "HP-UX"
#elif defined(solaris2)
#define CPU_MODEL_NAME "Solaris"
#elif defined(__linux__)
#define CPU_MODEL_NAME "Linux"
#elif defined(linux)
#define CPU_MODEL_NAME "Linux"
#elif defined(__FreeBSD__)
#define CPU_MODEL_NAME "FreeBSD"
#else
#error "Unsupported CPU Model"
#endif
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */

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/* unixtypes.h
*
* This include file contains type definitions which are appropriate
* for a typical modern UNIX box using GNU C for the RTEMS simulator.
*
* COPYRIGHT (c) 1989-1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __UNIX_TYPES_h
#define __UNIX_TYPES_h
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* some C++ compilers (eg: HP's) don't do 'signed' or 'volatile'
*/
#if defined(__cplusplus) && !defined(__GNUC__)
#define signed
#define volatile
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed char signed8; /* 8-bit signed integer */
typedef signed short signed16; /* 16-bit signed integer */
typedef signed int signed32; /* 32-bit signed integer */
/*
* some C++ compilers (eg: HP's) don't do 'long long'
*/
#if defined(__GNUC__)
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef signed long long signed64; /* 64 bit signed integer */
#endif
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void unix_isr;
typedef unix_isr ( *unix_isr_entry )( void );
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/* end of include file */

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#
# $Id$
#
# *** NOTE *** This Makefile violates RTEMS Makefile standards.
# This Makefile picks up sources from outside this directory
# and installs relocatible objects outside of this directory.
# This behavior is a work-around for RTEMS Makefile's missing
# ability to compile inside of directories containing subdirectories.
# This directory will disapear once automake will be introduced.
#
@SET_MAKE@
srcdir = @srcdir@
VPATH = @srcdir@/..
RTEMS_ROOT = @top_srcdir@
PROJECT_ROOT = @PROJECT_ROOT@
RELS=../$(ARCH)/rtems-cpu.rel
# C source names, if any, go here -- minus the .c
C_PIECES = cpu
C_FILES=$(C_PIECES:%=%.c)
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
H_PIECES =
H_FILES=$(H_PIECES:%=$(srcdir)/../%)
# Assembly source names, if any, go here -- minus the .S
S_PIECES =
S_FILES=$(S_PIECES:%=%.S)
S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o)
SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES)
OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
include $(RTEMS_ROOT)/make/leaf.cfg
#
# (OPTIONAL) Add local stuff here using +=
#
DEFINES += -DCPU_SYNC_IO $(LIBC_DEFINES)
CPPFLAGS += -I$(srcdir)/..
CFLAGS += $(CFLAGS_OS_V)
LD_PATHS +=
LD_LIBS +=
LDFLAGS +=
#
# Add your list of files to delete here. The config files
# already know how to delete some stuff, so you may want
# to just run 'make clean' first to see what gets missed.
# 'make clobber' already includes 'make clean'
#
CLEAN_ADDITIONS += ../$(ARCH)
CLOBBER_ADDITIONS +=
../$(ARCH)/rtems-cpu.rel: $(OBJS)
test -d ../$(ARCH) || mkdir ../$(ARCH)
$(make-rel)
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
# Install the program(s), appending _g or _p as appropriate.
# for include files, just use $(INSTALL)
install: all
preinstall: ${ARCH}
$(INSTALL) -m 444 ${H_FILES} $(PROJECT_INCLUDE)

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c/src/lib/libcpu/sh/sh7032/include/iosh7032.h Normal file
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/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __IOSH7030_H
#define __IOSH7030_H
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
* 16 bit == short ( readw, writew, read16, write16 )
* 32 bit == long ( readl, writel, read32, write32 )
*/
#define SCI0_SMR 0x05fffec0 /* char */
#define SCI0_BRR 0x05fffec1 /* char */
#define SCI0_SCR 0x05fffec2 /* char */
#define SCI0_TDR 0x05fffec3 /* char */
#define SCI0_SSR 0x05fffec4 /* char */
#define SCI0_RDR 0x05fffec5 /* char */
#define SCI1_SMR 0x05fffec8 /* char */
#define SCI1_BRR 0x05fffec9 /* char */
#define SCI1_SCR 0x05fffeca /* char */
#define SCI1_TDR 0x05fffecb /* char */
#define SCI1_SSR 0x05fffecc /* char */
#define SCI1_RDR 0x05fffecd /* char */
#define ADDRAH 0x05fffee0 /* char */
#define ADDRAL 0x05fffee1 /* char */
#define ADDRBH 0x05fffee2 /* char */
#define ADDRBL 0x05fffee3 /* char */
#define ADDRCH 0x05fffee4 /* char */
#define ADDRCL 0x05fffee5 /* char */
#define ADDRDH 0x05fffee6 /* char */
#define ADDRDL 0x05fffee7 /* char */
#define AD_DRA 0x05fffee0 /* short */
#define AD_DRB 0x05fffee2 /* short */
#define AD_DRC 0x05fffee4 /* short */
#define AD_DRD 0x05fffee6 /* short */
#define ADCSR 0x05fffee8 /* char */
#define ADCR 0x05fffee9 /* char */
/*ITU SHARED*/
#define ITU_TSTR 0x05ffff00 /* char */
#define ITU_TSNC 0x05ffff01 /* char */
#define ITU_TMDR 0x05ffff02 /* char */
#define ITU_TFCR 0x05ffff03 /* char */
/*ITU CHANNEL 0*/
#define ITU_TCR0 0x05ffff04 /* char */
#define ITU_TIOR0 0x05ffff05 /* char */
#define ITU_TIER0 0x05ffff06 /* char */
#define ITU_TSR0 0x05ffff07 /* char */
#define ITU_TCNT0 0x05ffff08 /* short */
#define ITU_GRA0 0x05ffff0a /* short */
#define ITU_GRB0 0x05ffff0c /* short */
/*ITU CHANNEL 1*/
#define ITU_TCR1 0x05ffff0E /* char */
#define ITU_TIOR1 0x05ffff0F /* char */
#define ITU_TIER1 0x05ffff10 /* char */
#define ITU_TSR1 0x05ffff11 /* char */
#define ITU_TCNT1 0x05ffff12 /* short */
#define ITU_GRA1 0x05ffff14 /* short */
#define ITU_GRB1 0x05ffff16 /* short */
/*ITU CHANNEL 2*/
#define ITU_TCR2 0x05ffff18 /* char */
#define ITU_TIOR2 0x05ffff19 /* char */
#define ITU_TIER2 0x05ffff1A /* char */
#define ITU_TSR2 0x05ffff1B /* char */
#define ITU_TCNT2 0x05ffff1C /* short */
#define ITU_GRA2 0x05ffff1E /* short */
#define ITU_GRB2 0x05ffff20 /* short */
/*ITU CHANNEL 3*/
#define ITU_TCR3 0x05ffff22 /* char */
#define ITU_TIOR3 0x05ffff23 /* char */
#define ITU_TIER3 0x05ffff24 /* char */
#define ITU_TSR3 0x05ffff25 /* char */
#define ITU_TCNT3 0x05ffff26 /* short */
#define ITU_GRA3 0x05ffff28 /* short */
#define ITU_GRB3 0x05ffff2A /* short */
#define ITU_BRA3 0x05ffff2C /* short */
#define ITU_BRB3 0x05ffff2E /* short */
/*ITU CHANNELS 0-4 SHARED*/
#define ITU_TOCR 0x05ffff31 /* char */
/*ITU CHANNEL 4*/
#define ITU_TCR4 0x05ffff32 /* char */
#define ITU_TIOR4 0x05ffff33 /* char */
#define ITU_TIER4 0x05ffff34 /* char */
#define ITU_TSR4 0x05ffff35 /* char */
#define ITU_TCNT4 0x05ffff36 /* short */
#define ITU_GRA4 0x05ffff38 /* short */
#define ITU_GRB4 0x05ffff3A /* short */
#define ITU_BRA4 0x05ffff3C /* short */
#define ITU_BRB4 0x05ffff3E /* short */
/*DMAC CHANNELS 0-3 SHARED*/
#define DMAOR 0x05ffff48 /* short */
/*DMAC CHANNEL 0*/
#define DMA_SAR0 0x05ffff40 /* long */
#define DMA_DAR0 0x05ffff44 /* long */
#define DMA_TCR0 0x05ffff4a /* short */
#define DMA_CHCR0 0x05ffff4e /* short */
/*DMAC CHANNEL 1*/
#define DMA_SAR1 0x05ffff50 /* long */
#define DMA_DAR1 0x05ffff54 /* long */
#define DMA_TCR1 0x05fffF5a /* short */
#define DMA_CHCR1 0x05ffff5e /* short */
/*DMAC CHANNEL 3*/
#define DMA_SAR3 0x05ffff60 /* long */
#define DMA_DAR3 0x05ffff64 /* long */
#define DMA_TCR3 0x05fffF6a /* short */
#define DMA_CHCR3 0x05ffff6e /* short */
/*DMAC CHANNEL 4*/
#define DMA_SAR4 0x05ffff70 /* long */
#define DMA_DAR4 0x05ffff74 /* long */
#define DMA_TCR4 0x05fffF7a /* short */
#define DMA_CHCR4 0x05ffff7e /* short */
/*INTC*/
#define INTC_IPRA 0x05ffff84 /* short */
#define INTC_IPRB 0x05ffff86 /* short */
#define INTC_IPRC 0x05ffff88 /* short */
#define INTC_IPRD 0x05ffff8A /* short */
#define INTC_IPRE 0x05ffff8C /* short */
#define INTC_ICR 0x05ffff8E /* short */
/*UBC*/
#define UBC_BARH 0x05ffff90 /* short */
#define UBC_BARL 0x05ffff92 /* short */
#define UBC_BAMRH 0x05ffff94 /* short */
#define UBC_BAMRL 0x05ffff96 /* short */
#define UBC_BBR 0x05ffff98 /* short */
/*BSC*/
#define BSC_BCR 0x05ffffA0 /* short */
#define BSC_WCR1 0x05ffffA2 /* short */
#define BSC_WCR2 0x05ffffA4 /* short */
#define BSC_WCR3 0x05ffffA6 /* short */
#define BSC_DCR 0x05ffffA8 /* short */
#define BSC_PCR 0x05ffffAA /* short */
#define BSC_RCR 0x05ffffAC /* short */
#define BSC_RTCSR 0x05ffffAE /* short */
#define BSC_RTCNT 0x05ffffB0 /* short */
#define BSC_RTCOR 0x05ffffB2 /* short */
/*WDT*/
#define WDT_TCSR 0x05ffffB8 /* char */
#define WDT_TCNT 0x05ffffB9 /* char */
#define WDT_RSTCSR 0x05ffffBB /* char */
/*POWER DOWN STATE*/
#define PDT_SBYCR 0x05ffffBC /* char */
/*PORT A*/
#define PADR 0x05ffffC0 /* short */
/*PORT B*/
#define PBDR 0x05ffffC2 /* short */
/*PORT C*/
#define PCDR 0x05ffffD0 /* short */
/*PFC*/
#define PFC_PAIOR 0x05ffffC4 /* short */
#define PFC_PBIOR 0x05ffffC6 /* short */
#define PFC_PACR1 0x05ffffC8 /* short */
#define PFC_PACR2 0x05ffffCA /* short */
#define PFC_PBCR1 0x05ffffCC /* short */
#define PFC_PBCR2 0x05ffffCE /* short */
#define PFC_CASCR 0x05ffffEE /* short */
/*TPC*/
#define TPC_TPMR 0x05ffffF0 /* short */
#define TPC_TPCR 0x05ffffF1 /* short */
#define TPC_NDERH 0x05ffffF2 /* short */
#define TPC_NDERL 0x05ffffF3 /* short */
#define TPC_NDRB 0x05ffffF4 /* char */
#define TPC_NDRA 0x05ffff5F /* char */
#define TPC_NDRB1 0x05ffffF6 /* char */
#define TPC_NDRA1 0x05ffffF7 /* char */
#endif

165
c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h Normal file
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@@ -0,0 +1,165 @@
/*
* This include file contains information pertaining to the Hitachi SH
* processor.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __CPU_ISPS_H
#define __CPU_ISPS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems/score/shtypes.h>
extern void __ISR_Handler( unsigned32 vector );
/*
* interrupt vector table offsets
*/
#define NMI_ISP_V 11
#define USB_ISP_V 12
#define IRQ0_ISP_V 64
#define IRQ1_ISP_V 65
#define IRQ2_ISP_V 66
#define IRQ3_ISP_V 67
#define IRQ4_ISP_V 68
#define IRQ5_ISP_V 69
#define IRQ6_ISP_V 70
#define IRQ7_ISP_V 71
#define DMA0_ISP_V 72
#define DMA1_ISP_V 74
#define DMA2_ISP_V 76
#define DMA3_ISP_V 78
#define IMIA0_ISP_V 80
#define IMIB0_ISP_V 81
#define OVI0_ISP_V 82
#define IMIA1_ISP_V 84
#define IMIB1_ISP_V 85
#define OVI1_ISP_V 86
#define IMIA2_ISP_V 88
#define IMIB2_ISP_V 89
#define OVI2_ISP_V 90
#define IMIA3_ISP_V 92
#define IMIB3_ISP_V 93
#define OVI3_ISP_V 94
#define IMIA4_ISP_V 96
#define IMIB4_ISP_V 97
#define OVI4_ISP_V 98
#define ERI0_ISP_V 100
#define RXI0_ISP_V 101
#define TXI0_ISP_V 102
#define TEI0_ISP_V 103
#define ERI1_ISP_V 104
#define RXI1_ISP_V 105
#define TXI1_ISP_V 106
#define TEI1_ISP_V 107
#define PRT_ISP_V 108
#define ADU_ISP_V 109
#define WDT_ISP_V 112
#define DREF_ISP_V 113
/* dummy ISP */
extern void _dummy_isp( void );
/* Non Maskable Interrupt */
extern void _nmi_isp( void );
/* User Break Controller */
extern void _usb_isp( void );
/* External interrupts 0-7 */
extern void _irq0_isp( void );
extern void _irq1_isp( void );
extern void _irq2_isp( void );
extern void _irq3_isp( void );
extern void _irq4_isp( void );
extern void _irq5_isp( void );
extern void _irq6_isp( void );
extern void _irq7_isp( void );
/* DMA - Controller */
extern void _dma0_isp( void );
extern void _dma1_isp( void );
extern void _dma2_isp( void );
extern void _dma3_isp( void );
/* Interrupt Timer Unit */
/* Timer 0 */
extern void _imia0_isp( void );
extern void _imib0_isp( void );
extern void _ovi0_isp( void );
/* Timer 1 */
extern void _imia1_isp( void );
extern void _imib1_isp( void );
extern void _ovi1_isp( void );
/* Timer 2 */
extern void _imia2_isp( void );
extern void _imib2_isp( void );
extern void _ovi2_isp( void );
/* Timer 3 */
extern void _imia3_isp( void );
extern void _imib3_isp( void );
extern void _ovi3_isp( void );
/* Timer 4 */
extern void _imia4_isp( void );
extern void _imib4_isp( void );
extern void _ovi4_isp( void );
/* seriell interfaces */
extern void _eri0_isp( void );
extern void _rxi0_isp( void );
extern void _txi0_isp( void );
extern void _tei0_isp( void );
extern void _eri1_isp( void );
extern void _rxi1_isp( void );
extern void _txi1_isp( void );
extern void _tei1_isp( void );
/* Parity Control Unit of the Bus State Controllers */
extern void _prt_isp( void );
/* ADC */
extern void _adu_isp( void );
/* Watchdog Timer */
extern void _wdt_isp( void );
/* DRAM refresh control unit of bus state controller */
extern void _dref_isp( void );
#ifdef __cplusplus
}
#endif
#endif