forked from Imagelibrary/rtems
arm_rtl22xx: added new doxygen
This commit is contained in:
Daniel Ramirez
committed by
Gedare Bloom
Gedare Bloom
parent
c0f731dfd7
commit
78e529a660
@@ -1,89 +1,187 @@
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/*
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* Definitions for LPC22xx/LPC21xx
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/**
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* @file
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* @ingroup rtl22xx_uart
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* @brief UART support.
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*/
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#ifndef LPC22XX_UART_H
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#define LPC22XX_UART_H
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/**
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* @defgroup rtl22xx_uart UART Support
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* @ingroup arm_rtl22xx
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* @brief UART (Universal Asynchronous Reciever/Transmitter) Support
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* @{
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*/
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#define FIFODEEP 16
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#define BD115200 115200
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#define BD38400 38400
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#define BD9600 9600
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#define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */
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#define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */
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#define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */
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#define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */
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/** @brief PINSEL0 Value for UART0 */
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#define U0_PINSEL (0x00000005)
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/** @brief PINSEL0 Mask for UART0 */
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#define U0_PINMASK (0x0000000F)
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/** @brief PINSEL0 Value for UART1 */
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#define U1_PINSEL (0x00050000)
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/** @brief PINSEL0 Mask for UART1 */
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#define U1_PINMASK (0x000F0000)
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/**
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* @name Uart line control register bit descriptions
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* @{
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*/
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/* Uart line control register bit descriptions */
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#define LCR_WORDLENTH_BIT 0
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#define LCR_STOPBITSEL_BIT 2
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#define LCR_PARITYENBALE_BIT 3
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#define LCR_PARITYSEL_BIT 4
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#define LCR_BREAKCONTROL_BIT 6
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#define LCR_DLAB_BIT 7
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// Line Control Register bit definitions
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#define ULCR_CHAR_5 (0 << 0) // 5-bit character length
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#define ULCR_CHAR_6 (1 << 0) // 6-bit character length
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#define ULCR_CHAR_7 (2 << 0) // 7-bit character length
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#define ULCR_CHAR_8 (3 << 0) // 8-bit character length
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#define ULCR_STOP_0 (0 << 2) // no stop bits
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#define ULCR_STOP_1 (1 << 2) // 1 stop bit
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#define ULCR_PAR_NO (0 << 3) // No Parity
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#define ULCR_PAR_ODD (1 << 3) // Odd Parity
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#define ULCR_PAR_EVEN (3 << 3) // Even Parity
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#define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity
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#define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty
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#define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition
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#define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access
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// Modem Control Register bit definitions
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#define UMCR_DTR (1 << 0) // Data Terminal Ready
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#define UMCR_RTS (1 << 1) // Request To Send
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#define UMCR_LB (1 << 4) // Loopback
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// Line Status Register bit definitions
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#define ULSR_RDR (1 << 0) // Receive Data Ready
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#define ULSR_OE (1 << 1) // Overrun Error
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#define ULSR_PE (1 << 2) // Parity Error
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#define ULSR_FE (1 << 3) // Framing Error
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#define ULSR_BI (1 << 4) // Break Interrupt
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#define ULSR_THRE (1 << 5) // Transmit Holding Register Empty
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#define ULSR_TEMT (1 << 6) // Transmitter Empty
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#define ULSR_RXFE (1 << 7) // Error in Receive FIFO
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/** @} */
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/**
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* @name Line Control Register bit definitions
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* @{
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*/
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/** @brief 5-bit character length */
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#define ULCR_CHAR_5 (0 << 0)
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/** @brief 6-bit character length */
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#define ULCR_CHAR_6 (1 << 0)
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/** @brief 7-bit character length */
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#define ULCR_CHAR_7 (2 << 0)
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/** @brief 8-bit character length */
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#define ULCR_CHAR_8 (3 << 0)
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/** @brief no stop bits */
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#define ULCR_STOP_0 (0 << 2)
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/** @brief 1 stop bit */
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#define ULCR_STOP_1 (1 << 2)
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/** @brief No Parity */
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#define ULCR_PAR_NO (0 << 3)
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/** @brief Odd Parity */
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#define ULCR_PAR_ODD (1 << 3)
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/** @brief Even Parity */
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#define ULCR_PAR_EVEN (3 << 3)
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/** @brief MARK "1" Parity */
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#define ULCR_PAR_MARK (5 << 3)
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/** @brief SPACE "0" Paruty */
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#define ULCR_PAR_SPACE (7 << 3)
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/** @brief Output BREAK line condition */
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#define ULCR_BREAK_ENABLE (1 << 6)
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/** @brief Enable Divisor Latch Access */
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#define ULCR_DLAB_ENABLE (1 << 7)
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/** @} */
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/**
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* @name Modem Control Register bit definitions
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* @{
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*/
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/** @brief Data Terminal Ready */
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#define UMCR_DTR (1 << 0)
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/** @brief Request To Send */
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#define UMCR_RTS (1 << 1)
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/** @brief Loopback */
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#define UMCR_LB (1 << 4)
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/** @} */
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/**
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* @name Line Status Register bit definitions
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* @{
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*/
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/** @brief Receive Data Ready */
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#define ULSR_RDR (1 << 0)
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/** @brief Overrun Error */
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#define ULSR_OE (1 << 1)
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/** @brief Parity Error */
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#define ULSR_PE (1 << 2)
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/** @brief Framing Error */
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#define ULSR_FE (1 << 3)
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/** @brief Break Interrupt */
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#define ULSR_BI (1 << 4)
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/** @brief Transmit Holding Register Empty */
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#define ULSR_THRE (1 << 5)
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/** @brief Transmitter Empty */
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#define ULSR_TEMT (1 << 6)
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/** @brief Error in Receive FIFO */
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#define ULSR_RXFE (1 << 7)
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#define ULSR_ERR_MASK 0x1E
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// Modem Status Register bit definitions
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#define UMSR_DCTS (1 << 0) // Delta Clear To Send
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#define UMSR_DDSR (1 << 1) // Delta Data Set Ready
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#define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator
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#define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect
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#define UMSR_CTS (1 << 4) // Clear To Send
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#define UMSR_DSR (1 << 5) // Data Set Ready
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#define UMSR_RI (1 << 6) // Ring Indicator
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#define UMSR_DCD (1 << 7) // Data Carrier Detect
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/** @} */
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/**
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* @name Modem Status Register bit definitions
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* @{
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*/
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/** @brief Delta Clear To Send */
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#define UMSR_DCTS (1 << 0)
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/** @brief Delta Data Set Ready */
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#define UMSR_DDSR (1 << 1)
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/** @brief Trailing Edge Ring Indicator */
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#define UMSR_TERI (1 << 2)
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/** @brief Delta Data Carrier Detect */
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#define UMSR_DDCD (1 << 3)
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/** @brief Clear To Send */
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#define UMSR_CTS (1 << 4)
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/** @brief Data Set Ready */
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#define UMSR_DSR (1 << 5)
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/** @brief Ring Indicator */
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#define UMSR_RI (1 << 6)
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/** @brief Data Carrier Detect */
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#define UMSR_DCD (1 << 7)
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/** @} */
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/**
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* @name Uart Interrupt Identification
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* @{
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*/
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/* Uart Interrupt Identification */
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#define IIR_RSL 0x3
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#define IIR_RDA 0x2
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#define IIR_CTI 0x6
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#define IIR_THRE 0x1
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/* Uart Interrupt Enable Type*/
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/** @} */
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/**
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* @name Uart Interrupt Enable Type
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* @{
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*/
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#define IER_RBR 0x1
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#define IER_THRE 0x2
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#define IER_RLS 0x4
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/* Uart Receiver Errors*/
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/** @} */
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/**
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* @name Uart Receiver Errors
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* @{
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*/
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#define RC_FIFO_OVERRUN_ERR 0x1
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#define RC_OVERRUN_ERR 0x2
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#define RC_PARITY_ERR 0x4
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#define RC_FRAMING_ERR 0x8
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#define RC_BREAK_IND 0x10
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/** @} */
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typedef enum {
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UART0 = 0,
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UART1
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} LPC_UartChanel_t;
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/** @} */
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#endif
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@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup arm_rtl22xx
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* @brief Global BSP definitions.
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*/
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/*
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* Philips LPC22XX/LPC21xx BSP header file
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*
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@@ -17,6 +23,13 @@ extern "C" {
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#include <bspopts.h>
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#include <bsp/default-initial-extension.h>
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/**
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* @defgroup arm_rtl22xx RTL22XX Support
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* @ingroup bsp_arm
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* @brief RTL22XX Support Package
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* @{
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*/
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#define BSP_SMALL_MEMORY 1
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#include <rtems.h>
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@@ -30,39 +43,67 @@ extern "C" {
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/* cclk=cco/(2*P) */
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/* cco = cclk*2*P */
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/* system clk frequecy,<=60Mhz, defined in system configuration */
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/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
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#define LPC22xx_Fcclk CONFIG_ARM_CLK
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/* Fcco 156M~320Mhz*/
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/* system clk frequecy,<=60Mhz, defined in system configuration */
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/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
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#define LPC22xx_Fcclk CONFIG_ARM_CLK
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#define LPC22xx_Fcco LPC22xx_Fcclk * 4
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/*VPB clk frequency,1,1/2,1/4 times of Fcclk */
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/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */
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#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1
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/* Fcclk range: 10MHz ~ MCU allowed frequency */
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/**
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* @name Fcclk range: 10MHz ~ MCU allowed frequency
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* @{
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*/
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#define Fcclk_MIN 10000000L
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#define Fcclk_MAX 60000000L
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/* Fcco range: 156MHz ~ 320MHz */
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/** @} */
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/**
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* @name Fcco range: 156MHz ~ 320MHz
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* @{
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*/
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#define Fcco_MIN 156000000L
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#define Fcco_MAX 320000000L
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/** @} */
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#define PLLFEED_DATA1 0xAA
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#define PLLFEED_DATA2 0x55
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/* PLL PLLCON register bit descriptions */
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/**
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* @name PLL PLLCON register bit descriptions
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* @{
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*/
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#define PLLCON_ENABLE_BIT 0
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#define PLLCON_CONNECT_BIT 1
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/* PLL PLLSTAT register bit descriptions */
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/** @} */
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/**
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* @name PLL PLLSTAT register bit descriptions
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* @{
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*/
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#define PLLSTAT_ENABLE_BIT 8
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#define PLLSTAT_CONNECT_BIT 9
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#define PLLSTAT_LOCK_BIT 10
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/* PM Peripheral Type */
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/** @} */
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/**
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* @name PM Peripheral Type
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* @{
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*/
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#define PC_TIMER0 0x2
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#define PC_TIMER1 0x4
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#define PC_UART0 0x8
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@@ -72,73 +113,112 @@ extern "C" {
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#define PC_SPI0 0x100
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#define PC_RTC 0x200
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// OSC [Hz]
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/** @} */
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/** @brief OSC [Hz] */
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#define FOSC 11059200
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// Core clk [Hz]
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/** @brief Core clk [Hz] */
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#define FCCLK FOSC<<2
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/**
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* help file
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*/
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/* System configure, Fosc Fcclk Fcco Fpclk must be defined*/
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#define Fosc 11059200 // osc freq,10MHz~25MHz,
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// change to real one if needed
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#define Fcclk (Fosc << 2) //system freq 2^n time of Fosc(1~32) <=60MHZ
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#define Fcco (Fcclk <<2) //CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz
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#define Fpclk (Fcclk >>2) * 1 //VPB freq only(Fcclk / 4) 1~4
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* @name System Configure
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* @{
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*/
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/** @brief osc freq,10MHz~25MHz, change to a real one if needed */
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#define Fosc 11059200
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/** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */
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#define Fcclk (Fosc << 2)
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/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */
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#define Fcco (Fcclk <<2)
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/** @brief VPB freq only(Fcclk / 4) 1~4 */
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#define Fpclk (Fcclk >>2) * 1
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/* This was M. That is a BAD BAD public constant. I renamed it to
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* JOEL_M so it wouldn't conflict with user code. If you can find
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* a better name, fix this. But nothing I found uses it.
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*/
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/** @} */
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#define JOEL_M Fcclk / Fosc
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#define P_min Fcco_MIN / (2*Fcclk) + 1;
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#define P_max Fcco_MAX / (2*Fcclk);
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#define UART_BPS 115200
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// Time Precision time [us]
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/** @brief Time Precision time [us] */
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#define TIMER_PRECISION 10
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// I2C Speed [bit/s]
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/** @brief I2C Speed [bit/s] */
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#define I2CSPEED 20000 // 20 Kbit/s
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// Uarts buffers size
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/**
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* @name Uarts buffers size
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* @{
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*/
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#define RXBUFSIZE 32
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#define TXBUFSIZE 32
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// SPI Speed [bit/s]
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/** @} */
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/** @brief SPI Speed [bit/s] */
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#define SPISPEED 1500000 // 1.5 Mbit/s
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// SPI EEPROM CS pin (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
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/** @brief SPI EEPROM CS pin
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*
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* (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
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*/
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#define SPI_CS_PIN P0_13
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#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN
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// Flash definition
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/**
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* @name Flash definition
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* @{
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*/
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//#define FLASH_SIZE (0x200000-FLASH_BOOT) // Total area of Flash region in words 8 bit
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#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit
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/** @brief Total area of Flash region in words 8 bit */
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#define FLASH_SIZE (0x80000-FLASH_BOOT)
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//#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit
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#define FLASH_BEGIN 0x80000000
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#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) //First 0x8000 bytes reserved for boot loader etc.
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/** @brief First 0x8000 bytes reserved for boot loader etc. */
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#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT)
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// SRAM definition
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#define SRAM_SIZE 0x100000 // Total area of Flash region in words 8 bit
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#define SRAM_BASE 0x81000000 //First 0x8000 bytes reserved for boot loader etc.
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/** @} */
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// CS8900A definition
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/**
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* @name SRAM definition
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* @{
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*/
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/** @brief Total area of Flash region in words 8 bit */
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#define SRAM_SIZE 0x100000
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/** @brief First 0x8000 bytes reserved for boot loader etc. */
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#define SRAM_BASE 0x81000000
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/** @} */
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/** @brief CS8900A definition */
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#define CS8900A_BASE 0x82000000
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// RTL8019AS definition
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/** @brief RTL8019AS definition */
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#define RTL8019AS_BASE 0x82000000
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struct rtems_bsdnet_ifconfig;
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int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,
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int attaching);
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/*
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* Network driver configuration
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/**
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* @name Network driver configuration
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* @{
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*/
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#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
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#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
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/** @} */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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218
c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~
Normal file
218
c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~
Normal file
@@ -0,0 +1,218 @@
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/**
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* @file
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* @ingroup arm_rtl22xx
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* @brief Global BSP definitions.
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*/
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/*
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||||
* Philips LPC22XX/LPC21xx BSP header file
|
||||
*
|
||||
* by Ray,Xu <Rayx.cn@gmail.com>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
#ifndef _BSP_H
|
||||
#define _BSP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <bsp/default-initial-extension.h>
|
||||
|
||||
/**
|
||||
* @defgroup arm_rtl22xx RTL22XX Support
|
||||
* @ingroup bsp_arm
|
||||
* @brief RTL22XX Support Package
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BSP_SMALL_MEMORY 1
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/iosupp.h>
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/clockdrv.h>
|
||||
|
||||
#define BSP_FEATURE_IRQ_EXTENSION
|
||||
|
||||
#define CONFIG_ARM_CLK 60000000L
|
||||
/* cclk=cco/(2*P) */
|
||||
/* cco = cclk*2*P */
|
||||
|
||||
/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
|
||||
#define LPC22xx_Fcclk CONFIG_ARM_CLK
|
||||
|
||||
/* Fcco 156M~320Mhz*/
|
||||
/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
|
||||
#define LPC22xx_Fcclk CONFIG_ARM_CLK
|
||||
#define LPC22xx_Fcco LPC22xx_Fcclk * 4
|
||||
/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */
|
||||
#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @name Fcclk range: 10MHz ~ MCU allowed frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define Fcclk_MIN 10000000L
|
||||
#define Fcclk_MAX 60000000L
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Fcco range: 156MHz ~ 320MHz
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define Fcco_MIN 156000000L
|
||||
#define Fcco_MAX 320000000L
|
||||
|
||||
/** @} */
|
||||
|
||||
#define PLLFEED_DATA1 0xAA
|
||||
#define PLLFEED_DATA2 0x55
|
||||
|
||||
/**
|
||||
* @name PLL PLLCON register bit descriptions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PLLCON_ENABLE_BIT 0
|
||||
#define PLLCON_CONNECT_BIT 1
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PLL PLLSTAT register bit descriptions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PLLSTAT_ENABLE_BIT 8
|
||||
#define PLLSTAT_CONNECT_BIT 9
|
||||
#define PLLSTAT_LOCK_BIT 10
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PM Peripheral Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PC_TIMER0 0x2
|
||||
#define PC_TIMER1 0x4
|
||||
#define PC_UART0 0x8
|
||||
#define PC_UART1 0x10
|
||||
#define PC_PWM0 0x20
|
||||
#define PC_I2C 0x80
|
||||
#define PC_SPI0 0x100
|
||||
#define PC_RTC 0x200
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @brief OSC [Hz] */
|
||||
#define FOSC 11059200
|
||||
/** @brief Core clk [Hz] */
|
||||
#define FCCLK FOSC<<2
|
||||
|
||||
/**
|
||||
* @name System Configure
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define Fosc 11059200 /** @brief osc freq,10MHz~25MHz, change to a real one if needed */
|
||||
#define Fcclk (Fosc << 2) /** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */
|
||||
#define Fcco (Fcclk <<2) /** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */
|
||||
#define Fpclk (Fcclk >>2) * 1 /** @brief VPB freq only(Fcclk / 4) 1~4 */
|
||||
/* This was M. That is a BAD BAD public constant. I renamed it to
|
||||
* JOEL_M so it wouldn't conflict with user code. If you can find
|
||||
* a better name, fix this. But nothing I found uses it.
|
||||
*/
|
||||
|
||||
/** @} */
|
||||
|
||||
#define JOEL_M Fcclk / Fosc
|
||||
#define P_min Fcco_MIN / (2*Fcclk) + 1;
|
||||
#define P_max Fcco_MAX / (2*Fcclk);
|
||||
|
||||
#define UART_BPS 115200
|
||||
|
||||
/** @brief Time Precision time [us] */
|
||||
#define TIMER_PRECISION 10
|
||||
|
||||
/** @brief I2C Speed [bit/s] */
|
||||
#define I2CSPEED 20000 // 20 Kbit/s
|
||||
|
||||
/**
|
||||
* @name Uarts buffers size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RXBUFSIZE 32
|
||||
#define TXBUFSIZE 32
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @brief SPI Speed [bit/s] */
|
||||
#define SPISPEED 1500000 // 1.5 Mbit/s
|
||||
/** @brief SPI EEPROM CS pin
|
||||
*
|
||||
* (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
|
||||
*/
|
||||
#define SPI_CS_PIN P0_13
|
||||
#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN
|
||||
|
||||
/**
|
||||
* @name Flash definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
//#define FLASH_SIZE (0x200000-FLASH_BOOT) // Total area of Flash region in words 8 bit
|
||||
#define FLASH_SIZE (0x80000-FLASH_BOOT) /** @brief Total area of Flash region in words 8 bit */
|
||||
//#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit
|
||||
#define FLASH_BEGIN 0x80000000
|
||||
#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) /** @brief First 0x8000 bytes reserved for boot loader etc. */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SRAM definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SRAM_SIZE 0x100000 /** @brief Total area of Flash region in words 8 bit */
|
||||
#define SRAM_BASE 0x81000000 /** @brief First 0x8000 bytes reserved for boot loader etc. */
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @brief CS8900A definition */
|
||||
#define CS8900A_BASE 0x82000000
|
||||
/** @brief RTL8019AS definition */
|
||||
#define RTL8019AS_BASE 0x82000000
|
||||
|
||||
struct rtems_bsdnet_ifconfig;
|
||||
int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,
|
||||
int attaching);
|
||||
|
||||
/**
|
||||
* @name Network driver configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_H */
|
||||
Reference in New Issue
Block a user