Eliminate use of /*PAGE and clean up formatting

c/src/lib/libcpu/m68k/shared/misc/m68kidle.c

@@ -1,6 +1,12 @@
 /*
  *  Motorola MC68xxx Dependent Idle Body Source
  *
+ *  This kernel routine is the idle thread.  The idle thread runs any time
+ *  no other thread is ready to run.  This thread loops forever with
+ *  interrupts enabled.
+ */
+
+/*
  *  COPYRIGHT (c) 1989-2002.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -12,21 +18,6 @@
 #include <rtems/system.h>
 #include <rtems/score/thread.h>
 
-
-/*PAGE
- *
- *  _CPU_Thread_Idle_body
- *
- *  This kernel routine is the idle thread.  The idle thread runs any time
- *  no other thread is ready to run.  This thread loops forever with
- *  interrupts enabled.
- *
- *  Input parameters:
- *    ignored - this parameter is ignored
- *
- *  Output parameters:  NONE
- */
-
 void *_CPU_Thread_Idle_body( uintptr_t ignored )
 {
 #if defined(mcf5272)
@@ -35,7 +26,9 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
     __asm__ volatile( "nop" );
   }
 #else
-  for( ; ; )
-    __asm__ volatile( "stop #0x3000":::"cc" );  /* supervisor mode, all interrupts on */
+  for( ; ; ) {
+    /* supervisor mode, all interrupts on */
+    __asm__ volatile( "stop #0x3000":::"cc" );
+  }
 #endif
 }

c/src/lib/libcpu/powerpc/new-exceptions/cpu.c

@@ -1,7 +1,9 @@
 /*
  *  PowerPC CPU Dependent Source
- *
- *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ */
+
+/*
+ *  Author:  Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -40,23 +42,17 @@
 /*  _CPU_Initialize
  *
  *  This routine performs processor dependent initialization.
- *
- *  INPUT PARAMETERS: NONE
  */
-
 void _CPU_Initialize(void)
 {
-  /* Do nothing */
 #ifdef __ALTIVEC__
   _CPU_Initialize_altivec();
 #endif
 }
 
-/*PAGE
- *
+/*
  *  _CPU_Context_Initialize
  */
-
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
   uint32_t         *stack_base,

c/src/lib/libcpu/sparc64/shared/score/cpu.c

@@ -1,6 +1,8 @@
 /*
  *  SPARC-v9 Dependent Source
- *
+ */
+
+/*
  *  COPYRIGHT (c) 1989-2007.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -45,8 +47,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = {
 };
 
 
-/*PAGE
- *
+/*
  *  _CPU_ISR_Get_level
  *
  *  Input Parameters: NONE
@@ -54,7 +55,6 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = {
  *  Output Parameters:
  *    returns the current interrupt level (PIL field of the PSR)
  */
-
 uint32_t   _CPU_ISR_Get_level( void )
 {
   uint32_t   level;
@@ -64,8 +64,7 @@ uint32_t   _CPU_ISR_Get_level( void )
   return level;
 }
 
-/*PAGE
- *
+/*
  *  _CPU_ISR_install_raw_handler
  *
  *  This routine installs the specified handler as a "raw" non-executive
@@ -203,8 +202,7 @@ void _CPU_ISR_install_raw_handler(
 
 }
 
-/*PAGE
- *
+/*
  *  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
@@ -217,9 +215,7 @@ void _CPU_ISR_install_raw_handler(
  *
  *  Output parameters:
  *    *old_handler - former ISR for this vector number
- *
  */
-
 void _CPU_ISR_install_vector(
   uint64_t    vector,
   proc_ptr    new_handler,