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Patch from Eric Valette <valette@crf.canon.fr> to fix interrupt

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initialization typo and make i8259s_cache only accessed from C.
This commit is contained in:
Joel Sherrill
1999-08-03 13:52:59 +00:00
parent 26eff5c295
commit 783e8322d3
2 changed files with 3 additions and 5 deletions
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2
c/src/lib/libbsp/i386/pc386/startup/ldsegs.S
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@@ -139,8 +139,6 @@ next_step:
outb al, $0x21 /* is cascaded */ outb al, $0x21 /* is cascaded */
call SYM(delay) call SYM(delay)
movw $0xFFFB, SYM(i8259s_cache) /* set up same values in cache */
jmp SYM (_establish_stack) # return to the bsp entry code jmp SYM (_establish_stack) # return to the bsp entry code
/*-------------------------------------------------------------------------+ /*-------------------------------------------------------------------------+

6
c/src/lib/libbsp/i386/shared/irq/irq.c
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@@ -53,7 +53,7 @@ static rtems_irq_connect_data* rtems_hdl_tbl;
* while upper bits are interrupt on the slave PIC. * while upper bits are interrupt on the slave PIC.
* This cache is initialized in ldseg.s * This cache is initialized in ldseg.s
*/ */
rtems_i8259_masks i8259s_cache; rtems_i8259_masks i8259s_cache = 0xffbf;
/*-------------------------------------------------------------------------+ /*-------------------------------------------------------------------------+
| Function: BSP_irq_disable_at_i8259s | Function: BSP_irq_disable_at_i8259s
@@ -83,7 +83,7 @@ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine)
} }
else else
{ {
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
} }
_CPU_ISR_Enable (level); _CPU_ISR_Enable (level);
@@ -118,7 +118,7 @@ int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine)
} }
else else
{ {
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
} }
_CPU_ISR_Enable (level); _CPU_ISR_Enable (level);