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bsp/xilinx-zynqmp: Implement Ultra96 target

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Modifications to get xilinx-zynqmp BSP working on an Ultra96 board.

Update #3682.
This commit is contained in:
Jeff Kubascik
2019-04-10 19:38:55 -04:00
committed by Sebastian Huber
parent 677d5167ba
commit 77f9a1be47
17 changed files with 268 additions and 254 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
bsps/arm/xilinx-zynqmp/README
View File

@@ -1,13 +1,30 @@
Tested only on Qemu.
Tested on an Ultra96 board with JTAG boot.
git clone git://git.qemu.org/qemu.git qemu
cd qemu
git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080
mkdir build
cd build
../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu
make
make install
export PATH="$PATH:/opt/qemu/bin"
Make sure to configure the boot mode switches for JTAG mode.
qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe
Using the xsct tool, load and run the application with
connect
targets -set -filter {name =~ "PSU"}
rst -system
source psu_init.tcl
psu_init
targets -set -filter {name =~ "Cortex-A53 #0"}
rst -processor
dow ticker.exe
# Set generic timer frequency
rwr sys 14 cntfrq_el0 100000000
# Switch to AArch32 Supervisor mode
rwr cpsr 0x2001d3
# Boot arguments
rwr r0 0
rwr r1 0
rwr r2 0
rwr r3 0
con

2
bsps/arm/xilinx-zynqmp/config/xilinx_zynq.inc → bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp.inc
View File

@@ -2,7 +2,7 @@ include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a53
CFLAGS_OPTIMIZE_V ?= -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections

1
bsps/arm/xilinx-zynqmp/config/xilinx_zynqmp_ultra96.cfg Normal file
View File

@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/xilinx_zynqmp.inc

69
bsps/arm/xilinx-zynqmp/console/console-config.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2013, 2017 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -27,21 +32,22 @@
#include <rtems/console.h>
#include <rtems/bspIo.h>
#include <rtems/sysinit.h>
#include <bsp/irq.h>
#include <bsp/zynq-uart.h>
#include <bspopts.h>
zynq_uart_context zynq_uart_instances[2] = {
static zynq_uart_context zynqmp_uart_instances[2] = {
{
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
.regs = (volatile struct zynq_uart *) 0xe0000000,
.irq = ZYNQ_IRQ_UART_0
.regs = (volatile struct zynq_uart *) 0xff000000,
.irq = ZYNQMP_IRQ_UART_0
}, {
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
.regs = (volatile struct zynq_uart *) 0xe0001000,
.irq = ZYNQ_IRQ_UART_1
.regs = (volatile struct zynq_uart *) 0xff010000,
.irq = ZYNQMP_IRQ_UART_1
}
};
@@ -55,7 +61,7 @@ rtems_status_code console_initialize(
rtems_termios_initialize();
for (i = 0; i < RTEMS_ARRAY_SIZE(zynq_uart_instances); ++i) {
for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
char uart[] = "/dev/ttySX";
uart[sizeof(uart) - 2] = (char) ('0' + i);
@@ -63,7 +69,7 @@ rtems_status_code console_initialize(
&uart[0],
&zynq_uart_handler,
NULL,
&zynq_uart_instances[i].base
&zynqmp_uart_instances[i].base
);
if (i == BSP_CONSOLE_MINOR) {
@@ -73,3 +79,52 @@ rtems_status_code console_initialize(
return RTEMS_SUCCESSFUL;
}
void zynqmp_debug_console_flush(void)
{
zynq_uart_reset_tx_flush(&zynqmp_uart_instances[BSP_CONSOLE_MINOR]);
}
static void zynqmp_debug_console_out(char c)
{
rtems_termios_device_context *base =
&zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
zynq_uart_write_polled(base, c);
}
static void zynqmp_debug_console_init(void)
{
rtems_termios_device_context *base =
&zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
zynq_uart_initialize(base);
BSP_output_char = zynqmp_debug_console_out;
}
static void zynqmp_debug_console_early_init(char c)
{
rtems_termios_device_context *base =
&zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
zynq_uart_initialize(base);
zynqmp_debug_console_out(c);
}
static int zynqmp_debug_console_in(void)
{
rtems_termios_device_context *base =
&zynqmp_uart_instances[BSP_CONSOLE_MINOR].base;
return zynq_uart_read_polled(base);
}
BSP_output_char_function_type BSP_output_char = zynqmp_debug_console_early_init;
BSP_polling_getchar_function_type BSP_poll_char = zynqmp_debug_console_in;
RTEMS_SYSINIT_ITEM(
zynqmp_debug_console_init,
RTEMS_SYSINIT_BSP_START,
RTEMS_SYSINIT_ORDER_LAST
);

11
bsps/arm/xilinx-zynqmp/headers.am
View File

@@ -1,15 +1,10 @@
## This file was generated by "./boostrap -H".
include_HEADERS =
include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp.h
include_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/bsp.h
include_HEADERS += include/bspopts.h
include_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/tm27.h
include_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/tm27.h
include_bspdir = $(includedir)/bsp
include_bsp_HEADERS =
include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h
include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h
include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart-regs.h
include_bsp_HEADERS += ../../../../../../bsps/arm/include/bsp/zynq-uart.h
include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynqmp/include/bsp/irq.h

47
bsps/arm/xilinx-zynqmp/include/bsp.h
View File

@@ -1,6 +1,6 @@
/**
* @file
* @ingroup RTEMSBSPsARMZynq
* @ingroup RTEMSBSPsARMZynqMP
* @brief Global BSP definitions.
*/
@@ -9,6 +9,11 @@
*
* Copyright (C) 2013, 2014 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -31,15 +36,15 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H
#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H
#ifndef LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
#define LIBBSP_ARM_XILINX_ZYNQMP_BSP_H
/**
* @defgroup RTEMSBSPsARMZynq Xilinx Zynq
* @defgroup RTEMSBSPsARMZynqMP Xilinx Zynq UltraScale+ MPSoC
*
* @ingroup RTEMSBSPsARM
*
* @brief Xilinx Zynq Board Support Package.
* @brief Xilinx Zynq UltraScale+ MPSoC Board Support Package.
*
* @{
*/
@@ -54,39 +59,29 @@
#include <bsp/default-initial-extension.h>
#include <bsp/start.h>
#include <bsp/zynq-uart.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000
#define BSP_ARM_GIC_CPUIF_BASE 0xf9020000
#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
#define BSP_ARM_GIC_DIST_BASE 0xf9010000
#define BSP_ARM_A9MPCORE_GT_BASE 0xf8f00200
#define BSP_ARM_A9MPCORE_SCU_BASE 0
#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
#define BSP_ARM_L2C_310_BASE 0xf8f02000
#define BSP_ARM_L2C_310_ID 0x410000c8
extern zynq_uart_context zynq_uart_instances[2];
#define BSP_ARM_A9MPCORE_GT_BASE 0
/**
* @brief Zynq specific set up of the MMU.
* @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
*
* Provide in the application to override
* the defaults in the BSP. Note the defaults do not map in the GP0 and GP1
* AXI ports. You should add the specific regions that map into your
* PL rather than just open the whole of the GP[01] address space up.
* Provide in the application to override the defaults in the BSP.
*/
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void);
BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
uint32_t zynq_clock_cpu_1x(void);
void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
void zynqmp_debug_console_flush(void);
#ifdef __cplusplus
}
@@ -96,4 +91,4 @@ uint32_t zynq_clock_cpu_1x(void);
/** @} */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */
#endif /* LIBBSP_ARM_XILINX_ZYNQMP_BSP_H */

89
bsps/arm/xilinx-zynqmp/include/bsp/irq.h
View File

@@ -1,6 +1,6 @@
/**
* @file
* @ingroup zynq_interrupt
* @ingroup zynqmp_interrupt
* @brief Interrupt definitions.
*/
@@ -9,6 +9,11 @@
*
* Copyright (C) 2013 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -31,15 +36,14 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
#ifndef LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H
#define LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H
#ifndef ASM
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
#include <bsp/arm-a9mpcore-irq.h>
#include <bsp/arm-gic-irq.h>
#ifdef __cplusplus
@@ -47,75 +51,24 @@ extern "C" {
#endif /* __cplusplus */
/**
* @defgroup zynq_interrupt Interrupt Support
* @ingroup RTEMSBSPsARMZynq
* @defgroup zynqmp_interrupt Interrupt Support
* @ingroup RTEMSBSPsARMZynqMP
* @brief Interrupt Support
* @{
*/
#define ZYNQ_IRQ_CPU_0 32
#define ZYNQ_IRQ_CPU_1 33
#define ZYNQ_IRQ_L2_CACHE 34
#define ZYNQ_IRQ_OCM 35
#define ZYNQ_IRQ_PMU_0 37
#define ZYNQ_IRQ_PMU_1 38
#define ZYNQ_IRQ_XADC 39
#define ZYNQ_IRQ_DVI 40
#define ZYNQ_IRQ_SWDT 41
#define ZYNQ_IRQ_TTC_0_0 42
#define ZYNQ_IRQ_TTC_1_0 43
#define ZYNQ_IRQ_TTC_2_0 44
#define ZYNQ_IRQ_DMAC_ABORT 45
#define ZYNQ_IRQ_DMAC_0 46
#define ZYNQ_IRQ_DMAC_1 47
#define ZYNQ_IRQ_DMAC_2 48
#define ZYNQ_IRQ_DMAC_3 49
#define ZYNQ_IRQ_SMC 50
#define ZYNQ_IRQ_QUAD_SPI 51
#define ZYNQ_IRQ_GPIO 52
#define ZYNQ_IRQ_USB_0 53
#define ZYNQ_IRQ_ETHERNET_0 54
#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
#define ZYNQ_IRQ_SDIO_0 56
#define ZYNQ_IRQ_I2C_0 57
#define ZYNQ_IRQ_SPI_0 58
#define ZYNQ_IRQ_UART_0 59
#define ZYNQ_IRQ_CAN_0 60
#define ZYNQ_IRQ_FPGA_0 61
#define ZYNQ_IRQ_FPGA_1 62
#define ZYNQ_IRQ_FPGA_2 63
#define ZYNQ_IRQ_FPGA_3 64
#define ZYNQ_IRQ_FPGA_4 65
#define ZYNQ_IRQ_FPGA_5 66
#define ZYNQ_IRQ_FPGA_6 67
#define ZYNQ_IRQ_FPGA_7 68
#define ZYNQ_IRQ_TTC_0_1 69
#define ZYNQ_IRQ_TTC_1_1 70
#define ZYNQ_IRQ_TTC_2_1 71
#define ZYNQ_IRQ_DMAC_4 72
#define ZYNQ_IRQ_DMAC_5 73
#define ZYNQ_IRQ_DMAC_6 74
#define ZYNQ_IRQ_DMAC_7 75
#define ZYNQ_IRQ_USB_1 76
#define ZYNQ_IRQ_ETHERNET_1 77
#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
#define ZYNQ_IRQ_SDIO_1 79
#define ZYNQ_IRQ_I2C_1 80
#define ZYNQ_IRQ_SPI_1 81
#define ZYNQ_IRQ_UART_1 82
#define ZYNQ_IRQ_CAN_1 83
#define ZYNQ_IRQ_FPGA_8 84
#define ZYNQ_IRQ_FPGA_9 85
#define ZYNQ_IRQ_FPGA_10 86
#define ZYNQ_IRQ_FPGA_11 87
#define ZYNQ_IRQ_FPGA_12 88
#define ZYNQ_IRQ_FPGA_13 89
#define ZYNQ_IRQ_FPGA_14 90
#define ZYNQ_IRQ_FPGA_15 91
#define ZYNQ_IRQ_PARITY 92
/* PPIs */
#define ZYNQMP_IRQ_HYP_TIMER 26
#define ZYNQMP_IRQ_VIRT_TIMER 27
#define ZYNQMP_IRQ_S_PHYS_TIMER 29
#define ZYNQMP_IRQ_NS_PHYS_TIMER 30
/* SPIs */
#define ZYNQMP_IRQ_UART_0 53
#define ZYNQMP_IRQ_UART_1 54
#define BSP_INTERRUPT_VECTOR_MIN 0
#define BSP_INTERRUPT_VECTOR_MAX 92
#define BSP_INTERRUPT_VECTOR_MAX 187
/** @} */
@@ -125,4 +78,4 @@ extern "C" {
#endif /* ASM */
#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
#endif /* LIBBSP_ARM_XILINX_ZYNQMP_IRQ_H */

11
bsps/arm/xilinx-zynqmp/include/tm27.h
View File

@@ -1,6 +1,6 @@
/**
* @file
* @ingroup zynq_tm27
* @ingroup zynqmp_tm27
* @brief Interrupt mechanisms for tm27 test.
*/
@@ -9,6 +9,11 @@
*
* Copyright (C) 2013 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -39,8 +44,8 @@
#define __tm27_h
/**
* @defgroup zynq_tm27 TM27 Test Support
* @ingroup RTEMSBSPsARMZynq
* @defgroup zynqmp_tm27 TM27 Test Support
* @ingroup RTEMSBSPsARMZynqMP
* @brief Interrupt Mechanisms for tm27 test
*/

15
bsps/arm/xilinx-zynqmp/start/bspreset.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2013 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -26,18 +31,12 @@
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <bsp/zynq-uart.h>
void bsp_reset(void)
{
volatile uint32_t *slcr_unlock = (volatile uint32_t *) 0xf8000008;
volatile uint32_t *pss_rst_ctrl = (volatile uint32_t *) 0xf8000200;
zynq_uart_reset_tx_flush(&zynq_uart_instances[BSP_CONSOLE_MINOR]);
zynqmp_debug_console_flush();
while (true) {
*slcr_unlock = 0xdf0d;
*pss_rst_ctrl = 0x1;
/* Wait */
}
}

5
bsps/arm/xilinx-zynqmp/start/bspsmp.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2014 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:

22
bsps/arm/xilinx-zynqmp/start/bspstart.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2013, 2015 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -30,9 +35,22 @@
#include <bsp/irq-generic.h>
#include <bsp/linker-symbols.h>
__attribute__ ((weak)) uint32_t zynq_clock_cpu_1x(void)
#include <libcpu/arm-cp15.h>
void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq)
{
return ZYNQ_CLOCK_CPU_1X;
#ifdef ARM_GENERIC_TIMER_FREQ
*frequency = ARM_GENERIC_TIMER_FREQ;
#else
/* Use generic timer frequency provided by boot loader */
*frequency = arm_cp15_get_counter_frequency();
#endif
#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
*irq = ZYNQMP_IRQ_VIRT_TIMER;
#else
*irq = ZYNQMP_IRQ_NS_PHYS_TIMER;
#endif
}
void bsp_start(void)

20
bsps/arm/xilinx-zynqmp/start/bspstarthooks.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2013, 2014 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -37,6 +42,8 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
uint32_t sctlr_val;
sctlr_val = arm_cp15_get_control();
sctlr_val |= ARM_CP15_CTRL_CP15BEN;
arm_cp15_set_control( sctlr_val );
/*
* Current U-boot loader seems to start kernel image
@@ -69,21 +76,12 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
arm_a9mpcore_start_hook_0();
}
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
{
arm_a9mpcore_start_hook_1();
arm_a9mpcore_start_set_vector_base();
bsp_start_copy_sections();
zynq_setup_mmu_and_cache();
#if !defined(RTEMS_SMP) \
&& (defined(BSP_DATA_CACHE_ENABLED) \
|| defined(BSP_INSTRUCTION_CACHE_ENABLED))
/* Enable unified L2 cache */
rtems_cache_enable_data();
#endif
zynqmp_setup_mmu_and_cache();
bsp_start_clear_bss();
}

25
bsps/arm/xilinx-zynqmp/start/bspstartmmu.c
View File

@@ -3,6 +3,11 @@
*
* Copyright (C) 2013 embedded brains GmbH
*
* Copyright (C) 2019 DornerWorks
*
* Written by Jeff Kubascik <jeff.kubascik@dornerworks.com>
* and Josh Whitehead <josh.whitehead@dornerworks.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -33,7 +38,7 @@
#include <bsp/arm-a9mpcore-start.h>
BSP_START_DATA_SECTION static const arm_cp15_start_section_config
zynq_mmu_config_table[] = {
zynqmp_mmu_config_table[] = {
ARMV7_CP15_START_DEFAULT_SECTIONS,
#if defined(RTEMS_SMP)
{
@@ -43,12 +48,12 @@ zynq_mmu_config_table[] = {
},
#endif
{
.begin = 0xe0000000U,
.end = 0xe0200000U,
.begin = 0xf9000000U,
.end = 0xf9100000U,
.flags = ARMV7_MMU_DEVICE
}, {
.begin = 0xf8000000U,
.end = 0xf9000000U,
.begin = 0xfd000000U,
.end = 0xffc00000U,
.flags = ARMV7_MMU_DEVICE
}
};
@@ -56,12 +61,12 @@ zynq_mmu_config_table[] = {
/*
* Make weak and let the user override.
*/
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) __attribute__ ((weak));
BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void) __attribute__ ((weak));
BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void)
{
uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
ARM_CP15_CTRL_A,
ARM_CP15_CTRL_TRE | ARM_CP15_CTRL_A,
ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
);
@@ -69,7 +74,7 @@ BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void)
ctrl,
(uint32_t *) bsp_translation_table_base,
ARM_MMU_DEFAULT_CLIENT_DOMAIN,
&zynq_mmu_config_table[0],
RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
&zynqmp_mmu_config_table[0],
RTEMS_ARRAY_SIZE(zynqmp_mmu_config_table)
);
}

10
bsps/arm/xilinx-zynqmp/start/linkcmds.in
View File

@@ -1,9 +1,9 @@
MEMORY {
RAM_INT_0 : ORIGIN = @ZYNQ_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_0_LENGTH@
RAM_INT_1 : ORIGIN = @ZYNQ_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQ_RAM_INT_1_LENGTH@
RAM_MMU : ORIGIN = @ZYNQ_RAM_MMU@, LENGTH = @ZYNQ_RAM_MMU_LENGTH@
RAM : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@
NOCACHE : ORIGIN = @ZYNQ_RAM_ORIGIN_AVAILABLE@ + @ZYNQ_RAM_LENGTH_AVAILABLE@ - @ZYNQ_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQ_RAM_NOCACHE_LENGTH@
RAM_INT_0 : ORIGIN = @ZYNQMP_RAM_INT_0_ORIGIN@, LENGTH = @ZYNQMP_RAM_INT_0_LENGTH@
RAM_INT_1 : ORIGIN = @ZYNQMP_RAM_INT_1_ORIGIN@, LENGTH = @ZYNQMP_RAM_INT_1_LENGTH@
RAM_MMU : ORIGIN = @ZYNQMP_RAM_MMU@, LENGTH = @ZYNQMP_RAM_MMU_LENGTH@
RAM : ORIGIN = @ZYNQMP_RAM_ORIGIN_AVAILABLE@, LENGTH = @ZYNQMP_RAM_LENGTH_AVAILABLE@ - @ZYNQMP_RAM_NOCACHE_LENGTH@
NOCACHE : ORIGIN = @ZYNQMP_RAM_ORIGIN_AVAILABLE@ + @ZYNQMP_RAM_LENGTH_AVAILABLE@ - @ZYNQMP_RAM_NOCACHE_LENGTH@, LENGTH = @ZYNQMP_RAM_NOCACHE_LENGTH@
}
REGION_ALIAS ("REGION_START", RAM);