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2005-02-24 Jay Monkman <jtm@lopingdog.com>

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* Makefile.am, configure.ac: New CPU.
        * shared/interrupts/installisrentries.c,
	shared/interrupts/isr_entries.S: Added CPU32 support.
	* au1x00/Makefile.am, au1x00/include/au1x00.h,
	au1x00/vectorisrs/maxvectors.c, au1x00/vectorisrs/vectorisrs.c: New CPU.
This commit is contained in:
Jay Monkman
2005-02-25 05:18:49 +00:00
parent 7cde240ce8
commit 74fb4e1f1d
9 changed files with 819 additions and 1 deletions
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11
c/src/lib/libcpu/mips/shared/interrupts/installisrentries.c
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@@ -18,6 +18,17 @@ void mips_install_isr_entries( void )
memcpy( (void *)DB_VEC, exc_dbg_code, 40 );
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vevtor */
#elif __mips == 32
void exc_tlb_code(void);
void exc_xtlb_code(void);
void exc_cache_code(void);
void exc_norm_code(void);
memcpy( (void *)T_VEC, exc_tlb_code, 40 ); /* tlbmiss vector */
memcpy( (void *)X_VEC, exc_xtlb_code, 40 ); /* xtlbmiss vector */
memcpy( (void *)C_VEC, exc_cache_code, 40 ); /* cache error vector */
memcpy( (void *)E_VEC, exc_norm_code, 40 ); /* exception vector */
#elif __mips == 3
void exc_tlb_code(void);
void exc_xtlb_code(void);

30
c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S
View File

@@ -40,6 +40,36 @@ FRAME(exc_utlb_code,sp,0,ra)
nop
ENDFRAME(exc_utlb_code)
/*
* MIPS ISA Level 32
* XXX Again, reliance on SIM. Not good.??????????
*/
#elif __mips == 32
FRAME(exc_tlb_code,sp,0,ra)
la k0, _ISR_Handler
j k0
nop
ENDFRAME(exc_tlb_code)
FRAME(exc_xtlb_code,sp,0,ra)
la k0, _ISR_Handler
j k0
nop
ENDFRAME(exc_xtlb_code)
FRAME(exc_cache_code,sp,0,ra)
la k0, _ISR_Handler
j k0
nop
ENDFRAME(exc_cache_code)
FRAME(exc_norm_code,sp,0,ra)
la k0, _ISR_Handler /* generic external int hndlr */
j k0
nop
ENDFRAME(exc_norm_code)
/*
* MIPS ISA Level 3
* XXX Again, reliance on SIM. Not good.