forked from Imagelibrary/rtems
@@ -116,12 +116,7 @@ void arm_interrupt_handler_dispatch(rtems_vector_number vector);
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*/
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void gicvx_interrupt_dispatch(void);
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static inline uint32_t arm_gic_irq_processor_count(void)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
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}
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uint32_t arm_gic_irq_processor_count(void);
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void arm_gic_irq_initialize_secondary_cpu(void);
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@@ -269,3 +269,10 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
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#endif
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| GIC_DIST_ICDSGIR_SGIINTID(vector);
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}
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uint32_t arm_gic_irq_processor_count(void)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
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}
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@@ -354,3 +354,30 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
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#endif
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WRITE64_SR(ICC_SGI1, value);
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}
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uint32_t arm_gic_irq_processor_count(void)
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{
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volatile gic_dist *dist = ARM_GIC_DIST;
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uint32_t cpu_count;
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if ((dist->icddcr & GIC_DIST_ICDDCR_ARE_S) == 0) {
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cpu_count = GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
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} else {
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int i;
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/* Assume that an interrupt export port exists */
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cpu_count = 0;
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for (i = 0; i < CPU_MAXIMUM_PROCESSORS; ++i) {
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volatile gic_redist *redist = gicv3_get_redist(i);
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if ((redist->icrtyper & GIC_REDIST_ICRTYPER_LAST) != 0) {
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break;
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}
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++cpu_count;
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}
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}
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return cpu_count;
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}
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