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remove obsolete files

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This commit is contained in:
Thomas Doerfler
2009-07-17 15:10:27 +00:00
parent 3f81399c6b
commit 72f6cb06df
4 changed files with 0 additions and 839 deletions
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162
c/src/lib/libbsp/arm/gba/startup/cpu.c
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@@ -1,162 +0,0 @@
/**
* @file cpu.c
*
* ARM CPU Dependent Source.
*/
/*
* RTEMS GBA BSP
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2002 Advent Networks, Inc
* Jay Monkman <jmonkman@adventnetworks.com>
*
* Copyright (c) 2004
* Markku Puro <markku.puro@kopteri.net>
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <stdint.h>
#include <rtems/system.h>
#include <rtems.h>
#include <rtems/bspIo.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <rtems/score/thread.h>
#include <rtems/score/cpu.h>
#include <arm_mode_bits.h>
/**
* @brief _CPU_Initialize routine performs processor dependent initialization
*/
void _CPU_Initialize(void)
{
}
/**
* @brief _CPU_ISR_Get_level returns the current interrupt level
*
* @param None
* @return int level
*/
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t reg = 0; /* to avoid warning */
asm volatile ("mrs %0, cpsr \n" \
"and %0, %0, #0xc0 \n" \
: "=r" (reg) \
: "0" (reg) );
return reg;
}
/**
* @brief _CPU_ISR_install_vector kernel routine installs the RTEMS handler for the
* specified vector
*
* @param vector interrupt vector number
* @param new_handler replacement ISR for this vector number
* @param old_handler pointer to store former ISR for this vector number
* @return None
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
*/
extern __inline__ void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler);
/**
* @brief _CPU_Context_Initialize kernel routine initialize the specified context
*
* @param the_context
* @param stack_base
* @param size
* @param new_level
* @param entry_point
* @param is_fp
* @return None
*/
void _CPU_Context_Initialize(
Context_Control *the_context,
uint32_t *stack_base,
uint32_t size,
uint32_t new_level,
void *entry_point,
bool is_fp
)
{
the_context->register_sp = (uint32_t)stack_base + size ;
the_context->register_lr = (uint32_t)entry_point;
the_context->register_cpsr = new_level | ModePriv;
}
/**
* @brief _CPU_Install_interrupt_stack function is empty since the BSP must set up the interrupt stacks.
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
*/
extern __inline__ void _CPU_Install_interrupt_stack( void );
/**
* @brief _defaultExcHandler function is empty
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
*/
extern void _defaultExcHandler (CPU_Exception_frame *ctx);
/**
* @brief _currentExcHandler function is empty (_defaultExcHandler)
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
*/
cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
/*
extern void _Exception_Handler_Undef_Swi();
extern void _Exception_Handler_Abort();
extern void _exc_data_abort();
*/
/**
* @brief rtems_exception_init_mngt function is empty since the BSP must set up the interrupt stacks.
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
*/
extern __inline__ void rtems_exception_init_mngt(void);
/**
* @brief do_data_abort function is empty
*
* This function figure out what caused the data abort
*
* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!!
* This function is supposed to figure out what caused the data abort, do that, then return.
* All unhandled instructions cause the system to hang.
*/
extern __inline__ void do_data_abort(uint32_t insn, uint32_t spsr, CPU_Exception_frame *ctx);
/* @todo Can't use exception vectors in GBA because they are already in GBA ROM BIOS!! */
/* @todo Remove dummy functions needed by linker
****************************************************************************************/
/* @cond INCLUDE_ASM */
asm (" .text");
asm (" .arm");
asm (" .global _CPU_ISR_install_vector");
asm ("_CPU_ISR_install_vector:");
asm (" .global _CPU_Install_interrupt_stack");
asm ("_CPU_Install_interrupt_stack:");
asm (" .global _defaultExcHandler");
asm ("_defaultExcHandler:");
asm (" .global rtems_exception_init_mngt");
asm ("rtems_exception_init_mngt:");
asm (" .global do_data_abort");
asm ("do_data_abort:");
asm (" mov pc, lr");
/* @endcond */

86
c/src/lib/libbsp/arm/gba/startup/cpu_asm.S
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@@ -1,86 +0,0 @@
/**
* @file cpu_asm.S
*
* This file contains the implementation of exception handlers.
*/
/*
* RTEMS GBA BSP
*
* Copyright (c) 2002 by Advent Networks, Inc.
* Jay Monkman <jmonkman@adventnetworks.com>
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Copyright (c) 2004
* Markku Puro <markku.puro@kopteri.net>
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#define __asm__
#include <rtems/asm.h>
#include <rtems/score/cpu_asm.h>
#include <asm_macros.h>
/* @cond INCLUDE_ASM */
/**
* This routine performs a normal non-FP context.
* function void _CPU_Context_switch( run_context, heir_context )
* R0 = run_context R1 = heir_context
*
* This function copies the current registers to where r0 points, then
* restores the ones from where r1 points.
*
* Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
* a 16 bit data bus.
*
*/
.align
/* .section .iwram */
PUBLIC_ARM_FUNCTION(_CPU_Context_switch)
/* Start saving context */
mrs r2, cpsr
stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
/* Start restoring context */
_restore:
ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
msr cpsr, r2
mov pc, lr
LABEL_END(_CPU_Context_switch)
/**
* This function copies the restores the registers from where r0 points.
* function void _CPU_Context_restore( new_context )
* It must match _CPU_Context_switch()
*
*/
PUBLIC_ARM_FUNCTION(_CPU_Context_restore)
mov r1, r0
b _restore
LABEL_END(_CPU_Context_restore)
/**
* function _Exception_Handler_Undef_Swi
* Can't use exception vectors in GBA
* @todo _Exception_Handler_Undef_Swi: Unused handler needed by ../score/cpu_asm.S
*
*/
.global _Exception_Handler_Undef_Swi
_Exception_Handler_Undef_Swi:
mov pc, lr
/**
* function _Exception_Handler_Abort
* Can't use exception vectors in GBA
* @todo _Exception_Handler_Abort: Unused handler needed by ../score/cpu_asm.S
*
*/
.global _Exception_Handler_Abort
_Exception_Handler_Abort:
mov pc, lr
/* @endcond */

206
c/src/lib/libbsp/arm/shared/irq/irq_asm.S
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@@ -1,206 +0,0 @@
/* irq_asm.S
*
* This file contains the implementation of the IRQ handler
*
* Copyright (c) 2002 Advent Networks, Inc.
* Jay Monkman <jmonkman@adventnetworks.com>
*
* CopyRight (C) 2000 Canon Research France SA.
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
*
* Modified Andy Dachs <a.dachs@sstl.co.uk>
* Copyright (c) 2001 Surrey Satellite Technolgy Limited
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <rtems/asm.h>
#define __asm__
/*MUST be ARM code*/
/* assume that before interrupt we are in svc mode */
/* fix me: No priority support, interrupt disabled too long in the ISR */
.arm
.globl _ISR_Handler
_ISR_Handler:
.code 32
stmdb sp!, {r0, r1, r2, r3, r12} /* save regs on INT stack */
stmdb sp!, {lr} /* now safe to call C funcs */
/* one nest level deeper */
ldr r0, =_ISR_Nest_level
ldr r1, [r0]
add r1, r1,#1
str r1, [r0]
/* disable multitasking */
ldr r0, =_Thread_Dispatch_disable_level
ldr r1, [r0]
add r1, r1,#1
str r1, [r0]
/* BSP specific function to INT handler */
/* FIXME: I'm not sure why I can't save just r12. I'm also */
/* not sure which of r1-r3 are important. */
#ifdef __thumb__
ldr r0, =ExecuteITHandler +1
mov lr, pc
bx r0
#else
bl ExecuteITHandler
#endif
/* one less nest level */
ldr r0, =_ISR_Nest_level
ldr r1, [r0]
sub r1, r1,#1
str r1, [r0]
/* unnest multitasking */
ldr r0, =_Thread_Dispatch_disable_level
ldr r1, [r0]
sub r1, r1,#1
str r1, [r0]
/* check to see if we interrupted nd INT (with FIQ?) */
mrs r0, spsr
and r0, r0, #0x1f
cmp r0, #0x12 /* is it INT mode? */
beq exitit
/* If thread dispatching is disabled, exit */
cmp r1, #0
bne exitit
/* If a task switch is necessary, call scheduler */
ldr r0, =_Context_Switch_necessary
ldrb r1, [r0]
cmp r1, #0
/* since bframe is going to clear _ISR_Signals_to_thread_executing, */
/* we need to load it here */
ldr r0, =_ISR_Signals_to_thread_executing
ldrb r1, [r0]
bne bframe
/* If a signals to be sent (_ISR_Signals_to_thread_executing != 0), */
/* call scheduler */
cmp r1, #0
beq exitit
/* _ISR_Signals_to_thread_executing = FALSE */
mov r1, #0
strb r1, [r0]
bframe:
/* Now we need to set up the return from this ISR to be _ISR_Dispatch */
/* To do that, we need to save the current lr_int and spsr_int on the */
/* SVC stack */
mrs r0, spsr
ldmia sp!, {r1} /* get lr off stack */
stmdb sp!, {r1}
mrs r2, cpsr
orr r3, r2, #0x1 /* change to SVC mode */
msr cpsr_c, r3
/* now in SVC mode */
stmdb sp!, {r0, r1} /* put spsr_int and lr_int on SVC stack */
msr cpsr_c, r2 /* change back to INT mode */
/* now in INT mode */
/* replace lr with address of _ISR_Dispatch */
ldr lr, =_ISR_Dispatch_p_4 /* On entry to an ISR, the lr is */
/* the return address + 4, so */
/* we have to emulate that */
#ifdef __thumb__
sub lr, #0x1
#endif
ldmia sp!, {r1} /* out with the old */
stmdb sp!, {lr} /* in with the new (lr) */
#ifndef __thumb__
orr r0, r0, #0xc0
msr spsr_cf, r0 /* mask interrupt */
#endif
exitit:
ldmia sp!, {lr} /* restore regs from INT stack */
ldmia sp!, {r0, r1, r2, r3, r12} /* restore regs from INT stack */
subs pc, lr, #4 /* return */
/* on entry to _ISR_Dispatch, we're in SVC mode */
.globl _ISR_Dispatch
_ISR_Dispatch:
#ifdef __thumb__
/* will be called from ISR, with SPSR in T mode */
/* ISR will enter from here */
.code 16
.thumb_func
push {r0-r3,lr} /* save regs on SVC stack */
/* (now safe to call C funcs) */
/* we don't save lr, since */
/* it's just going to get */
/* overwritten */
//nop /* made _ISR_Dispatch_p_4 4-word align */ /*recent compiler have a better support for pad*/
#else
.code 32
stmdb sp!, {r0-r3, r12,lr} /* save regs on SVC stack */
/* (now safe to call C funcs) */
/* we don't save lr, since */
/* it's just going to get */
/* overwritten */
#endif
_ISR_Dispatch_p_4:
bl _Thread_Dispatch
#ifdef __thumb__
ldr r0, = .Thread_Disp_T
bx r0
.pool
.code 32
.Thread_Disp_T:
#endif
#ifdef __thumb__
ldmia sp!, {r0-r3, lr} /*r12 not saved in thumb mode*/
#else
ldmia sp!, {r0-r3, r12, lr}
#endif
stmdb sp!, {r0-r2}
/* Now we have to screw with the stack */
mov r0, sp /* copy the SVC stack pointer */
mrs r1, cpsr
bic r2, r1, #0x1 /* change to INT mode */
orr r2, r2, #0xc0 /* disable interrupts */
msr cpsr_c, r2
/* now in INT mode */
stmdb sp!, {r4, r5, r6} /* save temp vars on INT stack */
ldmia r0!, {r4, r5, r6} /* Get r0-r3 from SVC stack */
stmdb sp!, {r4, r5, r6} /* and save them on INT stack */
ldmia r0!, {r4, r5} /* get saved values from SVC stack */
/* r4=spsr, r5=lr */
mov lr, r5 /* restore lr_int */
msr spsr, r4 /* restore spsr_int */
/* switch to SVC mode, update sp, then return to INT mode */
msr cpsr_c, r1 /* switch to SVC mode */
mov sp, r0 /* update sp_svc */
msr cpsr_c, r2 /* switch back to INT mode */
/* pop all the registers from the stack */
ldmia sp!, {r0, r1, r2}
ldmia sp!, {r4, r5, r6}
/* Finally, we can return to the interrupted task */
subs pc, lr, #4

385
c/src/lib/libbsp/arm/shared/startup/linkcmds.rom
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@@ -1,385 +0,0 @@
/**
* @file
*
* @brief Linker command base file for configuration with internal and external
* RAM and optional ROM load.
*
* You need to add a linker command file to your board support package that
* includes this file at the end and provides the following definitions.
*
* Compulsory are the memory regions RAM_INT, RAM_EXT and NIRVANA.
* <pre>
* MEMORY {
* RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
* RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 32M
* NIRVANA : ORIGIN = 0, LENGTH = 0
* }
* </pre>
*
* You may optionally provide ROM start and size values.
* <pre>
* bsp_rom_start = 0x80000000;
* bsp_rom_size = 0x01000000;
* </pre>
*
* Optionally you can enable the load to ROM. It is enabled then
* bsp_enable_rom_load is defined. The value is arbitrary.
* <pre>
* bsp_enable_rom_load = 1;
* </pre>
*
* Include the linker command base file. This file has to be installed in the
* same directory than your linker command file.
* <pre>
* INCLUDE linkcmds.base
* </pre>
*
* You may define optionally values for the following sizes:
* - bsp_ram_int_size
* - bsp_ram_ext_size
* - bsp_stack_abt_size
* - bsp_stack_fiq_size
* - bsp_stack_irq_size
* - bsp_stack_svc_size
* - bsp_stack_undef_size
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
*/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH (arm)
ENTRY (start)
/*
* BSP: Symbols that may be defined externally. The minimum alignment
* requirement for regions is bsp_section_align.
*/
bsp_ram_int_size = DEFINED (bsp_ram_int_size) ? bsp_ram_int_size : LENGTH (RAM_INT);
bsp_ram_ext_size = DEFINED (bsp_ram_ext_size) ? bsp_ram_ext_size : LENGTH (RAM_EXT);
bsp_rom_start = DEFINED (bsp_rom_start) ? bsp_rom_start : 0;
bsp_rom_size = DEFINED (bsp_rom_size) ? bsp_rom_size : 0;
bsp_ram_ext_load_start = DEFINED (bsp_enable_rom_load) ? bsp_rom_start : bsp_ram_ext_start;
bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 128;
bsp_stack_fiq_size = DEFINED (bsp_stack_fiq_size) ? bsp_stack_fiq_size : 128;
bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 256;
bsp_stack_svc_size = DEFINED (bsp_stack_svc_size) ? bsp_stack_svc_size : 256;
bsp_stack_undef_size = DEFINED (bsp_stack_undef_size) ? bsp_stack_undef_size : 128;
/*
* BSP: Global symbols
*/
bsp_ram_int_start = ORIGIN (RAM_INT);
bsp_ram_int_end = bsp_ram_int_start + bsp_ram_int_size;
bsp_ram_ext_start = ORIGIN (RAM_EXT);
bsp_ram_ext_end = bsp_ram_ext_start + bsp_ram_ext_size;
bsp_rom_end = bsp_rom_start + bsp_rom_size;
bsp_section_align = 16;
bsp_stack_align = 16;
SECTIONS {
.vector : {
/*
* BSP: Start of vector section
*/
bsp_section_vector_start = .;
/*
* BSP: Reserve space for the the exception vector table and
* the pointers to the default exceptions handlers.
*/
. = . + 64;
. = ALIGN (bsp_section_align);
/*
* BSP: End of vector section
*/
bsp_section_vector_end = .;
} > RAM_INT
bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_start;
.text : {
/*
* BSP: Start of text section
*/
bsp_section_text_start = .;
/*
* BSP: System startup entry
*/
KEEP (*(.entry))
/*
* BSP: Moved into .text from .init
*/
KEEP (*(.init))
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
/*
* BSP: Magic ARM stuff
*/
*(.ARM.*)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
/*
* BSP: Special FreeBSD sysctl sections
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/*
* BSP: Moved into .text from .*
*/
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.eh_frame_hdr)
/*
* BSP: Required by cpukit/score/src/threadhandler.c
*/
PROVIDE (_fini = .);
/*
* BSP: Moved into .text from .fini
*/
KEEP (*(.fini))
. = ALIGN (bsp_section_align);
/*
* BSP: End of text section
*/
bsp_section_text_end = .;
} > ROM_INT
bsp_section_text_size = bsp_section_text_end - bsp_section_text_start;
.data : AT (bsp_section_text_end) {
/*
* BSP: Start of data section
*/
bsp_section_data_start = .;
/*
* BSP: Moved into .data from .ctors
*/
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
/*
* BSP: Moved into .data from .dtors
*/
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/*
* BSP: Moved into .data from .*
*/
*(.data1)
KEEP (*(.eh_frame))
*(.gcc_except_table .gcc_except_table.*)
KEEP (*(.jcr))
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
. = ALIGN (bsp_section_align);
/*
* BSP: End of data section
*/
bsp_section_data_end = .;
} > RAM_EXT
bsp_section_data_size = bsp_section_data_end - bsp_section_data_start;
.bss : {
/*
* BSP: Start of bss section
*/
bsp_section_bss_start = .;
*(COMMON)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN (bsp_section_align);
/*
* BSP: End of bss section
*/
bsp_section_bss_end = .;
} > RAM_EXT
bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_start;
.stack : {
/*
* BSP: Start of stack section
*/
bsp_section_stack_start = .;
. = ALIGN (bsp_stack_align);
bsp_stack_abt_start = .;
. = . + bsp_stack_abt_size;
. = ALIGN (bsp_stack_align);
bsp_stack_fiq_start = .;
. = . + bsp_stack_fiq_size;
. = ALIGN (bsp_stack_align);
bsp_stack_irq_start = .;
. = . + bsp_stack_irq_size;
. = ALIGN (bsp_stack_align);
bsp_stack_svc_start = .;
. = . + bsp_stack_svc_size;
. = ALIGN (bsp_stack_align);
bsp_stack_undef_start = .;
. = . + bsp_stack_undef_size;
. = ALIGN (bsp_section_align);
/*
* BSP: End of stack section
*/
bsp_section_stack_end = .;
} > RAM_INT
bsp_section_stack_size = bsp_section_stack_end - bsp_section_stack_start;
.work_area : {
/*
* BSP: Start of work area. The work area will occupy the remaining
* RAM_EXT region and contains the RTEMS work space and heap. We cannot
* assign the region end directly since this leads to a region full
* warning.
*/
bsp_section_work_area_start = .;
. = bsp_ram_ext_end - 4;
. = ALIGN (bsp_section_align);
/*
* BSP: End of work area
*/
bsp_section_work_area_end = .;
} > RAM_EXT
bsp_section_work_area_size = bsp_section_work_area_end - bsp_section_work_area_start;
/*
* BSP: External symbols (FIXME)
*/
RamBase = bsp_ram_ext_start;
RamSize = bsp_ram_ext_size;
WorkAreaBase = bsp_section_work_area_start;
HeapSize = 0;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* DWARF 3 */
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.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : {
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/*
* BSP: Catch all unknown sections
*/
.nirvana : {
*(*)
} > NIRVANA
}