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Corrected register constraints per suggestion from Thomas Doerfler, IMD

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<td@imd.m.isar.de>.
This commit is contained in:
Joel Sherrill
1998-03-24 17:10:44 +00:00
parent d662fef884
commit 72b397aafa
2 changed files with 6 additions and 6 deletions
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6
c/src/exec/score/cpu/powerpc/cpu.c
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@@ -106,12 +106,12 @@ void _CPU_Initialize(
{ {
unsigned32 tmp; unsigned32 tmp;
asm volatile ("mfmsr %0" : "=r" (tmp)); asm volatile ("mfmsr %0" : "=&r" (tmp));
msr = tmp; msr = tmp;
#ifdef ppc403 #ifdef ppc403
asm volatile ("mfspr %0, 0x3d6" : "=r" (tmp)); /* EVPR */ asm volatile ("mfspr %0, 0x3d6" : "=&r" (tmp)); /* EVPR */
evpr = tmp; evpr = tmp;
asm volatile ("mfdcr %0, 0x42" : "=r" (tmp)); /* EXIER */ asm volatile ("mfdcr %0, 0x42" : "=&r" (tmp)); /* EXIER */
exier = tmp; exier = tmp;
asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */ asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */
#endif #endif

6
c/src/exec/score/cpu/powerpc/cpu.h
View File

@@ -618,7 +618,7 @@ SCORE_EXTERN struct {
{ \ { \
asm volatile ( \ asm volatile ( \
"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
"=r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \ "=&r" ((_isr_cookie)) : "r" ((PPC_MSR_DISABLE_MASK)) \
); \ ); \
} }
@@ -631,7 +631,7 @@ SCORE_EXTERN struct {
#define _CPU_ISR_Enable( _isr_cookie ) \ #define _CPU_ISR_Enable( _isr_cookie ) \
{ \ { \
asm volatile ( "mtmsr %0" : \ asm volatile ( "mtmsr %0" : \
"=r" ((_isr_cookie)) : "0" ((_isr_cookie))); \ "=&r" ((_isr_cookie)) : "0" ((_isr_cookie))); \
} }
/* /*
@@ -1015,7 +1015,7 @@ static inline unsigned int CPU_swap_u32(
"rlwimi %0,%1,24,16,23;" "rlwimi %0,%1,24,16,23;"
"rlwimi %0,%1,8,8,15;" "rlwimi %0,%1,8,8,15;"
"rlwimi %0,%1,24,0,7;" : "rlwimi %0,%1,24,0,7;" :
"=r" ((swapped)) : "r" ((value))); "=&r" ((swapped)) : "r" ((value)));
return( swapped ); return( swapped );
} }