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2009-05-25 Allan Hessenflow <allanh@kallisti.com>

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PR 1418/bsps
	* mmu/mmu.c: enable mmu after initializing it.
	* mmu/mmu.h: add missing mmu flags entries.
	* include/mmuRegs.h: correct a couple field name typos.
This commit is contained in:
Joel Sherrill
2009-05-27 11:57:33 +00:00
parent 8ef7f20d01
commit 6ff3add123
4 changed files with 21 additions and 3 deletions
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6
c/src/lib/libcpu/bfin/ChangeLog
View File

@@ -1,3 +1,9 @@
2009-05-25 Allan Hessenflow <allanh@kallisti.com>
* mmu/mmu.c: enable mmu after initializing it.
* mmu/mmu.h: add missing mmu flags entries.
* include/mmuRegs.h: correct a couple field name typos.
2008-09-25 Allan Hessenflow <allanh@kallisti.com>
* clock/clock.c, include/bf533.h, include/bf537.h, include/sicRegs.h:

4
c/src/lib/libcpu/bfin/include/mmuRegs.h
View File

@@ -50,8 +50,8 @@
#define ICPLB_DATA_CPLB_L1_CHBL 0x00001000
#define ICPLB_DATA_CPLB_LRUPRIO 0x00000100
#define ICPLB_DATA_CPLB_USER_RD 0x00000004
#define ICPLB_DATA_CPLB_CPLB_LOCK 0x00000002
#define ICPLB_DATA_CPLB_CPLB_VALID 0x00000001
#define ICPLB_DATA_CPLB_LOCK 0x00000002
#define ICPLB_DATA_CPLB_VALID 0x00000001
#endif /* _mmuRegs_h_ */

4
c/src/lib/libcpu/bfin/mmu/mmu.c
View File

@@ -13,9 +13,9 @@
#include <rtems.h>
#include <libcpu/memoryRegs.h>
#include "mmu.h"
/* NOTE: see notes in mmu.h */
void bfin_mmu_init(bfin_mmu_config_t *config) {
@@ -32,6 +32,7 @@ void bfin_mmu_init(bfin_mmu_config_t *config) {
*(uint32_t volatile *) data = config->instruction[i].flags;
data += ICPLB_DATA_PITCH;
}
*(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_ENICPLB;
addr = (intptr_t) DCPLB_ADDR0;
data = (intptr_t) DCPLB_DATA0;
for (i = 0; i < sizeof(config->data) / sizeof(config->data[0]); i++) {
@@ -40,5 +41,6 @@ void bfin_mmu_init(bfin_mmu_config_t *config) {
*(uint32_t volatile *) data = config->data[i].flags;
data += DCPLB_DATA_PITCH;
}
*(uint32_t volatile *) DMEM_CONTROL |= DMEM_CONTROL_ENDCPLB;
}

10
c/src/lib/libcpu/bfin/mmu/mmu.h
View File

@@ -25,12 +25,22 @@
#include <libcpu/mmuRegs.h>
#define INSTR_NOCACHE (ICPLB_DATA_CPLB_USER_RD | \
ICPLB_DATA_CPLB_VALID)
#define INSTR_CACHEABLE (ICPLB_DATA_CPLB_L1_CHBL | \
ICPLB_DATA_CPLB_USER_RD | \
ICPLB_DATA_CPLB_VALID)
#define DATA_NOCACHE (DCPLB_DATA_CPLB_DIRTY | \
DCPLB_DATA_CPLB_SUPV_WR | \
DCPLB_DATA_CPLB_USER_WR | \
DCPLB_DATA_CPLB_USER_RD | \
DCPLB_DATA_CPLB_VALID)
#define DATA_WRITEBACK (DCPLB_DATA_CPLB_L1_AOW | \
DCPLB_DATA_CPLB_L1_CHBL | \
DCPLB_DATA_CPLB_DIRTY | \
DCPLB_DATA_CPLB_SUPV_WR | \
DCPLB_DATA_CPLB_USER_WR | \
DCPLB_DATA_CPLB_USER_RD | \