dev/serial: Rework Zynq UART Doxygen groups

This commit is contained in:
Sebastian Huber
2024-08-30 09:29:00 +02:00
parent cf47b09c6a
commit 6efbf0c7b8
6 changed files with 25 additions and 19 deletions

View File

@@ -1,7 +1,9 @@
/**
* @file
* @ingroup zynq_uart_regs
* @brief UART register definitions.
*
* @ingroup RTEMSDeviceSerialZynq
*
* @brief This header file provides Zynq UART interfaces.
*/
/*
@@ -32,9 +34,12 @@
*/
/**
* @defgroup zynq_uart_regs UART Register Definitions
* @ingroup zynq_uart
* @brief UART Register Definitions
* @defgroup RTEMSDeviceSerialZynq Zynq UART Support
*
* @ingroup RTEMSDeviceConsole
*
* @brief This group contains the Zynq UART support.
*
* @{
*/

View File

@@ -3,7 +3,7 @@
/**
* @file
*
* @ingroup zynq_uart
* @ingroup RTEMSDeviceSerialZynq
*
* @brief This header file provides interfaces with respect to the Zynq
* platform.
@@ -42,7 +42,7 @@ extern "C" {
#endif /* __cplusplus */
/**
* @addtogroup zynq_uart
* @addtogroup RTEMSDeviceSerialZynq
*
* @{
*/

View File

@@ -3,7 +3,7 @@
/**
* @file
*
* @ingroup zynq_uart
* @ingroup RTEMSDeviceSerialZynq
*
* @brief This header file provides interfaces with respect to the Zynq
* UltraScale+ MPSoC and RFSoC platforms.
@@ -42,7 +42,7 @@ extern "C" {
#endif /* __cplusplus */
/**
* @addtogroup zynq_uart
* @addtogroup RTEMSDeviceSerialZynq
*
* @{
*/

View File

@@ -1,13 +1,15 @@
/**
* @file
* @ingroup zynq_uart
* @brief UART support.
*
* @ingroup RTEMSDeviceSerialZynq
*
* @brief This header file provides Zynq UART Termios driver interfaces.
*/
/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (C) 2013, XXX embedded brains GmbH & Co. KG
* Copyright (C) 2013, 2024 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,12 +43,9 @@ extern "C" {
#endif /* __cplusplus */
/**
* @defgroup zynq_uart UART Support
* @ingroup RTEMSBSPsARMZynq
* @brief UART Support
* @addtogroup RTEMSDeviceSerialZynq
*
* This driver operates an instance of the Cadence UART present in the
* family of Xilinx Zynq SoCs.
* @{
*/
typedef struct {
@@ -59,6 +58,8 @@ typedef struct {
extern const rtems_termios_device_handler zynq_uart_handler;
/** @} */
#ifdef __cplusplus
}
#endif /* __cplusplus */