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bsps/arm: reorganize CP15 code to allow clean and invalidate ARMv7 cache by level.

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New function arm_cp15_cache_invalidate_level and arm_cp15_cache_clean_level
can be used to maintain single cache level (instruction or data).
This commit is contained in:
Pavel Pisa
2016-09-03 01:59:21 +02:00
parent 5c49464108
commit 6e6a77a690
1 changed files with 60 additions and 48 deletions
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54
c/src/lib/libcpu/arm/shared/include/arm-cp15.h
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@@ -1083,24 +1083,15 @@ arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way)
} }
ARM_CP15_TEXT_SECTION static inline void ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_invalidate_all_levels(void) arm_cp15_cache_invalidate_level(uint32_t level, uint32_t inst_data_fl)
{ {
uint32_t clidr = arm_cp15_get_cache_level_id();
uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
uint32_t level = 0;
for (level = 0; level < loc; ++level) {
uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
/* Check if this level has a data cache or unified cache */
if (((ctype & (0x6)) == 2) || (ctype == 4)) {
uint32_t ccsidr; uint32_t ccsidr;
uint32_t line_power; uint32_t line_power;
uint32_t associativity; uint32_t associativity;
uint32_t way; uint32_t way;
uint32_t way_shift; uint32_t way_shift;
ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1); ccsidr = arm_cp15_get_cache_size_id_for_level((level << 1) | inst_data_fl);
line_power = arm_ccsidr_get_line_power(ccsidr); line_power = arm_ccsidr_get_line_power(ccsidr);
associativity = arm_ccsidr_get_associativity(ccsidr); associativity = arm_ccsidr_get_associativity(ccsidr);
@@ -1119,6 +1110,21 @@ arm_cp15_data_cache_invalidate_all_levels(void)
} }
} }
} }
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_invalidate_all_levels(void)
{
uint32_t clidr = arm_cp15_get_cache_level_id();
uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
uint32_t level = 0;
for (level = 0; level < loc; ++level) {
uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
/* Check if this level has a data cache or unified cache */
if (((ctype & (0x6)) == 2) || (ctype == 4)) {
arm_cp15_cache_invalidate_level(level, 0);
}
} }
} }
@@ -1155,17 +1161,8 @@ arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way)
} }
ARM_CP15_TEXT_SECTION static inline void ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_clean_all_levels(void) arm_cp15_data_cache_clean_level(uint32_t level)
{ {
uint32_t clidr = arm_cp15_get_cache_level_id();
uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
uint32_t level = 0;
for (level = 0; level < loc; ++level) {
uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
/* Check if this level has a data cache or unified cache */
if (((ctype & (0x6)) == 2) || (ctype == 4)) {
uint32_t ccsidr; uint32_t ccsidr;
uint32_t line_power; uint32_t line_power;
uint32_t associativity; uint32_t associativity;
@@ -1191,6 +1188,21 @@ arm_cp15_data_cache_clean_all_levels(void)
} }
} }
} }
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_data_cache_clean_all_levels(void)
{
uint32_t clidr = arm_cp15_get_cache_level_id();
uint32_t loc = arm_clidr_get_level_of_coherency(clidr);
uint32_t level = 0;
for (level = 0; level < loc; ++level) {
uint32_t ctype = arm_clidr_get_cache_type(clidr, level);
/* Check if this level has a data cache or unified cache */
if (((ctype & (0x6)) == 2) || (ctype == 4)) {
arm_cp15_data_cache_clean_level(level);
}
} }
} }