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bsps/stm32h7: Add SPI support

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This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
This commit is contained in:
Kinsey Moore
2024-07-25 19:13:23 -05:00
committed by Amar Takhar
parent bcf0cee545
commit 6dee307542
24 changed files with 1352 additions and 2 deletions
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67
bsps/arm/stm32h7/start/stm32h7-hal-spi.c Normal file
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@@ -0,0 +1,67 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsARMSTM32H7
*
* @brief This source file contains the SPI MSP initialization implementation.
*/
/*
* Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stm32h7/hal.h>
void HAL_SPI_MspInit(SPI_HandleTypeDef *spi)
{
stm32h7_spi_context *ctx;
const stm32h7_spi_config *config;
stm32h7_module_index index = stm32h7_get_module_index(spi->Instance);
ctx = RTEMS_CONTAINER_OF(spi, stm32h7_spi_context, spi);
config = ctx->config;
stm32h7_clk_enable(index);
stm32h7_gpio_init(&config->sck_gpio);
stm32h7_gpio_init(&config->miso_gpio);
stm32h7_gpio_init(&config->mosi_gpio);
/* Configure SPI CS GPIOs */
for (int i = 0; i < STM32H7_NUM_SOFT_CS; i++) {
if (config->cs_gpio[i].regs == NULL) {
continue;
}
/* TODO(kmoore) handle multiple pins in a single GPIO block */
/* configure GPIO CS and set output high */
stm32h7_gpio_init(&config->cs_gpio[i]);
/* Set all GPIO CS pins high */
HAL_GPIO_WritePin(config->cs_gpio[i].regs, config->cs_gpio[i].config.Pin, GPIO_PIN_SET);
}
}

24
bsps/arm/stm32h7/start/stm32h7-hal.c
View File

@@ -90,6 +90,18 @@ stm32h7_module_index stm32h7_get_module_index(const void *regs)
case SDMMC2_BASE:
case DLYB_SDMMC2_BASE:
return STM32H7_MODULE_SDMMC2;
case SPI1_BASE:
return STM32H7_MODULE_SPI1;
case SPI2_BASE:
return STM32H7_MODULE_SPI2;
case SPI3_BASE:
return STM32H7_MODULE_SPI3;
case SPI4_BASE:
return STM32H7_MODULE_SPI4;
case SPI5_BASE:
return STM32H7_MODULE_SPI5;
case SPI6_BASE:
return STM32H7_MODULE_SPI6;
}
return STM32H7_MODULE_INVALID;
@@ -151,6 +163,12 @@ static const stm32h7_clk_info stm32h7_clk[] = {
#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN },
[STM32H7_MODULE_SPI1] = { &RCC->APB2ENR, RCC_APB2ENR_SPI1EN },
[STM32H7_MODULE_SPI2] = { &RCC->APB1LENR, RCC_APB1LENR_SPI2EN },
[STM32H7_MODULE_SPI3] = { &RCC->APB1LENR, RCC_APB1LENR_SPI3EN },
[STM32H7_MODULE_SPI4] = { &RCC->APB2ENR, RCC_APB2ENR_SPI4EN },
[STM32H7_MODULE_SPI5] = { &RCC->APB2ENR, RCC_APB2ENR_SPI5EN },
[STM32H7_MODULE_SPI6] = { &RCC->APB4ENR, RCC_APB4ENR_SPI6EN },
};
void stm32h7_clk_enable(stm32h7_module_index index)
@@ -234,6 +252,12 @@ static const stm32h7_clk_info stm32h7_clk_low_power[] = {
#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3LPENR, RCC_AHB3LPENR_SDMMC1LPEN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN },
[STM32H7_MODULE_SPI1] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI1LPEN },
[STM32H7_MODULE_SPI2] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_SPI2LPEN },
[STM32H7_MODULE_SPI3] = { &RCC->APB1LLPENR, RCC_APB1LLPENR_SPI3LPEN },
[STM32H7_MODULE_SPI4] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI4LPEN },
[STM32H7_MODULE_SPI5] = { &RCC->APB2LPENR, RCC_APB2LPENR_SPI5LPEN },
[STM32H7_MODULE_SPI6] = { &RCC->APB4LPENR, RCC_APB4LPENR_SPI6LPEN },
};
void stm32h7_clk_low_power_enable(stm32h7_module_index index)