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Switched from presenting timing data based on CPU models to presenting it

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based on board model.
This commit is contained in:
Joel Sherrill
1998-08-13 21:24:50 +00:00
parent fba4a16cb0
commit 6ddf0543b4
19 changed files with 162 additions and 155 deletions
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1
doc/supplements/i386/FORCE386_TIMES
View File

@@ -7,6 +7,7 @@
#
# CPU Model Information
#
RTEMS_BSP CPU386
RTEMS_CPU_MODEL i386
#
# Interrupt Latency

2
doc/supplements/i386/Makefile
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@@ -61,7 +61,7 @@ timedata.texi: timedata.t FORCE386_TIMES
wksheets.t: ../../common/wksheets.t
sed -e 's/WORKSHEETS_PREVIOUS_LINK/Processor Dependent Information Table CPU Dependent Information Table/' \
-e 's/WORKSHEETS_NEXT_LINK/i386 Timing Data/' \
-e 's/WORKSHEETS_NEXT_LINK/CPU386 Timing Data/' \
<../../common/wksheets.t >wksheets.t
wksheets.texi: wksheets.t FORCE386_TIMES

4
doc/supplements/i386/i386.texi
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@@ -91,7 +91,7 @@ Applications Supplement.
* Processor Dependent Information Table::
* Memory Requirements::
* Timing Specification::
* i386 Timing Data::
* CPU386 Timing Data::
* Command and Variable Index::
* Concept Index::
@end menu
@@ -102,7 +102,7 @@ Applications Supplement.
@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
@c
@node Command and Variable Index, Concept Index, i386 Timing Data Rate Monotonic Manager, Top
@node Command and Variable Index, Concept Index, CPU386 Timing Data Rate Monotonic Manager, Top
@unnumbered Command and Variable Index
There are currently no Command and Variable Index entries.

48
doc/supplements/i386/timeFORCE386.t
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@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node i386 Timing Data, i386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CPU386 Timing Data, CPU386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter i386 Timing Data
@chapter CPU386 Timing Data
@ifinfo
@menu
* i386 Timing Data Introduction::
* i386 Timing Data Hardware Platform::
* i386 Timing Data Interrupt Latency::
* i386 Timing Data Context Switch::
* i386 Timing Data Directive Times::
* i386 Timing Data Task Manager::
* i386 Timing Data Interrupt Manager::
* i386 Timing Data Clock Manager::
* i386 Timing Data Timer Manager::
* i386 Timing Data Semaphore Manager::
* i386 Timing Data Message Manager::
* i386 Timing Data Event Manager::
* i386 Timing Data Signal Manager::
* i386 Timing Data Partition Manager::
* i386 Timing Data Region Manager::
* i386 Timing Data Dual-Ported Memory Manager::
* i386 Timing Data I/O Manager::
* i386 Timing Data Rate Monotonic Manager::
* CPU386 Timing Data Introduction::
* CPU386 Timing Data Hardware Platform::
* CPU386 Timing Data Interrupt Latency::
* CPU386 Timing Data Context Switch::
* CPU386 Timing Data Directive Times::
* CPU386 Timing Data Task Manager::
* CPU386 Timing Data Interrupt Manager::
* CPU386 Timing Data Clock Manager::
* CPU386 Timing Data Timer Manager::
* CPU386 Timing Data Semaphore Manager::
* CPU386 Timing Data Message Manager::
* CPU386 Timing Data Event Manager::
* CPU386 Timing Data Signal Manager::
* CPU386 Timing Data Partition Manager::
* CPU386 Timing Data Region Manager::
* CPU386 Timing Data Dual-Ported Memory Manager::
* CPU386 Timing Data I/O Manager::
* CPU386 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node i386 Timing Data Introduction, i386 Timing Data Hardware Platform, i386 Timing Data, i386 Timing Data
@node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i386 version of RTEMS.
@ifinfo
@node i386 Timing Data Hardware Platform, i386 Timing Data Interrupt Latency, i386 Timing Data Introduction, i386 Timing Data
@node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data
@end ifinfo
@section Hardware Platform
@@ -74,7 +74,7 @@ instructions to disable and enable interrupts, was divided by 16
to simulate a i386 executing at 16 Mhz.
@ifinfo
@node i386 Timing Data Interrupt Latency, i386 Timing Data Context Switch, i386 Timing Data Hardware Platform, i386 Timing Data
@node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -99,7 +99,7 @@ Computers CPU386 benchmark platform using the int instruction as
the interrupt source.
@ifinfo
@node i386 Timing Data Context Switch, i386 Timing Data Directive Times, i386 Timing Data Interrupt Latency, i386 Timing Data
@node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data
@end ifinfo
@section Context Switch

48
doc/supplements/i386/timedata.t
View File

@@ -12,34 +12,34 @@
@end tex
@ifinfo
@node i386 Timing Data, i386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@node CPU386 Timing Data, CPU386 Timing Data Introduction, Memory Requirements RTEMS RAM Workspace Worksheet, Top
@end ifinfo
@chapter i386 Timing Data
@chapter CPU386 Timing Data
@ifinfo
@menu
* i386 Timing Data Introduction::
* i386 Timing Data Hardware Platform::
* i386 Timing Data Interrupt Latency::
* i386 Timing Data Context Switch::
* i386 Timing Data Directive Times::
* i386 Timing Data Task Manager::
* i386 Timing Data Interrupt Manager::
* i386 Timing Data Clock Manager::
* i386 Timing Data Timer Manager::
* i386 Timing Data Semaphore Manager::
* i386 Timing Data Message Manager::
* i386 Timing Data Event Manager::
* i386 Timing Data Signal Manager::
* i386 Timing Data Partition Manager::
* i386 Timing Data Region Manager::
* i386 Timing Data Dual-Ported Memory Manager::
* i386 Timing Data I/O Manager::
* i386 Timing Data Rate Monotonic Manager::
* CPU386 Timing Data Introduction::
* CPU386 Timing Data Hardware Platform::
* CPU386 Timing Data Interrupt Latency::
* CPU386 Timing Data Context Switch::
* CPU386 Timing Data Directive Times::
* CPU386 Timing Data Task Manager::
* CPU386 Timing Data Interrupt Manager::
* CPU386 Timing Data Clock Manager::
* CPU386 Timing Data Timer Manager::
* CPU386 Timing Data Semaphore Manager::
* CPU386 Timing Data Message Manager::
* CPU386 Timing Data Event Manager::
* CPU386 Timing Data Signal Manager::
* CPU386 Timing Data Partition Manager::
* CPU386 Timing Data Region Manager::
* CPU386 Timing Data Dual-Ported Memory Manager::
* CPU386 Timing Data I/O Manager::
* CPU386 Timing Data Rate Monotonic Manager::
@end menu
@end ifinfo
@ifinfo
@node i386 Timing Data Introduction, i386 Timing Data Hardware Platform, i386 Timing Data, i386 Timing Data
@node CPU386 Timing Data Introduction, CPU386 Timing Data Hardware Platform, CPU386 Timing Data, CPU386 Timing Data
@end ifinfo
@section Introduction
@@ -52,7 +52,7 @@ is a description of the interrupt latency and the context
switch times as they pertain to the i386 version of RTEMS.
@ifinfo
@node i386 Timing Data Hardware Platform, i386 Timing Data Interrupt Latency, i386 Timing Data Introduction, i386 Timing Data
@node CPU386 Timing Data Hardware Platform, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Introduction, CPU386 Timing Data
@end ifinfo
@section Hardware Platform
@@ -74,7 +74,7 @@ instructions to disable and enable interrupts, was divided by 16
to simulate a i386 executing at 16 Mhz.
@ifinfo
@node i386 Timing Data Interrupt Latency, i386 Timing Data Context Switch, i386 Timing Data Hardware Platform, i386 Timing Data
@node CPU386 Timing Data Interrupt Latency, CPU386 Timing Data Context Switch, CPU386 Timing Data Hardware Platform, CPU386 Timing Data
@end ifinfo
@section Interrupt Latency
@@ -99,7 +99,7 @@ Computers CPU386 benchmark platform using the int instruction as
the interrupt source.
@ifinfo
@node i386 Timing Data Context Switch, i386 Timing Data Directive Times, i386 Timing Data Interrupt Latency, i386 Timing Data
@node CPU386 Timing Data Context Switch, CPU386 Timing Data Directive Times, CPU386 Timing Data Interrupt Latency, CPU386 Timing Data
@end ifinfo
@section Context Switch