RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsp/mpc55xx: Fix no-cache section load

Browse Source
This commit is contained in:
Sebastian Huber
2012-11-13 11:50:38 +01:00
parent 353f0fa125
commit 6c4541048a
7 changed files with 49 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
View File

@@ -168,7 +168,7 @@ RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5566EVB],[if defined, use custom settings f
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_GWLCFM],[gwlcfm],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_GWLCFM],[if defined, use custom settings for GWLCFM board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674F_ECU508],[mpc5674f_ecu508_boot],[1])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674F_ECU508],[mpc5674f_ecu508*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674F_ECU508],[if defined, use custom settings for ECU508 board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_PHYCORE_MPC5554],[phycore_mpc5554],[1])

3
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-ebi-cs-cal.c
View File

@@ -75,7 +75,8 @@ BSP_START_TEXT_SECTION const struct EBI_CAL_CS_tag
}
}
}
#elif defined(MPC55XX_BOARD_MPC5674F_ECU508)
#elif defined(MPC55XX_BOARD_MPC5674F_ECU508) \
&& defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
/* D_CS0 for external SRAM */
{
.BR = {

6
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu-early.c
View File

@@ -25,7 +25,11 @@
BSP_START_TEXT_SECTION const struct MMU_tag
mpc55xx_start_config_mmu_early [] = {
#if MPC55XX_CHIP_FAMILY == 555
#if defined(MPC55XX_BOARD_MPC5674F_ECU508) \
&& !defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
/* Used as cache-inhibited area later (ADC, DSPI queues) */
MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 0)
#elif MPC55XX_CHIP_FAMILY == 555
/* Internal SRAM 96k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 1, 1, 1, 0),
#elif MPC55XX_CHIP_FAMILY == 556

58
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c
View File

@@ -75,31 +75,39 @@ BSP_START_TEXT_SECTION const struct MMU_tag
/* External Ethernet controller */
MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
#elif defined(MPC55XX_BOARD_MPC5674F_ECU508)
/* Arguments macro: idx, addr, size, x, w, r, io */
/* Internal flash 4M */
MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0), /* first 64k unused, to detect null-pointer access */
MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
/* External SRAM 2M */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 0),
/* Internal SRAM 256k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000 + 0 * 1024, MPC55XX_MMU_256K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(11, 0x40000000 + 128 * 1024, MPC55XX_MMU_64K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(12, 0x40000000 + 192 * 1024, MPC55XX_MMU_32K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(13, 0x40000000 + 224 * 1024, MPC55XX_MMU_16K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000 + 240 * 1024, MPC55XX_MMU_16K, 0, 1, 1, 1), // used as cache-inhibited area (ADC, DSPI queues)
/* External Ethernet controller */
MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_1K, 0, 1, 1, 1),
/* External MRAM 128k */
MPC55XX_MMU_TAG_INITIALIZER(16, 0x3ffa0000, MPC55XX_MMU_128K, 0, 1, 1, 0),
/* External ARCNET controller */
MPC55XX_MMU_TAG_INITIALIZER(17, 0x3ffc0000, MPC55XX_MMU_1K, 0, 1, 1, 1)
/* Peripheral Bridge A-Registers on MMU-table pos 4 */
/* Peripheral Bridge B-Registers on MMU-table pos 0 */
#if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
/* Arguments macro: idx, addr, size, x, w, r, io */
/* Internal flash 4M */
/* First 64k unused, to detect null-pointer access */
MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
/* External SRAM 2M */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 0),
/* Internal SRAM 256k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0),
/* Used as cache-inhibited area (ADC, DSPI queues) */
MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1),
/* External Ethernet controller */
MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_1K, 0, 1, 1, 1),
/* External MRAM 128k */
MPC55XX_MMU_TAG_INITIALIZER(16, 0x3ffa0000, MPC55XX_MMU_128K, 0, 1, 1, 0),
/* External ARCNET controller */
MPC55XX_MMU_TAG_INITIALIZER(17, 0x3ffc0000, MPC55XX_MMU_1K, 0, 1, 1, 1)
/* Peripheral Bridge A-Registers on MMU-table pos 4 */
/* Peripheral Bridge B-Registers on MMU-table pos 0 */
#else
/* Used as cache-inhibited area (ADC, DSPI queues) */
MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1),
#endif
#elif MPC55XX_CHIP_FAMILY == 564
/* Internal flash 1M */
MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0),

3
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-siu-pcr.c
View File

@@ -112,7 +112,8 @@ BSP_START_TEXT_SECTION const mpc55xx_siu_pcr_config
{ 294, 6, 0, { .B = { .PA = 1, .DSC = 1 } } }, /* D_RD_WR, D_WE0, D_WE1, D_OE, D_TS, D_ALE */
{ 301, 1, 0, { .B = { .PA = 1, .DSC = 1 } } }, /* D_CS1 */
{ 302, 6, 0, { .B = { .PA = 1, .DSC = 1 } } } /* D_BDIP, D_WE2, D_WE3, D_ADD9 .. D_ADD11 */
#elif defined(MPC55XX_BOARD_MPC5674F_ECU508)
#elif defined(MPC55XX_BOARD_MPC5674F_ECU508) \
&& defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
{ 196, 2, 0, { .B = { .PA = 0, .OBE = 1, .WPE = 0 } } }, /* EMIOS17 .. EMIOS18 (5VS_EN, 80V_EN) */
{ 200, 4, 0, { .B = { .PA = 0, .OBE = 1, .WPE = 0 } } }, /* EMIOS21 .. EMIOS24 (\KS_RST, \LS_RST, \IGNINJ_RST, \INJDI_RST) */
{ 204, 1, 1, { .B = { .PA = 0, .OBE = 1, .WPE = 0 } } }, /* EMIOS25 (HBR12_RST) */

3
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c
View File

@@ -174,7 +174,8 @@ static BSP_START_TEXT_SECTION void mpc55xx_start_ebi(void)
EBI.MCR.B.D16_31 = 1; /* use lower AD bus */
SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
#elif defined(MPC55XX_BOARD_MPC5674FEVB) || defined(MPC55XX_BOARD_MPC5674F_ECU508)
#elif defined(MPC55XX_BOARD_MPC5674FEVB) \
|| defined(MPC55XX_BOARD_MPC5674F_ECU508)
union EBI_MCR_tag mcr = {
.B = {
.ACGE = 0,

4
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
View File

@@ -174,11 +174,15 @@ _start:
LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BPEN
mtspr FSL_EIS_BUCSR, r3
#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
/* MMU early initialization */
LA r3, mpc55xx_start_config_mmu_early
LW r4, mpc55xx_start_config_mmu_early_count
bl mpc55xx_start_mmu_apply_config
#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
/* Initialize intermediate stack (ECC) */
LA r3, bsp_ram_start