bsps/riscv: Add Microchip PolarFire SoC BSP variant

The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.

spec/build/bsps/riscv/optextirqmax.yml

@@ -6,7 +6,10 @@ build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
 default: 64
-default-by-variant: []
+default-by-variant:
+- value: 187
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of external interrupts supported by the BSP (default 64)
 enabled-by: true

spec/build/bsps/riscv/optrambegin.yml

@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -22,6 +22,9 @@ default-by-variant:
 - value: 1073741824
   variants:
   - riscv/griscv
+- value: 68719476736
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'

spec/build/bsps/riscv/optramsize.yml

@@ -1,7 +1,7 @@
 SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
 actions:
 - get-integer: null
-- assert-uint32: null
+- assert-uint64: null
 - assert-aligned: 1048576
 - env-assign: null
 - format-and-define: null
@@ -16,6 +16,9 @@ default-by-variant:
 - value: 16777216
   variants:
   - riscv/griscv
+- value: 268435456
+  variants:
+  - riscv/mpfs64.*
 description: ''
 enabled-by: true
 format: '{:#010x}'

spec/build/bsps/riscv/riscv/abi.yml

@@ -10,6 +10,12 @@ default:
 - -march=rv32imac
 - -mabi=ilp32
 default-by-variant:
+- value:
+  - -march=rv64imafdc
+  - -mabi=lp64d
+  - -mcmodel=medany
+  variants:
+  - riscv/mpfs64imafdc
 - value:
   - -march=rv64imafdc
   - -mabi=lp64d

spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: mpfs64imafdc
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build

spec/build/bsps/riscv/riscv/grp.yml

@@ -44,10 +44,16 @@ links:
   uid: ../../optfdtro
 - role: build-dependency
   uid: ../../optfdtuboot
+- role: build-dependency
+  uid: ../../optdtb
+- role: build-dependency
+  uid: ../../optdtbheaderpath
 - role: build-dependency
   uid: optfrdme310arty
 - role: build-dependency
   uid: opthtif
+- role: build-dependency
+  uid: optmpfs
 - role: build-dependency
   uid: optns16550max
 - role: build-dependency

spec/build/bsps/riscv/riscv/optmpfs.yml

@@ -0,0 +1,18 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: false
+default-by-variant:
+- value: true
+  variants:
+  - riscv/mpfs64.*
+description: |
+  enables support Microchip PolarFire SoC if defined to a non-zero value,otherwise it is disabled (disabled by default)
+enabled-by: true
+links: []
+name: RISCV_ENABLE_MPFS_SUPPORT
+type: build

spec/build/bsps/riscv/riscv/optns16550max.yml

@@ -10,6 +10,9 @@ default-by-variant:
 - value: null
   variants:
   - riscv/frdme310arty.*
+- value: 1
+  variants:
+  - riscv/mpfs64.*
 description: |
   maximum number of NS16550 devices supported by the console driver (2 by default)
 enabled-by: true

spec/build/cpukit/cpuopts.yml

@@ -33,6 +33,8 @@ links:
   uid: optinstall
 - role: build-dependency
   uid: optada
+- role: build-dependency
+  uid: optboothartid
 - role: build-dependency
   uid: optbuildlabel
 - role: build-dependency

spec/build/cpukit/optarchbits.yml

@@ -11,6 +11,7 @@ default-by-variant:
 - value:
   - '64'
   variants:
+  - riscv/mpfs64.*
   - riscv/noel64.*
   - riscv/rv64.*
 - value:

spec/build/cpukit/optboothartid.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- define: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default: 0
+default-by-variant:
+- value: 1
+  variants:
+  - riscv/mpfs64.*
+description: |
+  boot hartid (processor number) of risc-v cpu (default 0)
+enabled-by: true
+format: '{}'
+links: []
+name: RISCV_BOOT_HARTID
+type: build

spec/build/cpukit/optsmp.yml

@@ -31,6 +31,7 @@ enabled-by:
 - riscv/griscv
 - riscv/grv32imac
 - riscv/grv32imafdc
+- riscv/mpfs64imafdc
 - riscv/noel32imafd
 - riscv/noel64imac
 - riscv/noel64imafdc