forked from Imagelibrary/rtems
PR2041: sparc64: vector number not included in CPU_Interrupt_frame
Add the trap vector to the interrupt frame. Also rename the assembly macro that accesses the field to be consistent with similar macros.
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@@ -118,7 +118,7 @@ PUBLIC(_ISR_Handler)
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stx %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET]
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stx %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET]
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stx %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET]
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stx %g2, [%sp + STACK_BIAS + ISF_TVEC_NUM]
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stx %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET]
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rd %y, %g4 ! save y
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stx %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET]
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@@ -522,7 +522,7 @@ dispatchAgain:
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ldx [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4
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ldx [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5
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ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
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ldx [%sp + STACK_BIAS + ISF_TVEC_NUM], %g2
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ldx [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2
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wrpr %g0, %g3, %pil
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wrpr %g0, %g4, %tpc
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wrpr %g0, %g5, %tnpc
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@@ -519,6 +519,7 @@ typedef struct {
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uint64_t o5;
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uint64_t o6_sp;
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uint64_t o7;
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uint64_t tvec;
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} CPU_Interrupt_frame;
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#endif /* ASM */
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@@ -548,7 +549,7 @@ typedef struct {
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#define ISF_O5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x88
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#define ISF_O6_SP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x90
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#define ISF_O7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x98
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#define ISF_TVEC_NUM CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0
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#define ISF_TVEC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0
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#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8
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#ifndef ASM
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