forked from Imagelibrary/rtems
Patch from Eric VALETTE <valette@crf.canon.fr>:
Here is a enhanced version of my previous patch. This patch enables
to potentially share the new interrupt management code for all Intel targets
(pc386, go32 and force386) bsp.
Note : this patch is complete only for pc386. It still needs to
be completed for go32 and force386. I carrefully checked
that anything needed is in for force386 (only some function
name changes for IDT manipulation and GDT segment
manipulation). But anyway I will not be able to test any
of theses targets...
This commit is contained in:
Joel Sherrill
200
c/src/lib/libbsp/i386/shared/irq/irq_init.c
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200
c/src/lib/libbsp/i386/shared/irq/irq_init.c
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@@ -0,0 +1,200 @@
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/* irq_init.c
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*
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* This file contains the implementation of rtems initialization
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* related to interrupt handling.
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*
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* CopyRight (C) 1998 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#include <libcpu/cpu.h>
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#include <irq.h>
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#include <bsp.h>
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/*
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* rtems prologue generated in irq_asm.S
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*/
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extern void rtems_irq_prologue_0();
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extern void rtems_irq_prologue_1();
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extern void rtems_irq_prologue_2();
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extern void rtems_irq_prologue_3();
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extern void rtems_irq_prologue_4();
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extern void rtems_irq_prologue_5();
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extern void rtems_irq_prologue_6();
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extern void rtems_irq_prologue_7();
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extern void rtems_irq_prologue_8();
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extern void rtems_irq_prologue_9();
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extern void rtems_irq_prologue_10();
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extern void rtems_irq_prologue_11();
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extern void rtems_irq_prologue_12();
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extern void rtems_irq_prologue_13();
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extern void rtems_irq_prologue_14();
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extern void rtems_irq_prologue_15();
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/*
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* default idt vector
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*/
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extern void default_raw_idt_handler();
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/*
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* default on/off function
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*/
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static void nop_func(){}
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/*
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* default isOn function
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*/
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static int not_connected() {return 0;}
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static rtems_raw_irq_connect_data idtHdl[IDT_SIZE];
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/*
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* Table used to store rtems managed interrupt handlers.
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* Borrow the table to store raw handler entries at the beginning.
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* The table will be reinitialized before the call to pc386_rtems_irq_mngt_set().
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*/
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static rtems_irq_connect_data rtemsIrq[PC_386_IRQ_LINES_NUMBER] = {
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{0,(rtems_irq_hdl)rtems_irq_prologue_0},
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{0,(rtems_irq_hdl)rtems_irq_prologue_1},
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{0,(rtems_irq_hdl)rtems_irq_prologue_2},
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{0,(rtems_irq_hdl)rtems_irq_prologue_3},
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{0,(rtems_irq_hdl)rtems_irq_prologue_4},
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{0,(rtems_irq_hdl)rtems_irq_prologue_5},
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{0,(rtems_irq_hdl)rtems_irq_prologue_6},
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{0,(rtems_irq_hdl)rtems_irq_prologue_7},
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{0,(rtems_irq_hdl)rtems_irq_prologue_8},
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{0,(rtems_irq_hdl)rtems_irq_prologue_9},
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{0,(rtems_irq_hdl)rtems_irq_prologue_10},
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{0,(rtems_irq_hdl)rtems_irq_prologue_11},
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{0,(rtems_irq_hdl)rtems_irq_prologue_12},
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{0,(rtems_irq_hdl)rtems_irq_prologue_13},
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{0,(rtems_irq_hdl)rtems_irq_prologue_14},
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{0,(rtems_irq_hdl)rtems_irq_prologue_15}
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};
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static rtems_raw_irq_connect_data defaultRawIrq = {
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/* vectorIdex, hdl , on , off , isOn */
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0, default_raw_idt_handler ,nop_func , nop_func, not_connected
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};
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static rtems_irq_connect_data defaultIrq = {
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/* vectorIdex, hdl , on , off , isOn */
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0, nop_func , nop_func , nop_func , not_connected
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};
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static rtems_irq_prio irqPrioTable[PC_386_IRQ_LINES_NUMBER]={
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/*
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* actual rpiorities for interrupt :
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* 0 means that only current interrupt is masked
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* 255 means all other interrupts are masked
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* The second entry has a priority of 255 because
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* it is the slave pic entry and is should always remain
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* unamsked.
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*/
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0,0,
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255,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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};
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static interrupt_gate_descriptor idtEntry;
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static rtems_irq_global_settings initial_config;
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static rtems_raw_irq_global_settings raw_initial_config;
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void raw_idt_notify()
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{
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printk("raw_idt_notify has been called \n");
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}
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void rtems_irq_mngt_init()
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{
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int i;
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interrupt_gate_descriptor* idt_entry_tbl;
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unsigned limit;
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unsigned int level;
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i386_get_info_from_IDTR (&idt_entry_tbl, &limit);
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_CPU_ISR_Disable(level);
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/*
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* Init the complete IDT vector table with defaultRawIrq value
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*/
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for (i = 0; i < IDT_SIZE; i++) {
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idtHdl[i] = defaultRawIrq;
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}
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raw_initial_config.idtSize = IDT_SIZE;
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raw_initial_config.defaultRawEntry = defaultRawIrq;
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raw_initial_config.rawIrqHdlTbl = idtHdl;
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if (!i386_init_idt (&raw_initial_config)) {
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/*
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* put something here that will show the failure...
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*/
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_IBMPC_initVideo();
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printk("Unable to initialize IDT!!! System locked\n");
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while (1);
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}
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/*
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* Patch the entry that will be used by RTEMS for interrupt management
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* with RTEMS prologue.
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*/
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for (i = 0; i < PC_386_IRQ_LINES_NUMBER; i++) {
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create_interrupt_gate_descriptor(&idtEntry,(rtems_raw_irq_hdl) rtemsIrq[i].hdl);
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idt_entry_tbl[i + PC386_ASM_IRQ_VECTOR_BASE] = idtEntry;
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}
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/*
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* At this point we have completed the initialization of IDT
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* with raw handlers. We must now initialize the higher level
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* interrupt management.
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*/
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/*
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* re-init the rtemsIrq table
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*/
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for (i = 0; i < PC_386_IRQ_LINES_NUMBER; i++) {
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rtemsIrq[i] = defaultIrq;
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}
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/*
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* Init initial Interrupt management config
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*/
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initial_config.irqNb = PC_386_IRQ_LINES_NUMBER;
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initial_config.defaultEntry = defaultIrq;
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initial_config.irqHdlTbl = rtemsIrq;
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initial_config.irqBase = PC386_ASM_IRQ_VECTOR_BASE;
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initial_config.irqPrioTbl = irqPrioTable;
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if (!pc386_rtems_irq_mngt_set(&initial_config)) {
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/*
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* put something here that will show the failure...
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*/
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_IBMPC_initVideo();
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printk("Unable to initialize RTEMS interrupt Management!!! System locked\n");
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while (1);
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}
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#define DEBUG
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#ifdef DEBUG
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{
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/*
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* following adresses should be the same
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*/
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unsigned tmp;
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_IBMPC_initVideo();
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printk("idt_entry_tbl = %x Interrupt_descriptor_table addr = %x\n",
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idt_entry_tbl, &Interrupt_descriptor_table);
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tmp = (unsigned) get_hdl_from_vector (PC386_ASM_IRQ_VECTOR_BASE + PC_386_PERIODIC_TIMER);
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printk("clock isr address from idt = %x should be %x\n",
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tmp, (unsigned) rtems_irq_prologue_0);
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}
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printk("i8259s_cache = %x\n", * (unsigned short*) &i8259s_cache);
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debugPollingGetChar();
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#endif
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asm volatile ("sti");
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}
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