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cpukit: Add Epiphany architecture port v4

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This commit is contained in:
Hesham ALMatary
2015-05-21 17:52:56 +01:00
committed by Gedare Bloom
parent 63c68cfcaf
commit 66a5000d78
16 changed files with 2492 additions and 0 deletions
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1
cpukit/configure.ac
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@@ -453,6 +453,7 @@ score/cpu/Makefile
score/cpu/arm/Makefile score/cpu/arm/Makefile
score/cpu/bfin/Makefile score/cpu/bfin/Makefile
score/cpu/avr/Makefile score/cpu/avr/Makefile
score/cpu/epiphany/Makefile
score/cpu/h8300/Makefile score/cpu/h8300/Makefile
score/cpu/i386/Makefile score/cpu/i386/Makefile
score/cpu/lm32/Makefile score/cpu/lm32/Makefile

1
cpukit/librpc/src/xdr/xdr_float.c
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@@ -61,6 +61,7 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
#if defined(__alpha__) || \ #if defined(__alpha__) || \
defined(_AM29K) || \ defined(_AM29K) || \
defined(__arm__) || \ defined(__arm__) || \
defined(__epiphany__) || defined(__EPIPHANY__) || \
defined(__H8300__) || defined(__h8300__) || \ defined(__H8300__) || defined(__h8300__) || \
defined(__hppa__) || \ defined(__hppa__) || \
defined(__i386__) || \ defined(__i386__) || \

1
cpukit/score/cpu/Makefile.am
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@@ -4,6 +4,7 @@ DIST_SUBDIRS =
DIST_SUBDIRS += arm DIST_SUBDIRS += arm
DIST_SUBDIRS += avr DIST_SUBDIRS += avr
DIST_SUBDIRS += bfin DIST_SUBDIRS += bfin
DIST_SUBDIRS += epiphany
DIST_SUBDIRS += h8300 DIST_SUBDIRS += h8300
DIST_SUBDIRS += i386 DIST_SUBDIRS += i386
DIST_SUBDIRS += lm32 DIST_SUBDIRS += lm32

32
cpukit/score/cpu/epiphany/Makefile.am Normal file
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@@ -0,0 +1,32 @@
include $(top_srcdir)/automake/compile.am
CLEANFILES =
DISTCLEANFILES =
include_rtemsdir = $(includedir)/rtems
include_rtems_HEADERS = rtems/asm.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS =
include_rtems_score_HEADERS += rtems/score/cpu.h
include_rtems_score_HEADERS += rtems/score/cpuatomic.h
include_rtems_score_HEADERS += rtems/score/cpu_asm.h
include_rtems_score_HEADERS += rtems/score/types.h
include_rtems_score_HEADERS += rtems/score/epiphany.h
include_rtems_score_HEADERS += rtems/score/epiphany-utility.h
noinst_LIBRARIES = libscorecpu.a
libscorecpu_a_SOURCES = cpu.c
libscorecpu_a_SOURCES += epiphany-exception-handler.S
libscorecpu_a_SOURCES += epiphany-context-switch.S
libscorecpu_a_SOURCES += epiphany-context-initialize.c
libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
all-local: $(PREINSTALL_FILES)
include $(srcdir)/preinstall.am
include $(top_srcdir)/automake/local.am

114
cpukit/score/cpu/epiphany/cpu.c Normal file
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@@ -0,0 +1,114 @@
/*
* Epiphany CPU Dependent Source
*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
#include <bsp/linker-symbols.h>
#include <rtems/score/cpu.h>
void init(void);
void fini(void);
void _init()
{
}
void _fini()
{
}
void _CPU_Exception_frame_print (const CPU_Exception_frame *ctx)
{
/* Do nothing */
}
/**
* @brief Performs processor dependent initialization.
*/
void _CPU_Initialize(void)
{
/* Do nothing */
}
void _CPU_ISR_Set_level(uint32_t level)
{
/* Do nothing */
}
uint32_t _CPU_ISR_Get_level( void )
{
/* Do nothing */
return 0;
}
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/* Do nothing */
}
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
/* Do nothing */
}
void _CPU_Install_interrupt_stack( void )
{
/* Do nothing */
}
CPU_Counter_ticks _CPU_Counter_read( void )
{
static CPU_Counter_ticks counter;
CPU_Counter_ticks snapshot;
snapshot = counter;
counter = snapshot + 1;
return snapshot;
}
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
do {
__asm__ __volatile__ ("idle");
} while (1);
return NULL;
}

66
cpukit/score/cpu/epiphany/epiphany-context-initialize.c Normal file
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@@ -0,0 +1,66 @@
/*
*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* COPYRIGHT (c) 1989-2006.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include <rtems/score/cpu.h>
#include <rtems/score/interr.h>
void _CPU_Context_Initialize(
Context_Control *context,
void *stack_area_begin,
size_t stack_area_size,
uint32_t new_level,
void (*entry_point)( void ),
bool is_fp,
void *tls_area
)
{
uintptr_t stack = ((uintptr_t) stack_area_begin);
uint32_t sr, iret;
/* Account for red-zone */
uintptr_t stack_high = stack + stack_area_size - EPIPHANY_GCC_RED_ZONE_SIZE;
asm volatile ("movfs %0, status \n" : "=r" (sr):);
asm volatile ("movfs %0, iret \n" : "=r" (iret):);
memset(context, 0, sizeof(*context));
context->r[11] = stack_high;
context->r[13] = stack_high;
context->r[14] = (uintptr_t) entry_point;
context->status = sr;
context->iret = iret;
}

216
cpukit/score/cpu/epiphany/epiphany-context-switch.S Normal file
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@@ -0,0 +1,216 @@
/*
* Epiphany CPU Dependent Source
*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/asm.h>
.section .text,"ax"
.align 4
PUBLIC(_CPU_Context_switch)
PUBLIC(_CPU_Context_restore)
PUBLIC(_CPU_Context_restore_fp)
PUBLIC(_CPU_Context_save_fp)
PUBLIC(restore)
SYM(_CPU_Context_switch):
/* Disable interrupts and store all registers */
gid
str r0, [r0]
str r1, [r0,1]
str r2, [r0,2]
str r3, [r0,3]
str r4, [r0,4]
str r5, [r0,5]
str r6, [r0,6]
str r7, [r0,7]
str r8, [r0,8]
str r9, [r0,9]
str r10, [r0,10]
str fp, [r0,11]
str r12, [r0,12]
str sp, [r0,13]
str lr, [r0,14]
str r15, [r0,15]
str r16, [r0,16]
str r17, [r0,17]
str r18, [r0,18]
str r19, [r0,19]
str r20, [r0,20]
str r21, [r0,21]
str r22, [r0,22]
str r23, [r0,23]
str r24, [r0,24]
str r25, [r0,25]
str r26, [r0,26]
str r27, [r0,27]
str r28, [r0,28]
str r29, [r0,29]
str r30, [r0,30]
str r31, [r0,31]
str r32, [r0,32]
str r33, [r0,33]
str r34, [r0,34]
str r35, [r0,35]
str r36, [r0,36]
str r37, [r0,37]
str r38, [r0,38]
str r39, [r0,39]
str r40, [r0,40]
str r41, [r0,41]
str r42, [r0,42]
str r43, [r0,43]
str r44, [r0,44]
str r45, [r0,45]
str r46, [r0,46]
str r47, [r0,47]
str r48, [r0,48]
str r49, [r0,49]
str r50, [r0,50]
str r51, [r0,51]
str r52, [r0,52]
str r53, [r0,53]
str r54, [r0,54]
str r55, [r0,55]
str r56, [r0,56]
str r57, [r0,57]
str r58, [r0,58]
str r59, [r0,59]
str r60, [r0,60]
str r61, [r0,61]
str r62, [r0,62]
str r63, [r0,63]
/* Store status register */
movfs r27, status
str r27, [r0,64]
/* Store config register */
movfs r27, config
str r27, [r0,65]
/* Store interrupt return address register */
movfs r27, iret
str r27, [r0,66]
SYM(restore):
/* r1 contains buffer address, skip it */
ldr r2, [r1,2]
ldr r3, [r1,3]
ldr r4, [r1,4]
ldr r5, [r1,5]
ldr r6, [r1,6]
ldr r7, [r1,7]
ldr r8, [r1,8]
ldr r9, [r1,9]
ldr r10, [r1,10]
ldr fp, [r1,11]
ldr r12, [r1,12]
ldr sp, [r1,13]
ldr lr, [r1,14]
ldr r15, [r1,15]
ldr r16, [r1,16]
ldr r17, [r1,17]
ldr r18, [r1,18]
ldr r19, [r1,19]
ldr r20, [r1,20]
ldr r21, [r1,21]
ldr r22, [r1,22]
ldr r23, [r1,23]
ldr r24, [r1,24]
ldr r25, [r1,25]
ldr r26, [r1,26]
ldr r27, [r1,27]
ldr r32, [r1,32]
ldr r33, [r1,33]
ldr r34, [r1,34]
ldr r35, [r1,35]
ldr r36, [r1,36]
ldr r37, [r1,37]
ldr r38, [r1,38]
ldr r39, [r1,39]
ldr r40, [r1,40]
ldr r41, [r1,41]
ldr r42, [r1,42]
ldr r43, [r1,43]
ldr r44, [r1,44]
ldr r45, [r1,45]
ldr r46, [r1,46]
ldr r47, [r1,47]
ldr r48, [r1,48]
ldr r49, [r1,49]
ldr r50, [r1,50]
ldr r51, [r1,51]
ldr r52, [r1,52]
ldr r53, [r1,53]
ldr r54, [r1,54]
ldr r55, [r1,55]
ldr r56, [r1,56]
ldr r57, [r1,57]
ldr r58, [r1,58]
ldr r59, [r1,59]
ldr r60, [r1,60]
ldr r61, [r1,61]
ldr r62, [r1,62]
ldr r63, [r1,63]
/* Load status register */
ldr r0, [r1,64]
movts status, r0
/* Load config register */
ldr r0, [r1,65]
movts config, r0
/* Load interrupt return address register */
ldr r0,[r1,66]
movts iret, r0
ldr r0,[r1]
ldr r1,[r1,1]
/* Enable interrupts and return */
gie
jr lr
SYM(_CPU_Context_restore):
mov r1, r0
b _restore
nop
/* No FP support for Epiphany yet */
SYM(_CPU_Context_restore_fp):
nop
SYM(_CPU_Context_save_fp):
nop

304
cpukit/score/cpu/epiphany/epiphany-exception-handler.S Normal file
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@@ -0,0 +1,304 @@
/**
* @file
*
* @ingroup ScoreCPU
*
* @brief Epiphany exception support implementation.
*/
/*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/score/cpu.h>
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
EXTERN(bsp_start_vector_table_begin)
EXTERN(_Thread_Dispatch)
PUBLIC(ISR_Handler)
.section .text, "ax"
.align 4
TYPE_FUNC(ISR_Handler)
SYM(ISR_Handler):
/* Reserve space for CPU_Exception_frame */
sub sp, sp, #(CPU_EXCEPTION_FRAME_SIZE)
str r0, [sp]
str r1, [sp,1]
str r2, [sp,2]
str r3, [sp,3]
str r4, [sp,4]
str r5, [sp,5]
str r6, [sp,6]
str r7, [sp,7]
str r8, [sp,8]
str r9, [sp,9]
str r10, [sp,10]
str fp, [sp,11]
str r12, [sp,12]
/* Save interrupted task stack pointer */
add r1, sp, #(CPU_EXCEPTION_FRAME_SIZE + 8)
str r1,[sp,13]
str lr, [sp,14]
str r15, [sp,15]
str r16, [sp,16]
str r17, [sp,17]
str r18, [sp,18]
str r19, [sp,19]
str r20, [sp,20]
str r21, [sp,21]
str r22, [sp,22]
str r23, [sp,23]
str r24, [sp,24]
str r25, [sp,25]
str r26, [sp,26]
str r27, [sp,27]
str r28, [sp,28]
str r29, [sp,29]
str r30, [sp,30]
str r31, [sp,31]
str r32, [sp,32]
str r33, [sp,33]
str r34, [sp,34]
str r35, [sp,35]
str r36, [sp,36]
str r37, [sp,37]
str r38, [sp,38]
str r39, [sp,39]
str r40, [sp,40]
str r41, [sp,41]
str r42, [sp,42]
str r43, [sp,43]
str r44, [sp,44]
str r45, [sp,45]
str r46, [sp,46]
str r47, [sp,47]
str r48, [sp,48]
str r49, [sp,49]
str r50, [sp,50]
str r51, [sp,51]
str r52, [sp,52]
str r53, [sp,53]
str r54, [sp,54]
str r55, [sp,55]
str r56, [sp,56]
str r57, [sp,57]
str r58, [sp,58]
str r59, [sp,59]
str r60, [sp,60]
str r61, [sp,61]
/* r62 and r63 are saved from start.S interrupt entry
* and hold vector number and _ISR_Handler address repsectively.
*/
/* Save status register */
movfs r1,status
str r1, [sp,62]
/* Save config register */
movfs r1,config
str r1, [sp,63]
/* Save interrupt return address register */
movfs r1,iret
str r1, [sp,64]
mov r33, %low(__Per_CPU_Information)
movt r33, %high(__Per_CPU_Information)
add r6, r33, #(PER_CPU_ISR_NEST_LEVEL)
add r8, r33, #(PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)
/* Increment nesting level and disable thread dispatch */
ldr r5, [r6]
ldr r7, [r8]
add r5, r5, #1
add r7, r7, #1
str r5, [r6]
str r7, [r8]
/* Keep sp (Exception frame address) in r32 - Callee saved */
mov r32, sp
/* Keep __Per_CPU_Information address in r33 - Callee saved */
mov r33, r18
/* Call the exception handler from vector table.
* First function arg for C handler is vector number,
* and the second is a pointer to exception frame.
*/
mov r0, r62
mov r1, sp
mov r27, r62
lsl r27, r27, #2
mov r26, %low(_bsp_start_vector_table_begin)
movt r15, #0
add r27, r27, r26
ldr r27, [r27]
/* Do not switch stacks if we are in a nested interrupt. At
* this point r5 should be holding ISR_NEST_LEVEL value.
*/
sub r37, r5, #1
bgtu jump_to_c_handler
/* Switch to RTEMS dedicated interrupt stack */
add sp, r18, #(PER_CPU_INTERRUPT_STACK_HIGH)
ldr sp, [sp]
jump_to_c_handler:
jalr r27
/* Switch back to the interrupted task stack */
mov sp, r32
/* Get the address of __Per_CPU_Information */
mov r18, r33
/* Decrement nesting level and enable multitasking */
add r6, r18, #(PER_CPU_ISR_NEST_LEVEL)
add r8, r18, #(PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)
ldr r5, [r6]
ldr r7, [r8]
sub r5, r5, #1
sub r7, r7, #1
str r5, [r6]
str r7, [r8]
/* Check if _ISR_Nest_level > 0 */
sub r37, r5, #0
bgtu exception_frame_restore
/* Check if _Thread_Dispatch_disable_level > 0 */
sub r37, r7, #0
bgtu exception_frame_restore
/* Check if dispatch needed */
add r31, r18, #(PER_CPU_DISPATCH_NEEDED)
ldr r31, [r31]
sub r35, r31, #0
beq exception_frame_restore
mov r35, %low(__Thread_Dispatch)
movt r35, %high(__Thread_Dispatch)
jalr r35
exception_frame_restore:
ldr r1, [sp,1]
ldr r2, [sp,2]
ldr r3, [sp,3]
ldr r4, [sp,4]
ldr r5, [sp,5]
ldr r6, [sp,6]
ldr r7, [sp,7]
ldr r8, [sp,8]
ldr r9, [sp,9]
ldr r10, [sp,10]
ldr fp, [sp,11]
ldr r12, [sp,12]
ldr lr, [sp,14]
ldr r15, [sp,15]
ldr r16, [sp,16]
ldr r17, [sp,17]
ldr r18, [sp,18]
ldr r19, [sp,19]
ldr r20, [sp,20]
ldr r21, [sp,21]
ldr r22, [sp,22]
ldr r23, [sp,23]
ldr r24, [sp,24]
ldr r25, [sp,25]
ldr r26, [sp,26]
ldr r27, [sp,27]
ldr r28, [sp,28]
ldr r29, [sp,29]
ldr r30, [sp,30]
ldr r31, [sp,31]
ldr r32, [sp,32]
ldr r34, [sp,34]
ldr r36, [sp,36]
ldr r38, [sp,38]
ldr r39, [sp,39]
ldr r40, [sp,40]
ldr r41, [sp,41]
ldr r42, [sp,42]
ldr r43, [sp,43]
ldr r44, [sp,44]
ldr r45, [sp,45]
ldr r46, [sp,46]
ldr r47, [sp,47]
ldr r48, [sp,48]
ldr r49, [sp,49]
ldr r50, [sp,50]
ldr r51, [sp,51]
ldr r52, [sp,52]
ldr r53, [sp,53]
ldr r54, [sp,54]
ldr r55, [sp,55]
ldr r56, [sp,56]
ldr r57, [sp,57]
ldr r58, [sp,58]
ldr r59, [sp,59]
ldr r60, [sp,60]
ldr r61, [sp,61]
/* Restore status register */
ldr r0,[sp,62]
movts status, r0
/* Restore config register */
ldr r0, [sp,63]
movts config, r0
/* Restore interrupt return address register */
ldr r0, [sp,64]
movts iret, r0
ldr r0,[sp]
/* Restore interrupted task's stack pointer */
ldr sp, [sp,13]
/* r62 and r63 are saved from start.S interrupt entry
* and hold vector number and _ISR_Handler address repsectively.
*/
ldr r62, [sp, -8]
ldr r63, [sp, -4]
/* return from interrupt */
rti

53
cpukit/score/cpu/epiphany/preinstall.am Normal file
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## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES += $(PREINSTALL_FILES)
$(PROJECT_INCLUDE)/rtems/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
$(PROJECT_INCLUDE)/rtems/score/epiphany.h: rtems/score/epiphany.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/epiphany.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/epiphany.h
$(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h: rtems/score/epiphany-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/epiphany-utility.h

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/**
* @file rtems/asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*/
/*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
*
* COPYRIGHT (c) 1994-1997.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __EPIPHANY_ASM_H
#define __EPIPHANY_ASM_H
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/cpuopts.h>
#include <rtems/score/epiphany.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .global SYM (sym)
#define EXTERN(sym) .extern SYM (sym)
#define TYPE_FUNC(sym) .type SYM (sym), %function
#endif

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/**
* @file
*
* @brief Epiphany Assembly File
*
* Very loose template for an include file for the cpu_asm.? file
* if it is implemented as a ".S" file (preprocessed by cpp) instead
* of a ".s" file (preprocessed by gm4 or gasp).
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef _RTEMS_SCORE_CPU_ASM_H
#define _RTEMS_SCORE_CPU_ASM_H
/* pull in the generated offsets */
/*
#include <rtems/score/offsets.h>
*/
/*
* Hardware General Registers
*/
/* put something here */
/*
* Hardware Floating Point Registers
*/
/* put something here */
/*
* Hardware Control Registers
*/
/* put something here */
/*
* Calling Convention
*/
/* put something here */
/*
* Temporary registers
*/
/* put something here */
/*
* Floating Point Registers - SW Conventions
*/
/* put something here */
/*
* Temporary floating point registers
*/
/* put something here */
#endif
/* end of file */

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/*
* COPYRIGHT (c) 2012-2013 Deng Hengyi.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
#define _RTEMS_SCORE_ATOMIC_CPU_H
#include <rtems/score/cpustdatomic.h>
#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */

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/**
* @file
*
* @ingroup ScoreCPU
*
* @brief This include file contains macros pertaining to the
* Epiphany processor family.
*/
/*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _EPIPHANY_UTILITY_H
#define _EPIPHANY_UTILITY_H
/* eCore IRQs */
typedef enum
{
START,
SW_EXCEPTION,
MEM_FAULT,
TIMER0,
TIMER1,
SMP_MESSAGE,
DMA0,
DMA1,
SER,
} EPIPHANY_IRQ_PER_CORE_T;
/* Per-core IO mapped register addresses
* @see Epiphany architecture reference.
*/
#define EPIPHANY_PER_CORE_REG_CONFIG 0xF0400
#define EPIPHANY_PER_CORE_REG_STATUS 0xF0404
#define EPIPHANY_PER_CORE_REG_PC 0xF0408
#define EPIPHANY_PER_CORE_REG_DEBUGSTATUS 0xF040C
#define EPIPHANY_PER_CORE_REG_LC 0xF0414
#define EPIPHANY_PER_CORE_REG_LS 0xF0418
#define EPIPHANY_PER_CORE_REG_LE 0xF041C
#define EPIPHANY_PER_CORE_REG_IRET 0xF0420
#define EPIPHANY_PER_CORE_REG_IMASK 0xF0424
#define EPIPHANY_PER_CORE_REG_ILAT 0xF0428
#define EPIPHANY_PER_CORE_REG_ILATST 0xF042C
#define EPIPHANY_PER_CORE_REG_ILATCL 0xF0430
#define EPIPHANY_PER_CORE_REG_IPEND 0xF0434
#define EPIPHANY_PER_CORE_REG_FSTATUS 0xF0440
#define EPIPHANY_PER_CORE_REG_DEBUGCMD 0xF0448
#define EPIPHANY_PER_CORE_REG_RESETCORE 0xF070C
/* Event timer registers */
#define EPIPHANY_PER_CORE_REG_CTIMER0 0xF0438
#define EPIPHANY_PER_CORE_REG_CTIMER1 0xF043C
/* Processor control registers */
#define EPIPHANY_PER_CORE_REG_MEMSTATUS 0xF0604
#define EPIPHANY_PER_CORE_REG_MEMPROTECT 0xF0608
/* DMA Registers */
#define EPIPHANY_PER_CORE_REG_DMA0CONFIG 0xF0500
#define EPIPHANY_PER_CORE_REG_DMA0STRIDE 0xF0504
#define EPIPHANY_PER_CORE_REG_DMA0COUNT 0xF0508
#define EPIPHANY_PER_CORE_REG_DMA0SRCADDR 0xF050C
#define EPIPHANY_PER_CORE_REG_DMA0DSTADDR 0xF0510
#define EPIPHANY_PER_CORE_REG_DMA0AUTO0 0xF0514
#define EPIPHANY_PER_CORE_REG_DMA0AUTO1 0xF0518
#define EPIPHANY_PER_CORE_REG_DMA0STATUS 0xF051C
#define EPIPHANY_PER_CORE_REG_DMA1CONFIG 0xF0520
#define EPIPHANY_PER_CORE_REG_DMA1STRIDE 0xF0524
#define EPIPHANY_PER_CORE_REG_DMA1COUNT 0xF0528
#define EPIPHANY_PER_CORE_REG_DMA1SRCADDR 0xF052C
#define EPIPHANY_PER_CORE_REG_DMA1DSTADDR 0xF0530
#define EPIPHANY_PER_CORE_REG_DMA1AUTO0 0xF0534
#define EPIPHANY_PER_CORE_REG_DMA1AUTO1 0xF0538
#define EPIPHANY_PER_CORE_REG_DMA1STATUS 0xF053C
/* Mesh Node Control Registers */
#define EPIPHANY_PER_CORE_REG_MESHCONFIG 0xF0700
#define EPIPHANY_PER_CORE_REG_COREID 0xF0704
#define EPIPHANY_PER_CORE_REG_MULTICAST 0xF0708
#define EPIPHANY_PER_CORE_REG_CMESHROUTE 0xF0710
#define EPIPHANY_PER_CORE_REG_XMESHROUTE 0xF0714
#define EPIPHANY_PER_CORE_REG_RMESHROUTE 0xF0718
/* This macros constructs an address space of epiphany cores
* from their IDs.
*/
#define EPIPHANY_COREID_TO_MSB_ADDR(id) (id) << 20
/* Construct a complete/absolute IO mapped address register from
* core ID and register name
*/
#define EPIPHANY_GET_REG_ABSOLUTE_ADDR(coreid, reg) \
(EPIPHANY_COREID_TO_MSB_ADDR(coreid) | (reg))
#define EPIPHANY_REG(reg) (uint32_t *) (reg)
/* Read register with its absolute address */
static inline uint32_t read_epiphany_reg(volatile uint32_t reg_addr)
{
return *(EPIPHANY_REG(reg_addr));
}
/* Write register with its abolute address */
static inline void write_epiphany_reg(volatile uint32_t reg_addr, uint32_t val)
{
*(EPIPHANY_REG(reg_addr)) = val;
}
/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses
* linear IDs. The following function converts RTEMS linear IDs to
* Epiphany corresponding ones
*/
static const uint32_t map[16] =
{
0x808, 0x809, 0x80A, 0x80B,
0x848, 0x849, 0x84A, 0x84B,
0x888, 0x889, 0x88A, 0x88B,
0x8C8, 0x8C9, 0x8CA, 0x8CB
};
static inline uint32_t rtems_coreid_to_epiphany_map(uint32_t rtems_id)
{
return map[rtems_id];
}
/* Epiphany uses 12 bits for defining core IDs, while RTEMS uses
* linear IDs. The following function is used to map Epiphany IDs to
* RTEMS linear IDs.
*/
static inline uint32_t epiphany_coreid_to_rtems_map(uint32_t epiphany_id)
{
register uint32_t coreid asm ("r17") = epiphany_id;
/* Mapping from Epiphany IDs to 0-16 IDs macro */
__asm__ __volatile__(" \
movfs r17, coreid \
mov r19, #0x003 \
mov r20, #0x0F0 \
and r19, r17, r19 \
and r20, r17, r20 \
lsr r20, r20, #4 \
add r17, r19, r20 \
");
/* coreid or r17 now holds the rtems core id */
return coreid;
}
static inline uint32_t _Epiphany_Get_current_processor()
{
uint32_t coreid;
asm volatile ("movfs %0, coreid" : "=r" (coreid): );
return epiphany_coreid_to_rtems_map(coreid);
}
#endif /* _EPIPHANY_UTILITY_H */

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/**
* @file rtems/score/epiphany.h
*/
/*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* COPYRIGHT (c) 1989-1999, 2010.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _RTEMS_SCORE_EPIPHANY_H
#define _RTEMS_SCORE_EPIPHANY_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the Epiphany family.
* It does this by setting variables to indicate which
* implementation dependent features are present in a particular
* member of the family.
*
* This is a good place to list all the known CPU models
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
/*
* Define the name of the CPU family and specific model.
*/
#define CPU_NAME "EPIPHANY"
#define CPU_MODEL_NAME "EPIPHANY"
#ifdef __cplusplus
}
#endif
#endif /* _RTEMS_SCORE_EPIPHANY_H */

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/**
* @file
*
* @brief Epiphany Architecture Types API
*/
/*
* Copyright (c) 2015 University of York.
* Hesham ALMatary <hmka501@york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _RTEMS_SCORE_TYPES_H
#define _RTEMS_SCORE_TYPES_H
#include <rtems/score/basedefs.h>
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/**
* @addtogroup ScoreCPU
*/
/**@{**/
/*
* This section defines the basic types for this processor.
*/
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
typedef uint16_t Priority_bit_map_Word;
typedef void epiphany_isr;
typedef void ( *epiphany_isr_entry )( void );
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif