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2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>

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* cpu_asm.S: Fix for CPUs with FPU revision B or C.
This commit is contained in:
Joel Sherrill
2000-11-21 14:03:17 +00:00
parent a1c86a4c51
commit 669a6dc364
4 changed files with 28 additions and 6 deletions
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4
c/src/exec/score/cpu/sparc/ChangeLog
View File

@@ -1,3 +1,7 @@
2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu_asm.S: Fix for CPUs with FPU revision B or C.
2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl> 2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu.c, rtems/cpu/sparc.h: Make floating point optional based * cpu.c, rtems/cpu/sparc.h: Make floating point optional based

13
c/src/exec/score/cpu/sparc/cpu_asm.S
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@@ -11,6 +11,13 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$ * $Id$
*/ */
@@ -490,13 +497,14 @@ dont_switch_stacks:
* when the interrupt handler returns. * when the interrupt handler returns.
*/ */
mov %l0, %g5
and %l3, 0x0ff, %g4
/* This is a fix for ERC32 with FPU rev.B or rev.C */ /* This is a fix for ERC32 with FPU rev.B or rev.C */
#if defined(FPU_REVB) #if defined(FPU_REVB)
mov %l0, %g5
and %l3, 0x0ff, %g4
subcc %g4, 0x08, %g0 subcc %g4, 0x08, %g0
be fpu_revb be fpu_revb
subcc %g4, 0x11, %g0 subcc %g4, 0x11, %g0
@@ -555,7 +563,6 @@ __sparc_fq:
#else #else
mov %l0, %g5
subcc %g4, 0x11, %g0 subcc %g4, 0x11, %g0
bl dont_fix_pil bl dont_fix_pil
subcc %g4, 0x1f, %g0 subcc %g4, 0x1f, %g0

4
cpukit/score/cpu/sparc/ChangeLog
View File

@@ -1,3 +1,7 @@
2000-11-21 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu_asm.S: Fix for CPUs with FPU revision B or C.
2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl> 2000-11-14 Jiri Gaisler <jgais@ws.estec.esa.nl>
* cpu.c, rtems/cpu/sparc.h: Make floating point optional based * cpu.c, rtems/cpu/sparc.h: Make floating point optional based

13
cpukit/score/cpu/sparc/cpu_asm.S
View File

@@ -11,6 +11,13 @@
* found in the file LICENSE in this distribution or at * found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$ * $Id$
*/ */
@@ -490,13 +497,14 @@ dont_switch_stacks:
* when the interrupt handler returns. * when the interrupt handler returns.
*/ */
mov %l0, %g5
and %l3, 0x0ff, %g4
/* This is a fix for ERC32 with FPU rev.B or rev.C */ /* This is a fix for ERC32 with FPU rev.B or rev.C */
#if defined(FPU_REVB) #if defined(FPU_REVB)
mov %l0, %g5
and %l3, 0x0ff, %g4
subcc %g4, 0x08, %g0 subcc %g4, 0x08, %g0
be fpu_revb be fpu_revb
subcc %g4, 0x11, %g0 subcc %g4, 0x11, %g0
@@ -555,7 +563,6 @@ __sparc_fq:
#else #else
mov %l0, %g5
subcc %g4, 0x11, %g0 subcc %g4, 0x11, %g0
bl dont_fix_pil bl dont_fix_pil
subcc %g4, 0x1f, %g0 subcc %g4, 0x1f, %g0